drm: radeon: Use RADEON_RB3D_DSTCACHE_CTLSTAT instead of RADEON_RB2D_DSTCACHE_CTLSTAT.

The latter seems to be a read-only mirror of the former.

Signed-off-by: Dave Airlie <airlied@linux.ie>

2 files changed, 12 insertions, 7 deletions

diff --git a/drivers/char/drm/radeon_cp.c b/drivers/char/drm/radeon_cp.c
index 3956628b2576..45f8044e9a30 100644
--- a/drivers/char/drm/radeon_cp.c
+++ b/drivers/char/drm/radeon_cp.c
@@ -864,13 +864,13 @@ static int radeon_do_pixcache_flush(drm_radeon_private_t * dev_priv)
 
         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 
-        tmp = RADEON_READ(RADEON_RB2D_DSTCACHE_CTLSTAT);
-        tmp |= RADEON_RB2D_DC_FLUSH_ALL;
-        RADEON_WRITE(RADEON_RB2D_DSTCACHE_CTLSTAT, tmp);
+        tmp = RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT);
+        tmp |= RADEON_RB3D_DC_FLUSH_ALL;
+        RADEON_WRITE(RADEON_RB3D_DSTCACHE_CTLSTAT, tmp);
 
         for (i = 0; i < dev_priv->usec_timeout; i++) {
-                if (!(RADEON_READ(RADEON_RB2D_DSTCACHE_CTLSTAT)
-                      & RADEON_RB2D_DC_BUSY)) {
+                if (!(RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT)
+                      & RADEON_RB3D_DC_BUSY)) {
                         return 0;
                 }
                 DRM_UDELAY(1);
diff --git a/drivers/char/drm/radeon_drv.h b/drivers/char/drm/radeon_drv.h
index b54b8967dcd2..2f51d5147730 100644
--- a/drivers/char/drm/radeon_drv.h
+++ b/drivers/char/drm/radeon_drv.h
@@ -545,6 +545,11 @@ extern int r300_do_cp_cmdbuf(drm_device_t * dev, DRMFILE filp,
 #       define RADEON_RB3D_ZC_FREE              (1 << 2)
 #       define RADEON_RB3D_ZC_FLUSH_ALL         0x5
 #       define RADEON_RB3D_ZC_BUSY              (1 << 31)
+#define RADEON_RB3D_DSTCACHE_CTLSTAT    0x325c
+#       define RADEON_RB3D_DC_FLUSH             (3 << 0)
+#       define RADEON_RB3D_DC_FREE              (3 << 2)
+#       define RADEON_RB3D_DC_FLUSH_ALL         0xf
+#       define RADEON_RB3D_DC_BUSY              (1 << 31)
 #define RADEON_RB3D_ZSTENCILCNTL        0x1c2c
 #       define RADEON_Z_TEST_MASK               (7 << 4)
 #       define RADEON_Z_TEST_ALWAYS             (7 << 4)
@@ -987,12 +992,12 @@ do {									\
 } while (0)
 
 #define RADEON_FLUSH_CACHE() do {                                       \
-        OUT_RING( CP_PACKET0( RADEON_RB2D_DSTCACHE_CTLSTAT, 0 ) );      \
+        OUT_RING( CP_PACKET0( RADEON_RB3D_DSTCACHE_CTLSTAT, 0 ) );      \
         OUT_RING( RADEON_RB2D_DC_FLUSH );                               \
 } while (0)
 
 #define RADEON_PURGE_CACHE() do {                                       \
-        OUT_RING( CP_PACKET0( RADEON_RB2D_DSTCACHE_CTLSTAT, 0 ) );      \
+        OUT_RING( CP_PACKET0( RADEON_RB3D_DSTCACHE_CTLSTAT, 0 ) );      \
         OUT_RING( RADEON_RB2D_DC_FLUSH_ALL );                           \
 } while (0)