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authorDave Airlie <airlied@starflyer.(none)>2005-09-25 00:28:13 -0400
committerDave Airlie <airlied@linux.ie>2005-09-25 00:28:13 -0400
commitb5e89ed53ed8d24f83ba1941c07382af00ed238e (patch)
tree747bae7a565f88a2e1d5974776eeb054a932c505 /drivers/char/drm/via_verifier.c
parent99a2657a29e2d623c3568cd86b27cac13fb63140 (diff)
drm: lindent the drm directory.
I've been threatening this for a while, so no point hanging around. This lindents the DRM code which was always really bad in tabbing department. I've also fixed some misnamed files in comments and removed some trailing whitespace. Signed-off-by: Dave Airlie <airlied@linux.ie>
Diffstat (limited to 'drivers/char/drm/via_verifier.c')
-rw-r--r--drivers/char/drm/via_verifier.c483
1 files changed, 259 insertions, 224 deletions
diff --git a/drivers/char/drm/via_verifier.c b/drivers/char/drm/via_verifier.c
index 07923b0c7a97..4ac495f297f7 100644
--- a/drivers/char/drm/via_verifier.c
+++ b/drivers/char/drm/via_verifier.c
@@ -28,7 +28,6 @@
28 * be very slow. 28 * be very slow.
29 */ 29 */
30 30
31
32#include "via_3d_reg.h" 31#include "via_3d_reg.h"
33#include "drmP.h" 32#include "drmP.h"
34#include "drm.h" 33#include "drm.h"
@@ -36,7 +35,7 @@
36#include "via_verifier.h" 35#include "via_verifier.h"
37#include "via_drv.h" 36#include "via_drv.h"
38 37
39typedef enum{ 38typedef enum {
40 state_command, 39 state_command,
41 state_header2, 40 state_header2,
42 state_header1, 41 state_header1,
@@ -45,8 +44,7 @@ typedef enum{
45 state_error 44 state_error
46} verifier_state_t; 45} verifier_state_t;
47 46
48 47typedef enum {
49typedef enum{
50 no_check = 0, 48 no_check = 0,
51 check_for_header2, 49 check_for_header2,
52 check_for_header1, 50 check_for_header1,
@@ -74,16 +72,16 @@ typedef enum{
74 check_for_vertex_count, 72 check_for_vertex_count,
75 check_number_texunits, 73 check_number_texunits,
76 forbidden_command 74 forbidden_command
77}hazard_t; 75} hazard_t;
78 76
79/* 77/*
80 * Associates each hazard above with a possible multi-command 78 * Associates each hazard above with a possible multi-command
81 * sequence. For example an address that is split over multiple 79 * sequence. For example an address that is split over multiple
82 * commands and that needs to be checked at the first command 80 * commands and that needs to be checked at the first command
83 * that does not include any part of the address. 81 * that does not include any part of the address.
84 */ 82 */
85 83
86static drm_via_sequence_t seqs[] = { 84static drm_via_sequence_t seqs[] = {
87 no_sequence, 85 no_sequence,
88 no_sequence, 86 no_sequence,
89 no_sequence, 87 no_sequence,
@@ -110,14 +108,12 @@ static drm_via_sequence_t seqs[] = {
110 tex_address, 108 tex_address,
111 no_sequence 109 no_sequence
112}; 110};
113 111
114typedef struct{ 112typedef struct {
115 unsigned int code; 113 unsigned int code;
116 hazard_t hz; 114 hazard_t hz;
117} hz_init_t; 115} hz_init_t;
118 116
119
120
121static hz_init_t init_table1[] = { 117static hz_init_t init_table1[] = {
122 {0xf2, check_for_header2_err}, 118 {0xf2, check_for_header2_err},
123 {0xf0, check_for_header1_err}, 119 {0xf0, check_for_header1_err},
@@ -169,8 +165,6 @@ static hz_init_t init_table1[] = {
169 {0x7D, check_for_vertex_count} 165 {0x7D, check_for_vertex_count}
170}; 166};
171 167
172
173
174static hz_init_t init_table2[] = { 168static hz_init_t init_table2[] = {
175 {0xf2, check_for_header2_err}, 169 {0xf2, check_for_header2_err},
176 {0xf0, check_for_header1_err}, 170 {0xf0, check_for_header1_err},
@@ -235,49 +229,49 @@ static hz_init_t init_table3[] = {
235 {0xcc, check_for_dummy}, 229 {0xcc, check_for_dummy},
236 {0x00, check_number_texunits} 230 {0x00, check_number_texunits}
237}; 231};
238
239
240static hazard_t table1[256];
241static hazard_t table2[256];
242static hazard_t table3[256];
243
244 232
233static hazard_t table1[256];
234static hazard_t table2[256];
235static hazard_t table3[256];
245 236
246static __inline__ int 237static __inline__ int
247eat_words(const uint32_t **buf, const uint32_t *buf_end, unsigned num_words) 238eat_words(const uint32_t ** buf, const uint32_t * buf_end, unsigned num_words)
248{ 239{
249 if ((*buf - buf_end) >= num_words) { 240 if ((*buf - buf_end) >= num_words) {
250 *buf += num_words; 241 *buf += num_words;
251 return 0; 242 return 0;
252 } 243 }
253 DRM_ERROR("Illegal termination of DMA command buffer\n"); 244 DRM_ERROR("Illegal termination of DMA command buffer\n");
254 return 1; 245 return 1;
255} 246}
256 247
257
258/* 248/*
259 * Partially stolen from drm_memory.h 249 * Partially stolen from drm_memory.h
260 */ 250 */
261 251
262static __inline__ drm_map_t * 252static __inline__ drm_map_t *via_drm_lookup_agp_map(drm_via_state_t * seq,
263via_drm_lookup_agp_map (drm_via_state_t *seq, unsigned long offset, unsigned long size, 253 unsigned long offset,
264 drm_device_t *dev) 254 unsigned long size,
255 drm_device_t * dev)
265{ 256{
266 struct list_head *list; 257 struct list_head *list;
267 drm_map_list_t *r_list; 258 drm_map_list_t *r_list;
268 drm_map_t *map = seq->map_cache; 259 drm_map_t *map = seq->map_cache;
269 260
270 if (map && map->offset <= offset && (offset + size) <= (map->offset + map->size)) { 261 if (map && map->offset <= offset
262 && (offset + size) <= (map->offset + map->size)) {
271 return map; 263 return map;
272 } 264 }
273 265
274 list_for_each(list, &dev->maplist->head) { 266 list_for_each(list, &dev->maplist->head) {
275 r_list = (drm_map_list_t *) list; 267 r_list = (drm_map_list_t *) list;
276 map = r_list->map; 268 map = r_list->map;
277 if (!map) 269 if (!map)
278 continue; 270 continue;
279 if (map->offset <= offset && (offset + size) <= (map->offset + map->size) && 271 if (map->offset <= offset
280 !(map->flags & _DRM_RESTRICTED) && (map->type == _DRM_AGP)) { 272 && (offset + size) <= (map->offset + map->size)
273 && !(map->flags & _DRM_RESTRICTED)
274 && (map->type == _DRM_AGP)) {
281 seq->map_cache = map; 275 seq->map_cache = map;
282 return map; 276 return map;
283 } 277 }
@@ -285,54 +279,60 @@ via_drm_lookup_agp_map (drm_via_state_t *seq, unsigned long offset, unsigned lon
285 return NULL; 279 return NULL;
286} 280}
287 281
288
289/* 282/*
290 * Require that all AGP texture levels reside in the same AGP map which should 283 * Require that all AGP texture levels reside in the same AGP map which should
291 * be mappable by the client. This is not a big restriction. 284 * be mappable by the client. This is not a big restriction.
292 * FIXME: To actually enforce this security policy strictly, drm_rmmap 285 * FIXME: To actually enforce this security policy strictly, drm_rmmap
293 * would have to wait for dma quiescent before removing an AGP map. 286 * would have to wait for dma quiescent before removing an AGP map.
294 * The via_drm_lookup_agp_map call in reality seems to take 287 * The via_drm_lookup_agp_map call in reality seems to take
295 * very little CPU time. 288 * very little CPU time.
296 */ 289 */
297 290
298 291static __inline__ int finish_current_sequence(drm_via_state_t * cur_seq)
299static __inline__ int
300finish_current_sequence(drm_via_state_t *cur_seq)
301{ 292{
302 switch(cur_seq->unfinished) { 293 switch (cur_seq->unfinished) {
303 case z_address: 294 case z_address:
304 DRM_DEBUG("Z Buffer start address is 0x%x\n", cur_seq->z_addr); 295 DRM_DEBUG("Z Buffer start address is 0x%x\n", cur_seq->z_addr);
305 break; 296 break;
306 case dest_address: 297 case dest_address:
307 DRM_DEBUG("Destination start address is 0x%x\n", cur_seq->d_addr); 298 DRM_DEBUG("Destination start address is 0x%x\n",
299 cur_seq->d_addr);
308 break; 300 break;
309 case tex_address: 301 case tex_address:
310 if (cur_seq->agp_texture) { 302 if (cur_seq->agp_texture) {
311 unsigned start = cur_seq->tex_level_lo[cur_seq->texture]; 303 unsigned start =
304 cur_seq->tex_level_lo[cur_seq->texture];
312 unsigned end = cur_seq->tex_level_hi[cur_seq->texture]; 305 unsigned end = cur_seq->tex_level_hi[cur_seq->texture];
313 unsigned long lo=~0, hi=0, tmp; 306 unsigned long lo = ~0, hi = 0, tmp;
314 uint32_t *addr, *pitch, *height, tex; 307 uint32_t *addr, *pitch, *height, tex;
315 unsigned i; 308 unsigned i;
316 309
317 if (end > 9) end = 9; 310 if (end > 9)
318 if (start > 9) start = 9; 311 end = 9;
312 if (start > 9)
313 start = 9;
319 314
320 addr =&(cur_seq->t_addr[tex = cur_seq->texture][start]); 315 addr =
316 &(cur_seq->t_addr[tex = cur_seq->texture][start]);
321 pitch = &(cur_seq->pitch[tex][start]); 317 pitch = &(cur_seq->pitch[tex][start]);
322 height = &(cur_seq->height[tex][start]); 318 height = &(cur_seq->height[tex][start]);
323 319
324 for (i=start; i<= end; ++i) { 320 for (i = start; i <= end; ++i) {
325 tmp = *addr++; 321 tmp = *addr++;
326 if (tmp < lo) lo = tmp; 322 if (tmp < lo)
323 lo = tmp;
327 tmp += (*height++ << *pitch++); 324 tmp += (*height++ << *pitch++);
328 if (tmp > hi) hi = tmp; 325 if (tmp > hi)
326 hi = tmp;
329 } 327 }
330 328
331 if (! via_drm_lookup_agp_map (cur_seq, lo, hi - lo, cur_seq->dev)) { 329 if (!via_drm_lookup_agp_map
332 DRM_ERROR("AGP texture is not in allowed map\n"); 330 (cur_seq, lo, hi - lo, cur_seq->dev)) {
331 DRM_ERROR
332 ("AGP texture is not in allowed map\n");
333 return 2; 333 return 2;
334 } 334 }
335 } 335 }
336 break; 336 break;
337 default: 337 default:
338 break; 338 break;
@@ -341,73 +341,84 @@ finish_current_sequence(drm_via_state_t *cur_seq)
341 return 0; 341 return 0;
342} 342}
343 343
344static __inline__ int 344static __inline__ int
345investigate_hazard( uint32_t cmd, hazard_t hz, drm_via_state_t *cur_seq) 345investigate_hazard(uint32_t cmd, hazard_t hz, drm_via_state_t * cur_seq)
346{ 346{
347 register uint32_t tmp, *tmp_addr; 347 register uint32_t tmp, *tmp_addr;
348 348
349 if (cur_seq->unfinished && (cur_seq->unfinished != seqs[hz])) { 349 if (cur_seq->unfinished && (cur_seq->unfinished != seqs[hz])) {
350 int ret; 350 int ret;
351 if ((ret = finish_current_sequence(cur_seq))) return ret; 351 if ((ret = finish_current_sequence(cur_seq)))
352 return ret;
352 } 353 }
353 354
354 switch(hz) { 355 switch (hz) {
355 case check_for_header2: 356 case check_for_header2:
356 if (cmd == HALCYON_HEADER2) return 1; 357 if (cmd == HALCYON_HEADER2)
358 return 1;
357 return 0; 359 return 0;
358 case check_for_header1: 360 case check_for_header1:
359 if ((cmd & HALCYON_HEADER1MASK) == HALCYON_HEADER1) return 1; 361 if ((cmd & HALCYON_HEADER1MASK) == HALCYON_HEADER1)
362 return 1;
360 return 0; 363 return 0;
361 case check_for_header2_err: 364 case check_for_header2_err:
362 if (cmd == HALCYON_HEADER2) return 1; 365 if (cmd == HALCYON_HEADER2)
366 return 1;
363 DRM_ERROR("Illegal DMA HALCYON_HEADER2 command\n"); 367 DRM_ERROR("Illegal DMA HALCYON_HEADER2 command\n");
364 break; 368 break;
365 case check_for_header1_err: 369 case check_for_header1_err:
366 if ((cmd & HALCYON_HEADER1MASK) == HALCYON_HEADER1) return 1; 370 if ((cmd & HALCYON_HEADER1MASK) == HALCYON_HEADER1)
371 return 1;
367 DRM_ERROR("Illegal DMA HALCYON_HEADER1 command\n"); 372 DRM_ERROR("Illegal DMA HALCYON_HEADER1 command\n");
368 break; 373 break;
369 case check_for_fire: 374 case check_for_fire:
370 if ((cmd & HALCYON_FIREMASK) == HALCYON_FIRECMD) return 1; 375 if ((cmd & HALCYON_FIREMASK) == HALCYON_FIRECMD)
376 return 1;
371 DRM_ERROR("Illegal DMA HALCYON_FIRECMD command\n"); 377 DRM_ERROR("Illegal DMA HALCYON_FIRECMD command\n");
372 break; 378 break;
373 case check_for_dummy: 379 case check_for_dummy:
374 if (HC_DUMMY == cmd) return 0; 380 if (HC_DUMMY == cmd)
381 return 0;
375 DRM_ERROR("Illegal DMA HC_DUMMY command\n"); 382 DRM_ERROR("Illegal DMA HC_DUMMY command\n");
376 break; 383 break;
377 case check_for_dd: 384 case check_for_dd:
378 if (0xdddddddd == cmd) return 0; 385 if (0xdddddddd == cmd)
386 return 0;
379 DRM_ERROR("Illegal DMA 0xdddddddd command\n"); 387 DRM_ERROR("Illegal DMA 0xdddddddd command\n");
380 break; 388 break;
381 case check_z_buffer_addr0: 389 case check_z_buffer_addr0:
382 cur_seq->unfinished = z_address; 390 cur_seq->unfinished = z_address;
383 cur_seq->z_addr = (cur_seq->z_addr & 0xFF000000) | 391 cur_seq->z_addr = (cur_seq->z_addr & 0xFF000000) |
384 (cmd & 0x00FFFFFF); 392 (cmd & 0x00FFFFFF);
385 return 0; 393 return 0;
386 case check_z_buffer_addr1: 394 case check_z_buffer_addr1:
387 cur_seq->unfinished = z_address; 395 cur_seq->unfinished = z_address;
388 cur_seq->z_addr = (cur_seq->z_addr & 0x00FFFFFF) | 396 cur_seq->z_addr = (cur_seq->z_addr & 0x00FFFFFF) |
389 ((cmd & 0xFF) << 24); 397 ((cmd & 0xFF) << 24);
390 return 0; 398 return 0;
391 case check_z_buffer_addr_mode: 399 case check_z_buffer_addr_mode:
392 cur_seq->unfinished = z_address; 400 cur_seq->unfinished = z_address;
393 if ((cmd & 0x0000C000) == 0) return 0; 401 if ((cmd & 0x0000C000) == 0)
402 return 0;
394 DRM_ERROR("Attempt to place Z buffer in system memory\n"); 403 DRM_ERROR("Attempt to place Z buffer in system memory\n");
395 return 2; 404 return 2;
396 case check_destination_addr0: 405 case check_destination_addr0:
397 cur_seq->unfinished = dest_address; 406 cur_seq->unfinished = dest_address;
398 cur_seq->d_addr = (cur_seq->d_addr & 0xFF000000) | 407 cur_seq->d_addr = (cur_seq->d_addr & 0xFF000000) |
399 (cmd & 0x00FFFFFF); 408 (cmd & 0x00FFFFFF);
400 return 0; 409 return 0;
401 case check_destination_addr1: 410 case check_destination_addr1:
402 cur_seq->unfinished = dest_address; 411 cur_seq->unfinished = dest_address;
403 cur_seq->d_addr = (cur_seq->d_addr & 0x00FFFFFF) | 412 cur_seq->d_addr = (cur_seq->d_addr & 0x00FFFFFF) |
404 ((cmd & 0xFF) << 24); 413 ((cmd & 0xFF) << 24);
405 return 0; 414 return 0;
406 case check_destination_addr_mode: 415 case check_destination_addr_mode:
407 cur_seq->unfinished = dest_address; 416 cur_seq->unfinished = dest_address;
408 if ((cmd & 0x0000C000) == 0) return 0; 417 if ((cmd & 0x0000C000) == 0)
409 DRM_ERROR("Attempt to place 3D drawing buffer in system memory\n"); 418 return 0;
410 return 2; 419 DRM_ERROR
420 ("Attempt to place 3D drawing buffer in system memory\n");
421 return 2;
411 case check_texture_addr0: 422 case check_texture_addr0:
412 cur_seq->unfinished = tex_address; 423 cur_seq->unfinished = tex_address;
413 tmp = (cmd >> 24); 424 tmp = (cmd >> 24);
@@ -433,9 +444,11 @@ investigate_hazard( uint32_t cmd, hazard_t hz, drm_via_state_t *cur_seq)
433 case check_texture_addr3: 444 case check_texture_addr3:
434 cur_seq->unfinished = tex_address; 445 cur_seq->unfinished = tex_address;
435 tmp = ((cmd >> 24) - 0x2B); 446 tmp = ((cmd >> 24) - 0x2B);
436 cur_seq->pitch[cur_seq->texture][tmp] = (cmd & 0x00F00000) >> 20; 447 cur_seq->pitch[cur_seq->texture][tmp] =
448 (cmd & 0x00F00000) >> 20;
437 if (!tmp && (cmd & 0x000FFFFF)) { 449 if (!tmp && (cmd & 0x000FFFFF)) {
438 DRM_ERROR("Unimplemented texture level 0 pitch mode.\n"); 450 DRM_ERROR
451 ("Unimplemented texture level 0 pitch mode.\n");
439 return 2; 452 return 2;
440 } 453 }
441 return 0; 454 return 0;
@@ -449,7 +462,7 @@ investigate_hazard( uint32_t cmd, hazard_t hz, drm_via_state_t *cur_seq)
449 cur_seq->unfinished = tex_address; 462 cur_seq->unfinished = tex_address;
450 /* 463 /*
451 * Texture width. We don't care since we have the pitch. 464 * Texture width. We don't care since we have the pitch.
452 */ 465 */
453 return 0; 466 return 0;
454 case check_texture_addr7: 467 case check_texture_addr7:
455 cur_seq->unfinished = tex_address; 468 cur_seq->unfinished = tex_address;
@@ -465,25 +478,26 @@ investigate_hazard( uint32_t cmd, hazard_t hz, drm_via_state_t *cur_seq)
465 cur_seq->unfinished = tex_address; 478 cur_seq->unfinished = tex_address;
466 tmp_addr = &(cur_seq->height[cur_seq->texture][0]); 479 tmp_addr = &(cur_seq->height[cur_seq->texture][0]);
467 tmp_addr[9] = 1 << ((cmd & 0x0000F000) >> 12); 480 tmp_addr[9] = 1 << ((cmd & 0x0000F000) >> 12);
468 tmp_addr[8] = 1 << ((cmd & 0x00000F00) >> 8); 481 tmp_addr[8] = 1 << ((cmd & 0x00000F00) >> 8);
469 tmp_addr[7] = 1 << ((cmd & 0x000000F0) >> 4); 482 tmp_addr[7] = 1 << ((cmd & 0x000000F0) >> 4);
470 tmp_addr[6] = 1 << (cmd & 0x0000000F); 483 tmp_addr[6] = 1 << (cmd & 0x0000000F);
471 return 0; 484 return 0;
472 case check_texture_addr_mode: 485 case check_texture_addr_mode:
473 cur_seq->unfinished = tex_address; 486 cur_seq->unfinished = tex_address;
474 if ( 2 == (tmp = cmd & 0x00000003)) { 487 if (2 == (tmp = cmd & 0x00000003)) {
475 DRM_ERROR("Attempt to fetch texture from system memory.\n"); 488 DRM_ERROR
489 ("Attempt to fetch texture from system memory.\n");
476 return 2; 490 return 2;
477 } 491 }
478 cur_seq->agp_texture = (tmp == 3); 492 cur_seq->agp_texture = (tmp == 3);
479 cur_seq->tex_palette_size[cur_seq->texture] = 493 cur_seq->tex_palette_size[cur_seq->texture] =
480 (cmd >> 16) & 0x000000007; 494 (cmd >> 16) & 0x000000007;
481 return 0; 495 return 0;
482 case check_for_vertex_count: 496 case check_for_vertex_count:
483 cur_seq->vertex_count = cmd & 0x0000FFFF; 497 cur_seq->vertex_count = cmd & 0x0000FFFF;
484 return 0; 498 return 0;
485 case check_number_texunits: 499 case check_number_texunits:
486 cur_seq->multitex = (cmd >> 3) & 1; 500 cur_seq->multitex = (cmd >> 3) & 1;
487 return 0; 501 return 0;
488 default: 502 default:
489 DRM_ERROR("Illegal DMA data: 0x%x\n", cmd); 503 DRM_ERROR("Illegal DMA data: 0x%x\n", cmd);
@@ -492,25 +506,27 @@ investigate_hazard( uint32_t cmd, hazard_t hz, drm_via_state_t *cur_seq)
492 return 2; 506 return 2;
493} 507}
494 508
495
496static __inline__ int 509static __inline__ int
497via_check_prim_list(uint32_t const **buffer, const uint32_t *buf_end, 510via_check_prim_list(uint32_t const **buffer, const uint32_t * buf_end,
498 drm_via_state_t *cur_seq) 511 drm_via_state_t * cur_seq)
499{ 512{
500 drm_via_private_t *dev_priv = (drm_via_private_t *) cur_seq->dev->dev_private; 513 drm_via_private_t *dev_priv =
501 uint32_t a_fire, bcmd , dw_count; 514 (drm_via_private_t *) cur_seq->dev->dev_private;
515 uint32_t a_fire, bcmd, dw_count;
502 int ret = 0; 516 int ret = 0;
503 int have_fire; 517 int have_fire;
504 const uint32_t *buf = *buffer; 518 const uint32_t *buf = *buffer;
505 519
506 while(buf < buf_end) { 520 while (buf < buf_end) {
507 have_fire = 0; 521 have_fire = 0;
508 if ((buf_end - buf) < 2) { 522 if ((buf_end - buf) < 2) {
509 DRM_ERROR("Unexpected termination of primitive list.\n"); 523 DRM_ERROR
524 ("Unexpected termination of primitive list.\n");
510 ret = 1; 525 ret = 1;
511 break; 526 break;
512 } 527 }
513 if ((*buf & HC_ACMD_MASK) != HC_ACMD_HCmdB) break; 528 if ((*buf & HC_ACMD_MASK) != HC_ACMD_HCmdB)
529 break;
514 bcmd = *buf++; 530 bcmd = *buf++;
515 if ((*buf & HC_ACMD_MASK) != HC_ACMD_HCmdA) { 531 if ((*buf & HC_ACMD_MASK) != HC_ACMD_HCmdA) {
516 DRM_ERROR("Expected Vertex List A command, got 0x%x\n", 532 DRM_ERROR("Expected Vertex List A command, got 0x%x\n",
@@ -518,43 +534,56 @@ via_check_prim_list(uint32_t const **buffer, const uint32_t *buf_end,
518 ret = 1; 534 ret = 1;
519 break; 535 break;
520 } 536 }
521 a_fire = *buf++ | HC_HPLEND_MASK | HC_HPMValidN_MASK | HC_HE3Fire_MASK; 537 a_fire =
522 538 *buf++ | HC_HPLEND_MASK | HC_HPMValidN_MASK |
539 HC_HE3Fire_MASK;
540
523 /* 541 /*
524 * How many dwords per vertex ? 542 * How many dwords per vertex ?
525 */ 543 */
526 544
527 if (cur_seq->agp && ((bcmd & (0xF << 11)) == 0)) { 545 if (cur_seq->agp && ((bcmd & (0xF << 11)) == 0)) {
528 DRM_ERROR("Illegal B command vertex data for AGP.\n"); 546 DRM_ERROR("Illegal B command vertex data for AGP.\n");
529 ret = 1; 547 ret = 1;
530 break; 548 break;
531 } 549 }
532 550
533 dw_count = 0; 551 dw_count = 0;
534 if (bcmd & (1 << 7)) dw_count += (cur_seq->multitex) ? 2:1; 552 if (bcmd & (1 << 7))
535 if (bcmd & (1 << 8)) dw_count += (cur_seq->multitex) ? 2:1; 553 dw_count += (cur_seq->multitex) ? 2 : 1;
536 if (bcmd & (1 << 9)) dw_count++; 554 if (bcmd & (1 << 8))
537 if (bcmd & (1 << 10)) dw_count++; 555 dw_count += (cur_seq->multitex) ? 2 : 1;
538 if (bcmd & (1 << 11)) dw_count++; 556 if (bcmd & (1 << 9))
539 if (bcmd & (1 << 12)) dw_count++; 557 dw_count++;
540 if (bcmd & (1 << 13)) dw_count++; 558 if (bcmd & (1 << 10))
541 if (bcmd & (1 << 14)) dw_count++; 559 dw_count++;
542 560 if (bcmd & (1 << 11))
543 while(buf < buf_end) { 561 dw_count++;
562 if (bcmd & (1 << 12))
563 dw_count++;
564 if (bcmd & (1 << 13))
565 dw_count++;
566 if (bcmd & (1 << 14))
567 dw_count++;
568
569 while (buf < buf_end) {
544 if (*buf == a_fire) { 570 if (*buf == a_fire) {
545 if (dev_priv->num_fire_offsets >= VIA_FIRE_BUF_SIZE) { 571 if (dev_priv->num_fire_offsets >=
572 VIA_FIRE_BUF_SIZE) {
546 DRM_ERROR("Fire offset buffer full.\n"); 573 DRM_ERROR("Fire offset buffer full.\n");
547 ret = 1; 574 ret = 1;
548 break; 575 break;
549 } 576 }
550 dev_priv->fire_offsets[dev_priv->num_fire_offsets++] = buf; 577 dev_priv->fire_offsets[dev_priv->
551 have_fire = 1; 578 num_fire_offsets++] =
579 buf;
580 have_fire = 1;
552 buf++; 581 buf++;
553 if (buf < buf_end && *buf == a_fire) 582 if (buf < buf_end && *buf == a_fire)
554 buf++; 583 buf++;
555 break; 584 break;
556 } 585 }
557 if ((*buf == HALCYON_HEADER2) || 586 if ((*buf == HALCYON_HEADER2) ||
558 ((*buf & HALCYON_FIREMASK) == HALCYON_FIRECMD)) { 587 ((*buf & HALCYON_FIREMASK) == HALCYON_FIRECMD)) {
559 DRM_ERROR("Missing Vertex Fire command, " 588 DRM_ERROR("Missing Vertex Fire command, "
560 "Stray Vertex Fire command or verifier " 589 "Stray Vertex Fire command or verifier "
@@ -576,18 +605,14 @@ via_check_prim_list(uint32_t const **buffer, const uint32_t *buf_end,
576 ret = 1; 605 ret = 1;
577 break; 606 break;
578 } 607 }
579 } 608 }
580 *buffer = buf; 609 *buffer = buf;
581 return ret; 610 return ret;
582} 611}
583 612
584
585
586
587
588static __inline__ verifier_state_t 613static __inline__ verifier_state_t
589via_check_header2( uint32_t const **buffer, const uint32_t *buf_end, 614via_check_header2(uint32_t const **buffer, const uint32_t * buf_end,
590 drm_via_state_t *hc_state) 615 drm_via_state_t * hc_state)
591{ 616{
592 uint32_t cmd; 617 uint32_t cmd;
593 int hz_mode; 618 int hz_mode;
@@ -595,17 +620,17 @@ via_check_header2( uint32_t const **buffer, const uint32_t *buf_end,
595 const uint32_t *buf = *buffer; 620 const uint32_t *buf = *buffer;
596 const hazard_t *hz_table; 621 const hazard_t *hz_table;
597 622
598
599 if ((buf_end - buf) < 2) { 623 if ((buf_end - buf) < 2) {
600 DRM_ERROR("Illegal termination of DMA HALCYON_HEADER2 sequence.\n"); 624 DRM_ERROR
625 ("Illegal termination of DMA HALCYON_HEADER2 sequence.\n");
601 return state_error; 626 return state_error;
602 } 627 }
603 buf++; 628 buf++;
604 cmd = (*buf++ & 0xFFFF0000) >> 16; 629 cmd = (*buf++ & 0xFFFF0000) >> 16;
605 630
606 switch(cmd) { 631 switch (cmd) {
607 case HC_ParaType_CmdVdata: 632 case HC_ParaType_CmdVdata:
608 if (via_check_prim_list(&buf, buf_end, hc_state )) 633 if (via_check_prim_list(&buf, buf_end, hc_state))
609 return state_error; 634 return state_error;
610 *buffer = buf; 635 *buffer = buf;
611 return state_command; 636 return state_command;
@@ -650,13 +675,13 @@ via_check_header2( uint32_t const **buffer, const uint32_t *buf_end,
650 */ 675 */
651 676
652 DRM_ERROR("Invalid or unimplemented HALCYON_HEADER2 " 677 DRM_ERROR("Invalid or unimplemented HALCYON_HEADER2 "
653 "DMA subcommand: 0x%x. Previous dword: 0x%x\n", 678 "DMA subcommand: 0x%x. Previous dword: 0x%x\n",
654 cmd, *(buf -2)); 679 cmd, *(buf - 2));
655 *buffer = buf; 680 *buffer = buf;
656 return state_error; 681 return state_error;
657 } 682 }
658 683
659 while(buf < buf_end) { 684 while (buf < buf_end) {
660 cmd = *buf++; 685 cmd = *buf++;
661 if ((hz = hz_table[cmd >> 24])) { 686 if ((hz = hz_table[cmd >> 24])) {
662 if ((hz_mode = investigate_hazard(cmd, hz, hc_state))) { 687 if ((hz_mode = investigate_hazard(cmd, hz, hc_state))) {
@@ -666,7 +691,7 @@ via_check_header2( uint32_t const **buffer, const uint32_t *buf_end,
666 } 691 }
667 return state_error; 692 return state_error;
668 } 693 }
669 } else if (hc_state->unfinished && 694 } else if (hc_state->unfinished &&
670 finish_current_sequence(hc_state)) { 695 finish_current_sequence(hc_state)) {
671 return state_error; 696 return state_error;
672 } 697 }
@@ -679,64 +704,65 @@ via_check_header2( uint32_t const **buffer, const uint32_t *buf_end,
679} 704}
680 705
681static __inline__ verifier_state_t 706static __inline__ verifier_state_t
682via_parse_header2( drm_via_private_t *dev_priv, uint32_t const **buffer, const uint32_t *buf_end, 707via_parse_header2(drm_via_private_t * dev_priv, uint32_t const **buffer,
683 int *fire_count) 708 const uint32_t * buf_end, int *fire_count)
684{ 709{
685 uint32_t cmd; 710 uint32_t cmd;
686 const uint32_t *buf = *buffer; 711 const uint32_t *buf = *buffer;
687 const uint32_t *next_fire; 712 const uint32_t *next_fire;
688 int burst = 0; 713 int burst = 0;
689 714
690 next_fire = dev_priv->fire_offsets[*fire_count]; 715 next_fire = dev_priv->fire_offsets[*fire_count];
691 buf++; 716 buf++;
692 cmd = (*buf & 0xFFFF0000) >> 16; 717 cmd = (*buf & 0xFFFF0000) >> 16;
693 VIA_WRITE(HC_REG_TRANS_SET + HC_REG_BASE, *buf++); 718 VIA_WRITE(HC_REG_TRANS_SET + HC_REG_BASE, *buf++);
694 switch(cmd) { 719 switch (cmd) {
695 case HC_ParaType_CmdVdata: 720 case HC_ParaType_CmdVdata:
696 while ((buf < buf_end) && 721 while ((buf < buf_end) &&
697 (*fire_count < dev_priv->num_fire_offsets) && 722 (*fire_count < dev_priv->num_fire_offsets) &&
698 (*buf & HC_ACMD_MASK) == HC_ACMD_HCmdB ) { 723 (*buf & HC_ACMD_MASK) == HC_ACMD_HCmdB) {
699 while(buf <= next_fire) { 724 while (buf <= next_fire) {
700 VIA_WRITE(HC_REG_TRANS_SPACE + HC_REG_BASE + (burst & 63), *buf++); 725 VIA_WRITE(HC_REG_TRANS_SPACE + HC_REG_BASE +
726 (burst & 63), *buf++);
701 burst += 4; 727 burst += 4;
702 } 728 }
703 if ( ( buf < buf_end ) && ((*buf & HALCYON_FIREMASK) == HALCYON_FIRECMD)) 729 if ((buf < buf_end)
730 && ((*buf & HALCYON_FIREMASK) == HALCYON_FIRECMD))
704 buf++; 731 buf++;
705 732
706 if (++(*fire_count) < dev_priv->num_fire_offsets) 733 if (++(*fire_count) < dev_priv->num_fire_offsets)
707 next_fire = dev_priv->fire_offsets[*fire_count]; 734 next_fire = dev_priv->fire_offsets[*fire_count];
708 } 735 }
709 break; 736 break;
710 default: 737 default:
711 while(buf < buf_end) { 738 while (buf < buf_end) {
712 739
713 if ( *buf == HC_HEADER2 || 740 if (*buf == HC_HEADER2 ||
714 (*buf & HALCYON_HEADER1MASK) == HALCYON_HEADER1 || 741 (*buf & HALCYON_HEADER1MASK) == HALCYON_HEADER1 ||
715 (*buf & VIA_VIDEOMASK) == VIA_VIDEO_HEADER5 || 742 (*buf & VIA_VIDEOMASK) == VIA_VIDEO_HEADER5 ||
716 (*buf & VIA_VIDEOMASK) == VIA_VIDEO_HEADER6 ) break; 743 (*buf & VIA_VIDEOMASK) == VIA_VIDEO_HEADER6)
717 744 break;
718 VIA_WRITE(HC_REG_TRANS_SPACE + HC_REG_BASE + (burst & 63), *buf++); 745
719 burst +=4; 746 VIA_WRITE(HC_REG_TRANS_SPACE + HC_REG_BASE +
747 (burst & 63), *buf++);
748 burst += 4;
720 } 749 }
721 } 750 }
722 *buffer = buf; 751 *buffer = buf;
723 return state_command; 752 return state_command;
724} 753}
725 754
726 755static __inline__ int verify_mmio_address(uint32_t address)
727
728static __inline__ int
729verify_mmio_address( uint32_t address)
730{ 756{
731 if ((address > 0x3FF) && (address < 0xC00 )) { 757 if ((address > 0x3FF) && (address < 0xC00)) {
732 DRM_ERROR("Invalid VIDEO DMA command. " 758 DRM_ERROR("Invalid VIDEO DMA command. "
733 "Attempt to access 3D- or command burst area.\n"); 759 "Attempt to access 3D- or command burst area.\n");
734 return 1; 760 return 1;
735 } else if ((address > 0xCFF) && (address < 0x1300)) { 761 } else if ((address > 0xCFF) && (address < 0x1300)) {
736 DRM_ERROR("Invalid VIDEO DMA command. " 762 DRM_ERROR("Invalid VIDEO DMA command. "
737 "Attempt to access PCI DMA area.\n"); 763 "Attempt to access PCI DMA area.\n");
738 return 1; 764 return 1;
739 } else if (address > 0x13FF ) { 765 } else if (address > 0x13FF) {
740 DRM_ERROR("Invalid VIDEO DMA command. " 766 DRM_ERROR("Invalid VIDEO DMA command. "
741 "Attempt to access VGA registers.\n"); 767 "Attempt to access VGA registers.\n");
742 return 1; 768 return 1;
@@ -745,7 +771,8 @@ verify_mmio_address( uint32_t address)
745} 771}
746 772
747static __inline__ int 773static __inline__ int
748verify_video_tail( uint32_t const **buffer, const uint32_t *buf_end, uint32_t dwords) 774verify_video_tail(uint32_t const **buffer, const uint32_t * buf_end,
775 uint32_t dwords)
749{ 776{
750 const uint32_t *buf = *buffer; 777 const uint32_t *buf = *buffer;
751 778
@@ -762,10 +789,9 @@ verify_video_tail( uint32_t const **buffer, const uint32_t *buf_end, uint32_t dw
762 *buffer = buf; 789 *buffer = buf;
763 return 0; 790 return 0;
764} 791}
765
766 792
767static __inline__ verifier_state_t 793static __inline__ verifier_state_t
768via_check_header1( uint32_t const **buffer, const uint32_t *buf_end ) 794via_check_header1(uint32_t const **buffer, const uint32_t * buf_end)
769{ 795{
770 uint32_t cmd; 796 uint32_t cmd;
771 const uint32_t *buf = *buffer; 797 const uint32_t *buf = *buffer;
@@ -774,21 +800,21 @@ via_check_header1( uint32_t const **buffer, const uint32_t *buf_end )
774 while (buf < buf_end) { 800 while (buf < buf_end) {
775 cmd = *buf; 801 cmd = *buf;
776 if ((cmd > ((0x3FF >> 2) | HALCYON_HEADER1)) && 802 if ((cmd > ((0x3FF >> 2) | HALCYON_HEADER1)) &&
777 (cmd < ((0xC00 >> 2) | HALCYON_HEADER1))) { 803 (cmd < ((0xC00 >> 2) | HALCYON_HEADER1))) {
778 if ((cmd & HALCYON_HEADER1MASK) != HALCYON_HEADER1) 804 if ((cmd & HALCYON_HEADER1MASK) != HALCYON_HEADER1)
779 break; 805 break;
780 DRM_ERROR("Invalid HALCYON_HEADER1 command. " 806 DRM_ERROR("Invalid HALCYON_HEADER1 command. "
781 "Attempt to access 3D- or command burst area.\n"); 807 "Attempt to access 3D- or command burst area.\n");
782 ret = state_error; 808 ret = state_error;
783 break; 809 break;
784 } else if (cmd > ((0xCFF >> 2) | HALCYON_HEADER1)) { 810 } else if (cmd > ((0xCFF >> 2) | HALCYON_HEADER1)) {
785 if ((cmd & HALCYON_HEADER1MASK) != HALCYON_HEADER1) 811 if ((cmd & HALCYON_HEADER1MASK) != HALCYON_HEADER1)
786 break; 812 break;
787 DRM_ERROR("Invalid HALCYON_HEADER1 command. " 813 DRM_ERROR("Invalid HALCYON_HEADER1 command. "
788 "Attempt to access VGA registers.\n"); 814 "Attempt to access VGA registers.\n");
789 ret = state_error; 815 ret = state_error;
790 break; 816 break;
791 } else { 817 } else {
792 buf += 2; 818 buf += 2;
793 } 819 }
794 } 820 }
@@ -797,15 +823,17 @@ via_check_header1( uint32_t const **buffer, const uint32_t *buf_end )
797} 823}
798 824
799static __inline__ verifier_state_t 825static __inline__ verifier_state_t
800via_parse_header1( drm_via_private_t *dev_priv, uint32_t const **buffer, const uint32_t *buf_end ) 826via_parse_header1(drm_via_private_t * dev_priv, uint32_t const **buffer,
827 const uint32_t * buf_end)
801{ 828{
802 register uint32_t cmd; 829 register uint32_t cmd;
803 const uint32_t *buf = *buffer; 830 const uint32_t *buf = *buffer;
804 831
805 while (buf < buf_end) { 832 while (buf < buf_end) {
806 cmd = *buf; 833 cmd = *buf;
807 if ((cmd & HALCYON_HEADER1MASK) != HALCYON_HEADER1) break; 834 if ((cmd & HALCYON_HEADER1MASK) != HALCYON_HEADER1)
808 VIA_WRITE( (cmd & ~HALCYON_HEADER1MASK) << 2, *++buf); 835 break;
836 VIA_WRITE((cmd & ~HALCYON_HEADER1MASK) << 2, *++buf);
809 buf++; 837 buf++;
810 } 838 }
811 *buffer = buf; 839 *buffer = buf;
@@ -813,7 +841,7 @@ via_parse_header1( drm_via_private_t *dev_priv, uint32_t const **buffer, const u
813} 841}
814 842
815static __inline__ verifier_state_t 843static __inline__ verifier_state_t
816via_check_vheader5( uint32_t const **buffer, const uint32_t *buf_end ) 844via_check_vheader5(uint32_t const **buffer, const uint32_t * buf_end)
817{ 845{
818 uint32_t data; 846 uint32_t data;
819 const uint32_t *buf = *buffer; 847 const uint32_t *buf = *buffer;
@@ -836,41 +864,41 @@ via_check_vheader5( uint32_t const **buffer, const uint32_t *buf_end )
836 DRM_ERROR("Illegal header5 header data\n"); 864 DRM_ERROR("Illegal header5 header data\n");
837 return state_error; 865 return state_error;
838 } 866 }
839 if (eat_words(&buf, buf_end, data)) 867 if (eat_words(&buf, buf_end, data))
840 return state_error; 868 return state_error;
841 if ((data & 3) && verify_video_tail(&buf, buf_end, 4 - (data & 3))) 869 if ((data & 3) && verify_video_tail(&buf, buf_end, 4 - (data & 3)))
842 return state_error; 870 return state_error;
843 *buffer = buf; 871 *buffer = buf;
844 return state_command; 872 return state_command;
845 873
846} 874}
847 875
848static __inline__ verifier_state_t 876static __inline__ verifier_state_t
849via_parse_vheader5( drm_via_private_t *dev_priv, uint32_t const **buffer, const uint32_t *buf_end ) 877via_parse_vheader5(drm_via_private_t * dev_priv, uint32_t const **buffer,
878 const uint32_t * buf_end)
850{ 879{
851 uint32_t addr, count, i; 880 uint32_t addr, count, i;
852 const uint32_t *buf = *buffer; 881 const uint32_t *buf = *buffer;
853 882
854 addr = *buf++ & ~VIA_VIDEOMASK; 883 addr = *buf++ & ~VIA_VIDEOMASK;
855 i = count = *buf; 884 i = count = *buf;
856 buf += 3; 885 buf += 3;
857 while(i--) { 886 while (i--) {
858 VIA_WRITE(addr, *buf++); 887 VIA_WRITE(addr, *buf++);
859 } 888 }
860 if (count & 3) buf += 4 - (count & 3); 889 if (count & 3)
890 buf += 4 - (count & 3);
861 *buffer = buf; 891 *buffer = buf;
862 return state_command; 892 return state_command;
863} 893}
864
865 894
866static __inline__ verifier_state_t 895static __inline__ verifier_state_t
867via_check_vheader6( uint32_t const **buffer, const uint32_t *buf_end ) 896via_check_vheader6(uint32_t const **buffer, const uint32_t * buf_end)
868{ 897{
869 uint32_t data; 898 uint32_t data;
870 const uint32_t *buf = *buffer; 899 const uint32_t *buf = *buffer;
871 uint32_t i; 900 uint32_t i;
872 901
873
874 if (buf_end - buf < 4) { 902 if (buf_end - buf < 4) {
875 DRM_ERROR("Illegal termination of video header6 command\n"); 903 DRM_ERROR("Illegal termination of video header6 command\n");
876 return state_error; 904 return state_error;
@@ -889,7 +917,7 @@ via_check_vheader6( uint32_t const **buffer, const uint32_t *buf_end )
889 DRM_ERROR("Illegal termination of video header6 command\n"); 917 DRM_ERROR("Illegal termination of video header6 command\n");
890 return state_error; 918 return state_error;
891 } 919 }
892 for (i=0; i<data; ++i) { 920 for (i = 0; i < data; ++i) {
893 if (verify_mmio_address(*buf++)) 921 if (verify_mmio_address(*buf++))
894 return state_error; 922 return state_error;
895 buf++; 923 buf++;
@@ -899,42 +927,42 @@ via_check_vheader6( uint32_t const **buffer, const uint32_t *buf_end )
899 return state_error; 927 return state_error;
900 *buffer = buf; 928 *buffer = buf;
901 return state_command; 929 return state_command;
902} 930}
903 931
904static __inline__ verifier_state_t 932static __inline__ verifier_state_t
905via_parse_vheader6( drm_via_private_t *dev_priv, uint32_t const **buffer, const uint32_t *buf_end ) 933via_parse_vheader6(drm_via_private_t * dev_priv, uint32_t const **buffer,
934 const uint32_t * buf_end)
906{ 935{
907 936
908 uint32_t addr, count, i; 937 uint32_t addr, count, i;
909 const uint32_t *buf = *buffer; 938 const uint32_t *buf = *buffer;
910 939
911 i = count = *++buf; 940 i = count = *++buf;
912 buf += 3; 941 buf += 3;
913 while(i--) { 942 while (i--) {
914 addr = *buf++; 943 addr = *buf++;
915 VIA_WRITE(addr, *buf++); 944 VIA_WRITE(addr, *buf++);
916 } 945 }
917 count <<= 1; 946 count <<= 1;
918 if (count & 3) buf += 4 - (count & 3); 947 if (count & 3)
948 buf += 4 - (count & 3);
919 *buffer = buf; 949 *buffer = buf;
920 return state_command; 950 return state_command;
921} 951}
922
923
924 952
925int 953int
926via_verify_command_stream(const uint32_t * buf, unsigned int size, drm_device_t *dev, 954via_verify_command_stream(const uint32_t * buf, unsigned int size,
927 int agp) 955 drm_device_t * dev, int agp)
928{ 956{
929 957
930 drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private; 958 drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private;
931 drm_via_state_t *hc_state = &dev_priv->hc_state; 959 drm_via_state_t *hc_state = &dev_priv->hc_state;
932 drm_via_state_t saved_state = *hc_state; 960 drm_via_state_t saved_state = *hc_state;
933 uint32_t cmd; 961 uint32_t cmd;
934 const uint32_t *buf_end = buf + ( size >> 2 ); 962 const uint32_t *buf_end = buf + (size >> 2);
935 verifier_state_t state = state_command; 963 verifier_state_t state = state_command;
936 int pro_group_a = dev_priv->pro_group_a; 964 int pro_group_a = dev_priv->pro_group_a;
937 965
938 hc_state->dev = dev; 966 hc_state->dev = dev;
939 hc_state->unfinished = no_sequence; 967 hc_state->unfinished = no_sequence;
940 hc_state->map_cache = NULL; 968 hc_state->map_cache = NULL;
@@ -946,38 +974,41 @@ via_verify_command_stream(const uint32_t * buf, unsigned int size, drm_device_t
946 974
947 switch (state) { 975 switch (state) {
948 case state_header2: 976 case state_header2:
949 state = via_check_header2( &buf, buf_end, hc_state ); 977 state = via_check_header2(&buf, buf_end, hc_state);
950 break; 978 break;
951 case state_header1: 979 case state_header1:
952 state = via_check_header1( &buf, buf_end ); 980 state = via_check_header1(&buf, buf_end);
953 break; 981 break;
954 case state_vheader5: 982 case state_vheader5:
955 state = via_check_vheader5( &buf, buf_end ); 983 state = via_check_vheader5(&buf, buf_end);
956 break; 984 break;
957 case state_vheader6: 985 case state_vheader6:
958 state = via_check_vheader6( &buf, buf_end ); 986 state = via_check_vheader6(&buf, buf_end);
959 break; 987 break;
960 case state_command: 988 case state_command:
961 if (HALCYON_HEADER2 == (cmd = *buf)) 989 if (HALCYON_HEADER2 == (cmd = *buf))
962 state = state_header2; 990 state = state_header2;
963 else if ((cmd & HALCYON_HEADER1MASK) == HALCYON_HEADER1) 991 else if ((cmd & HALCYON_HEADER1MASK) == HALCYON_HEADER1)
964 state = state_header1; 992 state = state_header1;
965 else if (pro_group_a && (cmd & VIA_VIDEOMASK) == VIA_VIDEO_HEADER5) 993 else if (pro_group_a
994 && (cmd & VIA_VIDEOMASK) == VIA_VIDEO_HEADER5)
966 state = state_vheader5; 995 state = state_vheader5;
967 else if (pro_group_a && (cmd & VIA_VIDEOMASK) == VIA_VIDEO_HEADER6) 996 else if (pro_group_a
997 && (cmd & VIA_VIDEOMASK) == VIA_VIDEO_HEADER6)
968 state = state_vheader6; 998 state = state_vheader6;
969 else { 999 else {
970 DRM_ERROR("Invalid / Unimplemented DMA HEADER command. 0x%x\n", 1000 DRM_ERROR
971 cmd); 1001 ("Invalid / Unimplemented DMA HEADER command. 0x%x\n",
1002 cmd);
972 state = state_error; 1003 state = state_error;
973 } 1004 }
974 break; 1005 break;
975 case state_error: 1006 case state_error:
976 default: 1007 default:
977 *hc_state = saved_state; 1008 *hc_state = saved_state;
978 return DRM_ERR(EINVAL); 1009 return DRM_ERR(EINVAL);
979 } 1010 }
980 } 1011 }
981 if (state == state_error) { 1012 if (state == state_error) {
982 *hc_state = saved_state; 1013 *hc_state = saved_state;
983 return DRM_ERR(EINVAL); 1014 return DRM_ERR(EINVAL);
@@ -985,77 +1016,81 @@ via_verify_command_stream(const uint32_t * buf, unsigned int size, drm_device_t
985 return 0; 1016 return 0;
986} 1017}
987 1018
988int 1019int
989via_parse_command_stream(drm_device_t *dev, const uint32_t * buf, unsigned int size) 1020via_parse_command_stream(drm_device_t * dev, const uint32_t * buf,
1021 unsigned int size)
990{ 1022{
991 1023
992 drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private; 1024 drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private;
993 uint32_t cmd; 1025 uint32_t cmd;
994 const uint32_t *buf_end = buf + ( size >> 2 ); 1026 const uint32_t *buf_end = buf + (size >> 2);
995 verifier_state_t state = state_command; 1027 verifier_state_t state = state_command;
996 int fire_count = 0; 1028 int fire_count = 0;
997 1029
998 while (buf < buf_end) { 1030 while (buf < buf_end) {
999 1031
1000 switch (state) { 1032 switch (state) {
1001 case state_header2: 1033 case state_header2:
1002 state = via_parse_header2( dev_priv, &buf, buf_end, &fire_count ); 1034 state =
1035 via_parse_header2(dev_priv, &buf, buf_end,
1036 &fire_count);
1003 break; 1037 break;
1004 case state_header1: 1038 case state_header1:
1005 state = via_parse_header1( dev_priv, &buf, buf_end ); 1039 state = via_parse_header1(dev_priv, &buf, buf_end);
1006 break; 1040 break;
1007 case state_vheader5: 1041 case state_vheader5:
1008 state = via_parse_vheader5( dev_priv, &buf, buf_end ); 1042 state = via_parse_vheader5(dev_priv, &buf, buf_end);
1009 break; 1043 break;
1010 case state_vheader6: 1044 case state_vheader6:
1011 state = via_parse_vheader6( dev_priv, &buf, buf_end ); 1045 state = via_parse_vheader6(dev_priv, &buf, buf_end);
1012 break; 1046 break;
1013 case state_command: 1047 case state_command:
1014 if (HALCYON_HEADER2 == (cmd = *buf)) 1048 if (HALCYON_HEADER2 == (cmd = *buf))
1015 state = state_header2; 1049 state = state_header2;
1016 else if ((cmd & HALCYON_HEADER1MASK) == HALCYON_HEADER1) 1050 else if ((cmd & HALCYON_HEADER1MASK) == HALCYON_HEADER1)
1017 state = state_header1; 1051 state = state_header1;
1018 else if ((cmd & VIA_VIDEOMASK) == VIA_VIDEO_HEADER5) 1052 else if ((cmd & VIA_VIDEOMASK) == VIA_VIDEO_HEADER5)
1019 state = state_vheader5; 1053 state = state_vheader5;
1020 else if ((cmd & VIA_VIDEOMASK) == VIA_VIDEO_HEADER6) 1054 else if ((cmd & VIA_VIDEOMASK) == VIA_VIDEO_HEADER6)
1021 state = state_vheader6; 1055 state = state_vheader6;
1022 else { 1056 else {
1023 DRM_ERROR("Invalid / Unimplemented DMA HEADER command. 0x%x\n", 1057 DRM_ERROR
1024 cmd); 1058 ("Invalid / Unimplemented DMA HEADER command. 0x%x\n",
1059 cmd);
1025 state = state_error; 1060 state = state_error;
1026 } 1061 }
1027 break; 1062 break;
1028 case state_error: 1063 case state_error:
1029 default: 1064 default:
1030 return DRM_ERR(EINVAL); 1065 return DRM_ERR(EINVAL);
1031 } 1066 }
1032 } 1067 }
1033 if (state == state_error) { 1068 if (state == state_error) {
1034 return DRM_ERR(EINVAL); 1069 return DRM_ERR(EINVAL);
1035 } 1070 }
1036 return 0; 1071 return 0;
1037} 1072}
1038 1073
1039 1074static void
1040
1041static void
1042setup_hazard_table(hz_init_t init_table[], hazard_t table[], int size) 1075setup_hazard_table(hz_init_t init_table[], hazard_t table[], int size)
1043{ 1076{
1044 int i; 1077 int i;
1045 1078
1046 for(i=0; i<256; ++i) { 1079 for (i = 0; i < 256; ++i) {
1047 table[i] = forbidden_command; 1080 table[i] = forbidden_command;
1048 } 1081 }
1049 1082
1050 for(i=0; i<size; ++i) { 1083 for (i = 0; i < size; ++i) {
1051 table[init_table[i].code] = init_table[i].hz; 1084 table[init_table[i].code] = init_table[i].hz;
1052 } 1085 }
1053} 1086}
1054 1087
1055void 1088void via_init_command_verifier(void)
1056via_init_command_verifier( void )
1057{ 1089{
1058 setup_hazard_table(init_table1, table1, sizeof(init_table1) / sizeof(hz_init_t)); 1090 setup_hazard_table(init_table1, table1,
1059 setup_hazard_table(init_table2, table2, sizeof(init_table2) / sizeof(hz_init_t)); 1091 sizeof(init_table1) / sizeof(hz_init_t));
1060 setup_hazard_table(init_table3, table3, sizeof(init_table3) / sizeof(hz_init_t)); 1092 setup_hazard_table(init_table2, table2,
1093 sizeof(init_table2) / sizeof(hz_init_t));
1094 setup_hazard_table(init_table3, table3,
1095 sizeof(init_table3) / sizeof(hz_init_t));
1061} 1096}