diff options
author | Dave Airlie <airlied@starflyer.(none)> | 2005-09-11 05:55:53 -0400 |
---|---|---|
committer | Dave Airlie <airlied@linux.ie> | 2005-09-11 05:55:53 -0400 |
commit | 9d17601c4e132eee9fe450191f6866fb9fb5a762 (patch) | |
tree | f4bdfbc95a28370ad0bf9f0d0f42a821f5a8ec9d /drivers/char/drm/radeon_state.c | |
parent | 70dfcfea4b728ab26af1a3e0f331cc63a7e3554b (diff) |
drm: update radeon driver to 1.18
Add support for GL_ATI_fragment_shader, new packets R200_EMIT_PP_AFS_0/1,
R200_EMIT_PP_TXCTLALL_0-5 (replaces R200_EMIT_PP_TXFILTER_0-5, 2 more regs)
and R200_EMIT_ATF_TFACTOR (replaces R200_EMIT_TFACTOR_0 (8 consts instead of 6)
From: Roland Scheidegger, David Airlie
Signed-off-by: David Airlie <airlied@linux.ie>
Diffstat (limited to 'drivers/char/drm/radeon_state.c')
-rw-r--r-- | drivers/char/drm/radeon_state.c | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/drivers/char/drm/radeon_state.c b/drivers/char/drm/radeon_state.c index 64a3e3a406ef..c4325f1e2294 100644 --- a/drivers/char/drm/radeon_state.c +++ b/drivers/char/drm/radeon_state.c | |||
@@ -207,6 +207,15 @@ static __inline__ int radeon_check_and_fixup_packets( drm_radeon_private_t *dev_ | |||
207 | case RADEON_EMIT_PP_CUBIC_FACES_1: | 207 | case RADEON_EMIT_PP_CUBIC_FACES_1: |
208 | case RADEON_EMIT_PP_CUBIC_FACES_2: | 208 | case RADEON_EMIT_PP_CUBIC_FACES_2: |
209 | case R200_EMIT_PP_TRI_PERF_CNTL: | 209 | case R200_EMIT_PP_TRI_PERF_CNTL: |
210 | case R200_EMIT_PP_AFS_0: | ||
211 | case R200_EMIT_PP_AFS_1: | ||
212 | case R200_EMIT_ATF_TFACTOR: | ||
213 | case R200_EMIT_PP_TXCTLALL_0: | ||
214 | case R200_EMIT_PP_TXCTLALL_1: | ||
215 | case R200_EMIT_PP_TXCTLALL_2: | ||
216 | case R200_EMIT_PP_TXCTLALL_3: | ||
217 | case R200_EMIT_PP_TXCTLALL_4: | ||
218 | case R200_EMIT_PP_TXCTLALL_5: | ||
210 | /* These packets don't contain memory offsets */ | 219 | /* These packets don't contain memory offsets */ |
211 | break; | 220 | break; |
212 | 221 | ||
@@ -568,6 +577,15 @@ static struct { | |||
568 | { RADEON_PP_CUBIC_FACES_2, 1, "RADEON_PP_CUBIC_FACES_2"}, | 577 | { RADEON_PP_CUBIC_FACES_2, 1, "RADEON_PP_CUBIC_FACES_2"}, |
569 | { RADEON_PP_CUBIC_OFFSET_T2_0, 5, "RADEON_PP_CUBIC_OFFSET_T2_0"}, | 578 | { RADEON_PP_CUBIC_OFFSET_T2_0, 5, "RADEON_PP_CUBIC_OFFSET_T2_0"}, |
570 | { R200_PP_TRI_PERF, 2, "R200_PP_TRI_PERF"}, | 579 | { R200_PP_TRI_PERF, 2, "R200_PP_TRI_PERF"}, |
580 | { R200_PP_AFS_0, 32, "R200_PP_AFS_0"}, /* 85 */ | ||
581 | { R200_PP_AFS_1, 32, "R200_PP_AFS_1"}, | ||
582 | { R200_PP_TFACTOR_0, 8, "R200_ATF_TFACTOR"}, | ||
583 | { R200_PP_TXFILTER_0, 8, "R200_PP_TXCTLALL_0"}, | ||
584 | { R200_PP_TXFILTER_1, 8, "R200_PP_TXCTLALL_1"}, | ||
585 | { R200_PP_TXFILTER_2, 8, "R200_PP_TXCTLALL_2"}, | ||
586 | { R200_PP_TXFILTER_3, 8, "R200_PP_TXCTLALL_3"}, | ||
587 | { R200_PP_TXFILTER_4, 8, "R200_PP_TXCTLALL_4"}, | ||
588 | { R200_PP_TXFILTER_5, 8, "R200_PP_TXCTLALL_5"}, | ||
571 | }; | 589 | }; |
572 | 590 | ||
573 | 591 | ||