diff options
author | Eric Anholt <eric@anholt.net> | 2007-08-25 05:22:43 -0400 |
---|---|---|
committer | Dave Airlie <airlied@optimus.(none)> | 2007-10-14 20:38:19 -0400 |
commit | 20caafa6ecb2487d9b223aa33e7cc704f912a758 (patch) | |
tree | 7df033fdee81305dad0a67ceba79f51ead7c1b8b /drivers/char/drm/radeon_state.c | |
parent | 23fd50450a34f2558070ceabb0bfebc1c9604af5 (diff) |
drm: Remove DRM_ERR OS macro.
This was used to make all ioctl handlers return -errno on linux and errno on
*BSD. Instead, just return -errno in shared code, and flip sign on return f
shared code to *BSD code.
Signed-off-by: Dave Airlie <airlied@linux.ie>
Diffstat (limited to 'drivers/char/drm/radeon_state.c')
-rw-r--r-- | drivers/char/drm/radeon_state.c | 154 |
1 files changed, 77 insertions, 77 deletions
diff --git a/drivers/char/drm/radeon_state.c b/drivers/char/drm/radeon_state.c index 3ddf86f2abf0..4bc0909b226f 100644 --- a/drivers/char/drm/radeon_state.c +++ b/drivers/char/drm/radeon_state.c | |||
@@ -85,7 +85,7 @@ static __inline__ int radeon_check_and_fixup_offset(drm_radeon_private_t * | |||
85 | *offset = off; | 85 | *offset = off; |
86 | return 0; | 86 | return 0; |
87 | } | 87 | } |
88 | return DRM_ERR(EINVAL); | 88 | return -EINVAL; |
89 | } | 89 | } |
90 | 90 | ||
91 | static __inline__ int radeon_check_and_fixup_packets(drm_radeon_private_t * | 91 | static __inline__ int radeon_check_and_fixup_packets(drm_radeon_private_t * |
@@ -99,7 +99,7 @@ static __inline__ int radeon_check_and_fixup_packets(drm_radeon_private_t * | |||
99 | if (radeon_check_and_fixup_offset(dev_priv, filp_priv, | 99 | if (radeon_check_and_fixup_offset(dev_priv, filp_priv, |
100 | &data[(RADEON_RB3D_DEPTHOFFSET - RADEON_PP_MISC) / 4])) { | 100 | &data[(RADEON_RB3D_DEPTHOFFSET - RADEON_PP_MISC) / 4])) { |
101 | DRM_ERROR("Invalid depth buffer offset\n"); | 101 | DRM_ERROR("Invalid depth buffer offset\n"); |
102 | return DRM_ERR(EINVAL); | 102 | return -EINVAL; |
103 | } | 103 | } |
104 | break; | 104 | break; |
105 | 105 | ||
@@ -107,7 +107,7 @@ static __inline__ int radeon_check_and_fixup_packets(drm_radeon_private_t * | |||
107 | if (radeon_check_and_fixup_offset(dev_priv, filp_priv, | 107 | if (radeon_check_and_fixup_offset(dev_priv, filp_priv, |
108 | &data[(RADEON_RB3D_COLOROFFSET - RADEON_PP_CNTL) / 4])) { | 108 | &data[(RADEON_RB3D_COLOROFFSET - RADEON_PP_CNTL) / 4])) { |
109 | DRM_ERROR("Invalid colour buffer offset\n"); | 109 | DRM_ERROR("Invalid colour buffer offset\n"); |
110 | return DRM_ERR(EINVAL); | 110 | return -EINVAL; |
111 | } | 111 | } |
112 | break; | 112 | break; |
113 | 113 | ||
@@ -120,7 +120,7 @@ static __inline__ int radeon_check_and_fixup_packets(drm_radeon_private_t * | |||
120 | if (radeon_check_and_fixup_offset(dev_priv, filp_priv, | 120 | if (radeon_check_and_fixup_offset(dev_priv, filp_priv, |
121 | &data[0])) { | 121 | &data[0])) { |
122 | DRM_ERROR("Invalid R200 texture offset\n"); | 122 | DRM_ERROR("Invalid R200 texture offset\n"); |
123 | return DRM_ERR(EINVAL); | 123 | return -EINVAL; |
124 | } | 124 | } |
125 | break; | 125 | break; |
126 | 126 | ||
@@ -130,7 +130,7 @@ static __inline__ int radeon_check_and_fixup_packets(drm_radeon_private_t * | |||
130 | if (radeon_check_and_fixup_offset(dev_priv, filp_priv, | 130 | if (radeon_check_and_fixup_offset(dev_priv, filp_priv, |
131 | &data[(RADEON_PP_TXOFFSET_0 - RADEON_PP_TXFILTER_0) / 4])) { | 131 | &data[(RADEON_PP_TXOFFSET_0 - RADEON_PP_TXFILTER_0) / 4])) { |
132 | DRM_ERROR("Invalid R100 texture offset\n"); | 132 | DRM_ERROR("Invalid R100 texture offset\n"); |
133 | return DRM_ERR(EINVAL); | 133 | return -EINVAL; |
134 | } | 134 | } |
135 | break; | 135 | break; |
136 | 136 | ||
@@ -147,7 +147,7 @@ static __inline__ int radeon_check_and_fixup_packets(drm_radeon_private_t * | |||
147 | &data[i])) { | 147 | &data[i])) { |
148 | DRM_ERROR | 148 | DRM_ERROR |
149 | ("Invalid R200 cubic texture offset\n"); | 149 | ("Invalid R200 cubic texture offset\n"); |
150 | return DRM_ERR(EINVAL); | 150 | return -EINVAL; |
151 | } | 151 | } |
152 | } | 152 | } |
153 | break; | 153 | break; |
@@ -163,7 +163,7 @@ static __inline__ int radeon_check_and_fixup_packets(drm_radeon_private_t * | |||
163 | &data[i])) { | 163 | &data[i])) { |
164 | DRM_ERROR | 164 | DRM_ERROR |
165 | ("Invalid R100 cubic texture offset\n"); | 165 | ("Invalid R100 cubic texture offset\n"); |
166 | return DRM_ERR(EINVAL); | 166 | return -EINVAL; |
167 | } | 167 | } |
168 | } | 168 | } |
169 | } | 169 | } |
@@ -256,7 +256,7 @@ static __inline__ int radeon_check_and_fixup_packets(drm_radeon_private_t * | |||
256 | 256 | ||
257 | default: | 257 | default: |
258 | DRM_ERROR("Unknown state packet ID %d\n", id); | 258 | DRM_ERROR("Unknown state packet ID %d\n", id); |
259 | return DRM_ERR(EINVAL); | 259 | return -EINVAL; |
260 | } | 260 | } |
261 | 261 | ||
262 | return 0; | 262 | return 0; |
@@ -277,12 +277,12 @@ static __inline__ int radeon_check_and_fixup_packet3(drm_radeon_private_t * | |||
277 | 277 | ||
278 | if ((cmd[0] & 0xc0000000) != RADEON_CP_PACKET3) { | 278 | if ((cmd[0] & 0xc0000000) != RADEON_CP_PACKET3) { |
279 | DRM_ERROR("Not a type 3 packet\n"); | 279 | DRM_ERROR("Not a type 3 packet\n"); |
280 | return DRM_ERR(EINVAL); | 280 | return -EINVAL; |
281 | } | 281 | } |
282 | 282 | ||
283 | if (4 * *cmdsz > cmdbuf->bufsz) { | 283 | if (4 * *cmdsz > cmdbuf->bufsz) { |
284 | DRM_ERROR("Packet size larger than size of data provided\n"); | 284 | DRM_ERROR("Packet size larger than size of data provided\n"); |
285 | return DRM_ERR(EINVAL); | 285 | return -EINVAL; |
286 | } | 286 | } |
287 | 287 | ||
288 | switch(cmd[0] & 0xff00) { | 288 | switch(cmd[0] & 0xff00) { |
@@ -307,7 +307,7 @@ static __inline__ int radeon_check_and_fixup_packet3(drm_radeon_private_t * | |||
307 | /* safe but r200 only */ | 307 | /* safe but r200 only */ |
308 | if (dev_priv->microcode_version != UCODE_R200) { | 308 | if (dev_priv->microcode_version != UCODE_R200) { |
309 | DRM_ERROR("Invalid 3d packet for r100-class chip\n"); | 309 | DRM_ERROR("Invalid 3d packet for r100-class chip\n"); |
310 | return DRM_ERR(EINVAL); | 310 | return -EINVAL; |
311 | } | 311 | } |
312 | break; | 312 | break; |
313 | 313 | ||
@@ -317,7 +317,7 @@ static __inline__ int radeon_check_and_fixup_packet3(drm_radeon_private_t * | |||
317 | if (count > 18) { /* 12 arrays max */ | 317 | if (count > 18) { /* 12 arrays max */ |
318 | DRM_ERROR("Too large payload in 3D_LOAD_VBPNTR (count=%d)\n", | 318 | DRM_ERROR("Too large payload in 3D_LOAD_VBPNTR (count=%d)\n", |
319 | count); | 319 | count); |
320 | return DRM_ERR(EINVAL); | 320 | return -EINVAL; |
321 | } | 321 | } |
322 | 322 | ||
323 | /* carefully check packet contents */ | 323 | /* carefully check packet contents */ |
@@ -330,7 +330,7 @@ static __inline__ int radeon_check_and_fixup_packet3(drm_radeon_private_t * | |||
330 | DRM_ERROR | 330 | DRM_ERROR |
331 | ("Invalid offset (k=%d i=%d) in 3D_LOAD_VBPNTR packet.\n", | 331 | ("Invalid offset (k=%d i=%d) in 3D_LOAD_VBPNTR packet.\n", |
332 | k, i); | 332 | k, i); |
333 | return DRM_ERR(EINVAL); | 333 | return -EINVAL; |
334 | } | 334 | } |
335 | k++; | 335 | k++; |
336 | i++; | 336 | i++; |
@@ -341,7 +341,7 @@ static __inline__ int radeon_check_and_fixup_packet3(drm_radeon_private_t * | |||
341 | DRM_ERROR | 341 | DRM_ERROR |
342 | ("Invalid offset (k=%d i=%d) in 3D_LOAD_VBPNTR packet.\n", | 342 | ("Invalid offset (k=%d i=%d) in 3D_LOAD_VBPNTR packet.\n", |
343 | k, i); | 343 | k, i); |
344 | return DRM_ERR(EINVAL); | 344 | return -EINVAL; |
345 | } | 345 | } |
346 | k++; | 346 | k++; |
347 | i++; | 347 | i++; |
@@ -351,33 +351,33 @@ static __inline__ int radeon_check_and_fixup_packet3(drm_radeon_private_t * | |||
351 | DRM_ERROR | 351 | DRM_ERROR |
352 | ("Malformed 3D_LOAD_VBPNTR packet (k=%d i=%d narrays=%d count+1=%d).\n", | 352 | ("Malformed 3D_LOAD_VBPNTR packet (k=%d i=%d narrays=%d count+1=%d).\n", |
353 | k, i, narrays, count + 1); | 353 | k, i, narrays, count + 1); |
354 | return DRM_ERR(EINVAL); | 354 | return -EINVAL; |
355 | } | 355 | } |
356 | break; | 356 | break; |
357 | 357 | ||
358 | case RADEON_3D_RNDR_GEN_INDX_PRIM: | 358 | case RADEON_3D_RNDR_GEN_INDX_PRIM: |
359 | if (dev_priv->microcode_version != UCODE_R100) { | 359 | if (dev_priv->microcode_version != UCODE_R100) { |
360 | DRM_ERROR("Invalid 3d packet for r200-class chip\n"); | 360 | DRM_ERROR("Invalid 3d packet for r200-class chip\n"); |
361 | return DRM_ERR(EINVAL); | 361 | return -EINVAL; |
362 | } | 362 | } |
363 | if (radeon_check_and_fixup_offset(dev_priv, filp_priv, &cmd[1])) { | 363 | if (radeon_check_and_fixup_offset(dev_priv, filp_priv, &cmd[1])) { |
364 | DRM_ERROR("Invalid rndr_gen_indx offset\n"); | 364 | DRM_ERROR("Invalid rndr_gen_indx offset\n"); |
365 | return DRM_ERR(EINVAL); | 365 | return -EINVAL; |
366 | } | 366 | } |
367 | break; | 367 | break; |
368 | 368 | ||
369 | case RADEON_CP_INDX_BUFFER: | 369 | case RADEON_CP_INDX_BUFFER: |
370 | if (dev_priv->microcode_version != UCODE_R200) { | 370 | if (dev_priv->microcode_version != UCODE_R200) { |
371 | DRM_ERROR("Invalid 3d packet for r100-class chip\n"); | 371 | DRM_ERROR("Invalid 3d packet for r100-class chip\n"); |
372 | return DRM_ERR(EINVAL); | 372 | return -EINVAL; |
373 | } | 373 | } |
374 | if ((cmd[1] & 0x8000ffff) != 0x80000810) { | 374 | if ((cmd[1] & 0x8000ffff) != 0x80000810) { |
375 | DRM_ERROR("Invalid indx_buffer reg address %08X\n", cmd[1]); | 375 | DRM_ERROR("Invalid indx_buffer reg address %08X\n", cmd[1]); |
376 | return DRM_ERR(EINVAL); | 376 | return -EINVAL; |
377 | } | 377 | } |
378 | if (radeon_check_and_fixup_offset(dev_priv, filp_priv, &cmd[2])) { | 378 | if (radeon_check_and_fixup_offset(dev_priv, filp_priv, &cmd[2])) { |
379 | DRM_ERROR("Invalid indx_buffer offset is %08X\n", cmd[2]); | 379 | DRM_ERROR("Invalid indx_buffer offset is %08X\n", cmd[2]); |
380 | return DRM_ERR(EINVAL); | 380 | return -EINVAL; |
381 | } | 381 | } |
382 | break; | 382 | break; |
383 | 383 | ||
@@ -391,7 +391,7 @@ static __inline__ int radeon_check_and_fixup_packet3(drm_radeon_private_t * | |||
391 | if (radeon_check_and_fixup_offset | 391 | if (radeon_check_and_fixup_offset |
392 | (dev_priv, filp_priv, &offset)) { | 392 | (dev_priv, filp_priv, &offset)) { |
393 | DRM_ERROR("Invalid first packet offset\n"); | 393 | DRM_ERROR("Invalid first packet offset\n"); |
394 | return DRM_ERR(EINVAL); | 394 | return -EINVAL; |
395 | } | 395 | } |
396 | cmd[2] = (cmd[2] & 0xffc00000) | offset >> 10; | 396 | cmd[2] = (cmd[2] & 0xffc00000) | offset >> 10; |
397 | } | 397 | } |
@@ -402,7 +402,7 @@ static __inline__ int radeon_check_and_fixup_packet3(drm_radeon_private_t * | |||
402 | if (radeon_check_and_fixup_offset | 402 | if (radeon_check_and_fixup_offset |
403 | (dev_priv, filp_priv, &offset)) { | 403 | (dev_priv, filp_priv, &offset)) { |
404 | DRM_ERROR("Invalid second packet offset\n"); | 404 | DRM_ERROR("Invalid second packet offset\n"); |
405 | return DRM_ERR(EINVAL); | 405 | return -EINVAL; |
406 | } | 406 | } |
407 | cmd[3] = (cmd[3] & 0xffc00000) | offset >> 10; | 407 | cmd[3] = (cmd[3] & 0xffc00000) | offset >> 10; |
408 | } | 408 | } |
@@ -410,7 +410,7 @@ static __inline__ int radeon_check_and_fixup_packet3(drm_radeon_private_t * | |||
410 | 410 | ||
411 | default: | 411 | default: |
412 | DRM_ERROR("Invalid packet type %x\n", cmd[0] & 0xff00); | 412 | DRM_ERROR("Invalid packet type %x\n", cmd[0] & 0xff00); |
413 | return DRM_ERR(EINVAL); | 413 | return -EINVAL; |
414 | } | 414 | } |
415 | 415 | ||
416 | return 0; | 416 | return 0; |
@@ -451,13 +451,13 @@ static int radeon_emit_state(drm_radeon_private_t * dev_priv, | |||
451 | if (radeon_check_and_fixup_offset(dev_priv, filp_priv, | 451 | if (radeon_check_and_fixup_offset(dev_priv, filp_priv, |
452 | &ctx->rb3d_depthoffset)) { | 452 | &ctx->rb3d_depthoffset)) { |
453 | DRM_ERROR("Invalid depth buffer offset\n"); | 453 | DRM_ERROR("Invalid depth buffer offset\n"); |
454 | return DRM_ERR(EINVAL); | 454 | return -EINVAL; |
455 | } | 455 | } |
456 | 456 | ||
457 | if (radeon_check_and_fixup_offset(dev_priv, filp_priv, | 457 | if (radeon_check_and_fixup_offset(dev_priv, filp_priv, |
458 | &ctx->rb3d_coloroffset)) { | 458 | &ctx->rb3d_coloroffset)) { |
459 | DRM_ERROR("Invalid depth buffer offset\n"); | 459 | DRM_ERROR("Invalid depth buffer offset\n"); |
460 | return DRM_ERR(EINVAL); | 460 | return -EINVAL; |
461 | } | 461 | } |
462 | 462 | ||
463 | BEGIN_RING(14); | 463 | BEGIN_RING(14); |
@@ -546,7 +546,7 @@ static int radeon_emit_state(drm_radeon_private_t * dev_priv, | |||
546 | if (radeon_check_and_fixup_offset(dev_priv, filp_priv, | 546 | if (radeon_check_and_fixup_offset(dev_priv, filp_priv, |
547 | &tex[0].pp_txoffset)) { | 547 | &tex[0].pp_txoffset)) { |
548 | DRM_ERROR("Invalid texture offset for unit 0\n"); | 548 | DRM_ERROR("Invalid texture offset for unit 0\n"); |
549 | return DRM_ERR(EINVAL); | 549 | return -EINVAL; |
550 | } | 550 | } |
551 | 551 | ||
552 | BEGIN_RING(9); | 552 | BEGIN_RING(9); |
@@ -566,7 +566,7 @@ static int radeon_emit_state(drm_radeon_private_t * dev_priv, | |||
566 | if (radeon_check_and_fixup_offset(dev_priv, filp_priv, | 566 | if (radeon_check_and_fixup_offset(dev_priv, filp_priv, |
567 | &tex[1].pp_txoffset)) { | 567 | &tex[1].pp_txoffset)) { |
568 | DRM_ERROR("Invalid texture offset for unit 1\n"); | 568 | DRM_ERROR("Invalid texture offset for unit 1\n"); |
569 | return DRM_ERR(EINVAL); | 569 | return -EINVAL; |
570 | } | 570 | } |
571 | 571 | ||
572 | BEGIN_RING(9); | 572 | BEGIN_RING(9); |
@@ -586,7 +586,7 @@ static int radeon_emit_state(drm_radeon_private_t * dev_priv, | |||
586 | if (radeon_check_and_fixup_offset(dev_priv, filp_priv, | 586 | if (radeon_check_and_fixup_offset(dev_priv, filp_priv, |
587 | &tex[2].pp_txoffset)) { | 587 | &tex[2].pp_txoffset)) { |
588 | DRM_ERROR("Invalid texture offset for unit 2\n"); | 588 | DRM_ERROR("Invalid texture offset for unit 2\n"); |
589 | return DRM_ERR(EINVAL); | 589 | return -EINVAL; |
590 | } | 590 | } |
591 | 591 | ||
592 | BEGIN_RING(9); | 592 | BEGIN_RING(9); |
@@ -1668,7 +1668,7 @@ static int radeon_cp_dispatch_texture(DRMFILE filp, | |||
1668 | 1668 | ||
1669 | if (radeon_check_and_fixup_offset(dev_priv, filp_priv, &tex->offset)) { | 1669 | if (radeon_check_and_fixup_offset(dev_priv, filp_priv, &tex->offset)) { |
1670 | DRM_ERROR("Invalid destination offset\n"); | 1670 | DRM_ERROR("Invalid destination offset\n"); |
1671 | return DRM_ERR(EINVAL); | 1671 | return -EINVAL; |
1672 | } | 1672 | } |
1673 | 1673 | ||
1674 | dev_priv->stats.boxes |= RADEON_BOX_TEXTURE_LOAD; | 1674 | dev_priv->stats.boxes |= RADEON_BOX_TEXTURE_LOAD; |
@@ -1711,11 +1711,11 @@ static int radeon_cp_dispatch_texture(DRMFILE filp, | |||
1711 | break; | 1711 | break; |
1712 | default: | 1712 | default: |
1713 | DRM_ERROR("invalid texture format %d\n", tex->format); | 1713 | DRM_ERROR("invalid texture format %d\n", tex->format); |
1714 | return DRM_ERR(EINVAL); | 1714 | return -EINVAL; |
1715 | } | 1715 | } |
1716 | spitch = blit_width >> 6; | 1716 | spitch = blit_width >> 6; |
1717 | if (spitch == 0 && image->height > 1) | 1717 | if (spitch == 0 && image->height > 1) |
1718 | return DRM_ERR(EINVAL); | 1718 | return -EINVAL; |
1719 | 1719 | ||
1720 | texpitch = tex->pitch; | 1720 | texpitch = tex->pitch; |
1721 | if ((texpitch << 22) & RADEON_DST_TILE_MICRO) { | 1721 | if ((texpitch << 22) & RADEON_DST_TILE_MICRO) { |
@@ -1760,8 +1760,8 @@ static int radeon_cp_dispatch_texture(DRMFILE filp, | |||
1760 | if (!buf) { | 1760 | if (!buf) { |
1761 | DRM_DEBUG("radeon_cp_dispatch_texture: EAGAIN\n"); | 1761 | DRM_DEBUG("radeon_cp_dispatch_texture: EAGAIN\n"); |
1762 | if (DRM_COPY_TO_USER(tex->image, image, sizeof(*image))) | 1762 | if (DRM_COPY_TO_USER(tex->image, image, sizeof(*image))) |
1763 | return DRM_ERR(EFAULT); | 1763 | return -EFAULT; |
1764 | return DRM_ERR(EAGAIN); | 1764 | return -EAGAIN; |
1765 | } | 1765 | } |
1766 | 1766 | ||
1767 | /* Dispatch the indirect buffer. | 1767 | /* Dispatch the indirect buffer. |
@@ -1774,7 +1774,7 @@ static int radeon_cp_dispatch_texture(DRMFILE filp, | |||
1774 | do { \ | 1774 | do { \ |
1775 | if (DRM_COPY_FROM_USER(_buf, _data, (_width))) {\ | 1775 | if (DRM_COPY_FROM_USER(_buf, _data, (_width))) {\ |
1776 | DRM_ERROR("EFAULT on pad, %d bytes\n", (_width)); \ | 1776 | DRM_ERROR("EFAULT on pad, %d bytes\n", (_width)); \ |
1777 | return DRM_ERR(EFAULT); \ | 1777 | return -EFAULT; \ |
1778 | } \ | 1778 | } \ |
1779 | } while(0) | 1779 | } while(0) |
1780 | 1780 | ||
@@ -2083,7 +2083,7 @@ static int radeon_surface_alloc(DRM_IOCTL_ARGS) | |||
2083 | sizeof(alloc)); | 2083 | sizeof(alloc)); |
2084 | 2084 | ||
2085 | if (alloc_surface(&alloc, dev_priv, filp) == -1) | 2085 | if (alloc_surface(&alloc, dev_priv, filp) == -1) |
2086 | return DRM_ERR(EINVAL); | 2086 | return -EINVAL; |
2087 | else | 2087 | else |
2088 | return 0; | 2088 | return 0; |
2089 | } | 2089 | } |
@@ -2098,7 +2098,7 @@ static int radeon_surface_free(DRM_IOCTL_ARGS) | |||
2098 | sizeof(memfree)); | 2098 | sizeof(memfree)); |
2099 | 2099 | ||
2100 | if (free_surface(filp, dev_priv, memfree.address)) | 2100 | if (free_surface(filp, dev_priv, memfree.address)) |
2101 | return DRM_ERR(EINVAL); | 2101 | return -EINVAL; |
2102 | else | 2102 | else |
2103 | return 0; | 2103 | return 0; |
2104 | } | 2104 | } |
@@ -2124,7 +2124,7 @@ static int radeon_cp_clear(DRM_IOCTL_ARGS) | |||
2124 | 2124 | ||
2125 | if (DRM_COPY_FROM_USER(&depth_boxes, clear.depth_boxes, | 2125 | if (DRM_COPY_FROM_USER(&depth_boxes, clear.depth_boxes, |
2126 | sarea_priv->nbox * sizeof(depth_boxes[0]))) | 2126 | sarea_priv->nbox * sizeof(depth_boxes[0]))) |
2127 | return DRM_ERR(EFAULT); | 2127 | return -EFAULT; |
2128 | 2128 | ||
2129 | radeon_cp_dispatch_clear(dev, &clear, depth_boxes); | 2129 | radeon_cp_dispatch_clear(dev, &clear, depth_boxes); |
2130 | 2130 | ||
@@ -2226,11 +2226,11 @@ static int radeon_cp_vertex(DRM_IOCTL_ARGS) | |||
2226 | if (vertex.idx < 0 || vertex.idx >= dma->buf_count) { | 2226 | if (vertex.idx < 0 || vertex.idx >= dma->buf_count) { |
2227 | DRM_ERROR("buffer index %d (of %d max)\n", | 2227 | DRM_ERROR("buffer index %d (of %d max)\n", |
2228 | vertex.idx, dma->buf_count - 1); | 2228 | vertex.idx, dma->buf_count - 1); |
2229 | return DRM_ERR(EINVAL); | 2229 | return -EINVAL; |
2230 | } | 2230 | } |
2231 | if (vertex.prim < 0 || vertex.prim > RADEON_PRIM_TYPE_3VRT_LINE_LIST) { | 2231 | if (vertex.prim < 0 || vertex.prim > RADEON_PRIM_TYPE_3VRT_LINE_LIST) { |
2232 | DRM_ERROR("buffer prim %d\n", vertex.prim); | 2232 | DRM_ERROR("buffer prim %d\n", vertex.prim); |
2233 | return DRM_ERR(EINVAL); | 2233 | return -EINVAL; |
2234 | } | 2234 | } |
2235 | 2235 | ||
2236 | RING_SPACE_TEST_WITH_RETURN(dev_priv); | 2236 | RING_SPACE_TEST_WITH_RETURN(dev_priv); |
@@ -2241,11 +2241,11 @@ static int radeon_cp_vertex(DRM_IOCTL_ARGS) | |||
2241 | if (buf->filp != filp) { | 2241 | if (buf->filp != filp) { |
2242 | DRM_ERROR("process %d using buffer owned by %p\n", | 2242 | DRM_ERROR("process %d using buffer owned by %p\n", |
2243 | DRM_CURRENTPID, buf->filp); | 2243 | DRM_CURRENTPID, buf->filp); |
2244 | return DRM_ERR(EINVAL); | 2244 | return -EINVAL; |
2245 | } | 2245 | } |
2246 | if (buf->pending) { | 2246 | if (buf->pending) { |
2247 | DRM_ERROR("sending pending buffer %d\n", vertex.idx); | 2247 | DRM_ERROR("sending pending buffer %d\n", vertex.idx); |
2248 | return DRM_ERR(EINVAL); | 2248 | return -EINVAL; |
2249 | } | 2249 | } |
2250 | 2250 | ||
2251 | /* Build up a prim_t record: | 2251 | /* Build up a prim_t record: |
@@ -2259,7 +2259,7 @@ static int radeon_cp_vertex(DRM_IOCTL_ARGS) | |||
2259 | sarea_priv->tex_state, | 2259 | sarea_priv->tex_state, |
2260 | sarea_priv->dirty)) { | 2260 | sarea_priv->dirty)) { |
2261 | DRM_ERROR("radeon_emit_state failed\n"); | 2261 | DRM_ERROR("radeon_emit_state failed\n"); |
2262 | return DRM_ERR(EINVAL); | 2262 | return -EINVAL; |
2263 | } | 2263 | } |
2264 | 2264 | ||
2265 | sarea_priv->dirty &= ~(RADEON_UPLOAD_TEX0IMAGES | | 2265 | sarea_priv->dirty &= ~(RADEON_UPLOAD_TEX0IMAGES | |
@@ -2310,11 +2310,11 @@ static int radeon_cp_indices(DRM_IOCTL_ARGS) | |||
2310 | if (elts.idx < 0 || elts.idx >= dma->buf_count) { | 2310 | if (elts.idx < 0 || elts.idx >= dma->buf_count) { |
2311 | DRM_ERROR("buffer index %d (of %d max)\n", | 2311 | DRM_ERROR("buffer index %d (of %d max)\n", |
2312 | elts.idx, dma->buf_count - 1); | 2312 | elts.idx, dma->buf_count - 1); |
2313 | return DRM_ERR(EINVAL); | 2313 | return -EINVAL; |
2314 | } | 2314 | } |
2315 | if (elts.prim < 0 || elts.prim > RADEON_PRIM_TYPE_3VRT_LINE_LIST) { | 2315 | if (elts.prim < 0 || elts.prim > RADEON_PRIM_TYPE_3VRT_LINE_LIST) { |
2316 | DRM_ERROR("buffer prim %d\n", elts.prim); | 2316 | DRM_ERROR("buffer prim %d\n", elts.prim); |
2317 | return DRM_ERR(EINVAL); | 2317 | return -EINVAL; |
2318 | } | 2318 | } |
2319 | 2319 | ||
2320 | RING_SPACE_TEST_WITH_RETURN(dev_priv); | 2320 | RING_SPACE_TEST_WITH_RETURN(dev_priv); |
@@ -2325,11 +2325,11 @@ static int radeon_cp_indices(DRM_IOCTL_ARGS) | |||
2325 | if (buf->filp != filp) { | 2325 | if (buf->filp != filp) { |
2326 | DRM_ERROR("process %d using buffer owned by %p\n", | 2326 | DRM_ERROR("process %d using buffer owned by %p\n", |
2327 | DRM_CURRENTPID, buf->filp); | 2327 | DRM_CURRENTPID, buf->filp); |
2328 | return DRM_ERR(EINVAL); | 2328 | return -EINVAL; |
2329 | } | 2329 | } |
2330 | if (buf->pending) { | 2330 | if (buf->pending) { |
2331 | DRM_ERROR("sending pending buffer %d\n", elts.idx); | 2331 | DRM_ERROR("sending pending buffer %d\n", elts.idx); |
2332 | return DRM_ERR(EINVAL); | 2332 | return -EINVAL; |
2333 | } | 2333 | } |
2334 | 2334 | ||
2335 | count = (elts.end - elts.start) / sizeof(u16); | 2335 | count = (elts.end - elts.start) / sizeof(u16); |
@@ -2337,11 +2337,11 @@ static int radeon_cp_indices(DRM_IOCTL_ARGS) | |||
2337 | 2337 | ||
2338 | if (elts.start & 0x7) { | 2338 | if (elts.start & 0x7) { |
2339 | DRM_ERROR("misaligned buffer 0x%x\n", elts.start); | 2339 | DRM_ERROR("misaligned buffer 0x%x\n", elts.start); |
2340 | return DRM_ERR(EINVAL); | 2340 | return -EINVAL; |
2341 | } | 2341 | } |
2342 | if (elts.start < buf->used) { | 2342 | if (elts.start < buf->used) { |
2343 | DRM_ERROR("no header 0x%x - 0x%x\n", elts.start, buf->used); | 2343 | DRM_ERROR("no header 0x%x - 0x%x\n", elts.start, buf->used); |
2344 | return DRM_ERR(EINVAL); | 2344 | return -EINVAL; |
2345 | } | 2345 | } |
2346 | 2346 | ||
2347 | buf->used = elts.end; | 2347 | buf->used = elts.end; |
@@ -2352,7 +2352,7 @@ static int radeon_cp_indices(DRM_IOCTL_ARGS) | |||
2352 | sarea_priv->tex_state, | 2352 | sarea_priv->tex_state, |
2353 | sarea_priv->dirty)) { | 2353 | sarea_priv->dirty)) { |
2354 | DRM_ERROR("radeon_emit_state failed\n"); | 2354 | DRM_ERROR("radeon_emit_state failed\n"); |
2355 | return DRM_ERR(EINVAL); | 2355 | return -EINVAL; |
2356 | } | 2356 | } |
2357 | 2357 | ||
2358 | sarea_priv->dirty &= ~(RADEON_UPLOAD_TEX0IMAGES | | 2358 | sarea_priv->dirty &= ~(RADEON_UPLOAD_TEX0IMAGES | |
@@ -2394,13 +2394,13 @@ static int radeon_cp_texture(DRM_IOCTL_ARGS) | |||
2394 | 2394 | ||
2395 | if (tex.image == NULL) { | 2395 | if (tex.image == NULL) { |
2396 | DRM_ERROR("null texture image!\n"); | 2396 | DRM_ERROR("null texture image!\n"); |
2397 | return DRM_ERR(EINVAL); | 2397 | return -EINVAL; |
2398 | } | 2398 | } |
2399 | 2399 | ||
2400 | if (DRM_COPY_FROM_USER(&image, | 2400 | if (DRM_COPY_FROM_USER(&image, |
2401 | (drm_radeon_tex_image_t __user *) tex.image, | 2401 | (drm_radeon_tex_image_t __user *) tex.image, |
2402 | sizeof(image))) | 2402 | sizeof(image))) |
2403 | return DRM_ERR(EFAULT); | 2403 | return -EFAULT; |
2404 | 2404 | ||
2405 | RING_SPACE_TEST_WITH_RETURN(dev_priv); | 2405 | RING_SPACE_TEST_WITH_RETURN(dev_priv); |
2406 | VB_AGE_TEST_WITH_RETURN(dev_priv); | 2406 | VB_AGE_TEST_WITH_RETURN(dev_priv); |
@@ -2424,7 +2424,7 @@ static int radeon_cp_stipple(DRM_IOCTL_ARGS) | |||
2424 | sizeof(stipple)); | 2424 | sizeof(stipple)); |
2425 | 2425 | ||
2426 | if (DRM_COPY_FROM_USER(&mask, stipple.mask, 32 * sizeof(u32))) | 2426 | if (DRM_COPY_FROM_USER(&mask, stipple.mask, 32 * sizeof(u32))) |
2427 | return DRM_ERR(EFAULT); | 2427 | return -EFAULT; |
2428 | 2428 | ||
2429 | RING_SPACE_TEST_WITH_RETURN(dev_priv); | 2429 | RING_SPACE_TEST_WITH_RETURN(dev_priv); |
2430 | 2430 | ||
@@ -2455,7 +2455,7 @@ static int radeon_cp_indirect(DRM_IOCTL_ARGS) | |||
2455 | if (indirect.idx < 0 || indirect.idx >= dma->buf_count) { | 2455 | if (indirect.idx < 0 || indirect.idx >= dma->buf_count) { |
2456 | DRM_ERROR("buffer index %d (of %d max)\n", | 2456 | DRM_ERROR("buffer index %d (of %d max)\n", |
2457 | indirect.idx, dma->buf_count - 1); | 2457 | indirect.idx, dma->buf_count - 1); |
2458 | return DRM_ERR(EINVAL); | 2458 | return -EINVAL; |
2459 | } | 2459 | } |
2460 | 2460 | ||
2461 | buf = dma->buflist[indirect.idx]; | 2461 | buf = dma->buflist[indirect.idx]; |
@@ -2463,17 +2463,17 @@ static int radeon_cp_indirect(DRM_IOCTL_ARGS) | |||
2463 | if (buf->filp != filp) { | 2463 | if (buf->filp != filp) { |
2464 | DRM_ERROR("process %d using buffer owned by %p\n", | 2464 | DRM_ERROR("process %d using buffer owned by %p\n", |
2465 | DRM_CURRENTPID, buf->filp); | 2465 | DRM_CURRENTPID, buf->filp); |
2466 | return DRM_ERR(EINVAL); | 2466 | return -EINVAL; |
2467 | } | 2467 | } |
2468 | if (buf->pending) { | 2468 | if (buf->pending) { |
2469 | DRM_ERROR("sending pending buffer %d\n", indirect.idx); | 2469 | DRM_ERROR("sending pending buffer %d\n", indirect.idx); |
2470 | return DRM_ERR(EINVAL); | 2470 | return -EINVAL; |
2471 | } | 2471 | } |
2472 | 2472 | ||
2473 | if (indirect.start < buf->used) { | 2473 | if (indirect.start < buf->used) { |
2474 | DRM_ERROR("reusing indirect: start=0x%x actual=0x%x\n", | 2474 | DRM_ERROR("reusing indirect: start=0x%x actual=0x%x\n", |
2475 | indirect.start, buf->used); | 2475 | indirect.start, buf->used); |
2476 | return DRM_ERR(EINVAL); | 2476 | return -EINVAL; |
2477 | } | 2477 | } |
2478 | 2478 | ||
2479 | RING_SPACE_TEST_WITH_RETURN(dev_priv); | 2479 | RING_SPACE_TEST_WITH_RETURN(dev_priv); |
@@ -2528,7 +2528,7 @@ static int radeon_cp_vertex2(DRM_IOCTL_ARGS) | |||
2528 | if (vertex.idx < 0 || vertex.idx >= dma->buf_count) { | 2528 | if (vertex.idx < 0 || vertex.idx >= dma->buf_count) { |
2529 | DRM_ERROR("buffer index %d (of %d max)\n", | 2529 | DRM_ERROR("buffer index %d (of %d max)\n", |
2530 | vertex.idx, dma->buf_count - 1); | 2530 | vertex.idx, dma->buf_count - 1); |
2531 | return DRM_ERR(EINVAL); | 2531 | return -EINVAL; |
2532 | } | 2532 | } |
2533 | 2533 | ||
2534 | RING_SPACE_TEST_WITH_RETURN(dev_priv); | 2534 | RING_SPACE_TEST_WITH_RETURN(dev_priv); |
@@ -2539,23 +2539,23 @@ static int radeon_cp_vertex2(DRM_IOCTL_ARGS) | |||
2539 | if (buf->filp != filp) { | 2539 | if (buf->filp != filp) { |
2540 | DRM_ERROR("process %d using buffer owned by %p\n", | 2540 | DRM_ERROR("process %d using buffer owned by %p\n", |
2541 | DRM_CURRENTPID, buf->filp); | 2541 | DRM_CURRENTPID, buf->filp); |
2542 | return DRM_ERR(EINVAL); | 2542 | return -EINVAL; |
2543 | } | 2543 | } |
2544 | 2544 | ||
2545 | if (buf->pending) { | 2545 | if (buf->pending) { |
2546 | DRM_ERROR("sending pending buffer %d\n", vertex.idx); | 2546 | DRM_ERROR("sending pending buffer %d\n", vertex.idx); |
2547 | return DRM_ERR(EINVAL); | 2547 | return -EINVAL; |
2548 | } | 2548 | } |
2549 | 2549 | ||
2550 | if (sarea_priv->nbox > RADEON_NR_SAREA_CLIPRECTS) | 2550 | if (sarea_priv->nbox > RADEON_NR_SAREA_CLIPRECTS) |
2551 | return DRM_ERR(EINVAL); | 2551 | return -EINVAL; |
2552 | 2552 | ||
2553 | for (laststate = 0xff, i = 0; i < vertex.nr_prims; i++) { | 2553 | for (laststate = 0xff, i = 0; i < vertex.nr_prims; i++) { |
2554 | drm_radeon_prim_t prim; | 2554 | drm_radeon_prim_t prim; |
2555 | drm_radeon_tcl_prim_t tclprim; | 2555 | drm_radeon_tcl_prim_t tclprim; |
2556 | 2556 | ||
2557 | if (DRM_COPY_FROM_USER(&prim, &vertex.prim[i], sizeof(prim))) | 2557 | if (DRM_COPY_FROM_USER(&prim, &vertex.prim[i], sizeof(prim))) |
2558 | return DRM_ERR(EFAULT); | 2558 | return -EFAULT; |
2559 | 2559 | ||
2560 | if (prim.stateidx != laststate) { | 2560 | if (prim.stateidx != laststate) { |
2561 | drm_radeon_state_t state; | 2561 | drm_radeon_state_t state; |
@@ -2563,11 +2563,11 @@ static int radeon_cp_vertex2(DRM_IOCTL_ARGS) | |||
2563 | if (DRM_COPY_FROM_USER(&state, | 2563 | if (DRM_COPY_FROM_USER(&state, |
2564 | &vertex.state[prim.stateidx], | 2564 | &vertex.state[prim.stateidx], |
2565 | sizeof(state))) | 2565 | sizeof(state))) |
2566 | return DRM_ERR(EFAULT); | 2566 | return -EFAULT; |
2567 | 2567 | ||
2568 | if (radeon_emit_state2(dev_priv, filp_priv, &state)) { | 2568 | if (radeon_emit_state2(dev_priv, filp_priv, &state)) { |
2569 | DRM_ERROR("radeon_emit_state2 failed\n"); | 2569 | DRM_ERROR("radeon_emit_state2 failed\n"); |
2570 | return DRM_ERR(EINVAL); | 2570 | return -EINVAL; |
2571 | } | 2571 | } |
2572 | 2572 | ||
2573 | laststate = prim.stateidx; | 2573 | laststate = prim.stateidx; |
@@ -2613,19 +2613,19 @@ static int radeon_emit_packets(drm_radeon_private_t * dev_priv, | |||
2613 | RING_LOCALS; | 2613 | RING_LOCALS; |
2614 | 2614 | ||
2615 | if (id >= RADEON_MAX_STATE_PACKETS) | 2615 | if (id >= RADEON_MAX_STATE_PACKETS) |
2616 | return DRM_ERR(EINVAL); | 2616 | return -EINVAL; |
2617 | 2617 | ||
2618 | sz = packet[id].len; | 2618 | sz = packet[id].len; |
2619 | reg = packet[id].start; | 2619 | reg = packet[id].start; |
2620 | 2620 | ||
2621 | if (sz * sizeof(int) > cmdbuf->bufsz) { | 2621 | if (sz * sizeof(int) > cmdbuf->bufsz) { |
2622 | DRM_ERROR("Packet size provided larger than data provided\n"); | 2622 | DRM_ERROR("Packet size provided larger than data provided\n"); |
2623 | return DRM_ERR(EINVAL); | 2623 | return -EINVAL; |
2624 | } | 2624 | } |
2625 | 2625 | ||
2626 | if (radeon_check_and_fixup_packets(dev_priv, filp_priv, id, data)) { | 2626 | if (radeon_check_and_fixup_packets(dev_priv, filp_priv, id, data)) { |
2627 | DRM_ERROR("Packet verification failed\n"); | 2627 | DRM_ERROR("Packet verification failed\n"); |
2628 | return DRM_ERR(EINVAL); | 2628 | return -EINVAL; |
2629 | } | 2629 | } |
2630 | 2630 | ||
2631 | BEGIN_RING(sz + 1); | 2631 | BEGIN_RING(sz + 1); |
@@ -2713,7 +2713,7 @@ static __inline__ int radeon_emit_veclinear(drm_radeon_private_t *dev_priv, | |||
2713 | if (!sz) | 2713 | if (!sz) |
2714 | return 0; | 2714 | return 0; |
2715 | if (sz * 4 > cmdbuf->bufsz) | 2715 | if (sz * 4 > cmdbuf->bufsz) |
2716 | return DRM_ERR(EINVAL); | 2716 | return -EINVAL; |
2717 | 2717 | ||
2718 | BEGIN_RING(5 + sz); | 2718 | BEGIN_RING(5 + sz); |
2719 | OUT_RING_REG(RADEON_SE_TCL_STATE_FLUSH, 0); | 2719 | OUT_RING_REG(RADEON_SE_TCL_STATE_FLUSH, 0); |
@@ -2781,7 +2781,7 @@ static int radeon_emit_packet3_cliprect(struct drm_device *dev, | |||
2781 | do { | 2781 | do { |
2782 | if (i < cmdbuf->nbox) { | 2782 | if (i < cmdbuf->nbox) { |
2783 | if (DRM_COPY_FROM_USER(&box, &boxes[i], sizeof(box))) | 2783 | if (DRM_COPY_FROM_USER(&box, &boxes[i], sizeof(box))) |
2784 | return DRM_ERR(EFAULT); | 2784 | return -EFAULT; |
2785 | /* FIXME The second and subsequent times round | 2785 | /* FIXME The second and subsequent times round |
2786 | * this loop, send a WAIT_UNTIL_3D_IDLE before | 2786 | * this loop, send a WAIT_UNTIL_3D_IDLE before |
2787 | * calling emit_clip_rect(). This fixes a | 2787 | * calling emit_clip_rect(). This fixes a |
@@ -2839,7 +2839,7 @@ static int radeon_emit_wait(struct drm_device * dev, int flags) | |||
2839 | ADVANCE_RING(); | 2839 | ADVANCE_RING(); |
2840 | break; | 2840 | break; |
2841 | default: | 2841 | default: |
2842 | return DRM_ERR(EINVAL); | 2842 | return -EINVAL; |
2843 | } | 2843 | } |
2844 | 2844 | ||
2845 | return 0; | 2845 | return 0; |
@@ -2870,7 +2870,7 @@ static int radeon_cp_cmdbuf(DRM_IOCTL_ARGS) | |||
2870 | VB_AGE_TEST_WITH_RETURN(dev_priv); | 2870 | VB_AGE_TEST_WITH_RETURN(dev_priv); |
2871 | 2871 | ||
2872 | if (cmdbuf.bufsz > 64 * 1024 || cmdbuf.bufsz < 0) { | 2872 | if (cmdbuf.bufsz > 64 * 1024 || cmdbuf.bufsz < 0) { |
2873 | return DRM_ERR(EINVAL); | 2873 | return -EINVAL; |
2874 | } | 2874 | } |
2875 | 2875 | ||
2876 | /* Allocate an in-kernel area and copy in the cmdbuf. Do this to avoid | 2876 | /* Allocate an in-kernel area and copy in the cmdbuf. Do this to avoid |
@@ -2881,11 +2881,11 @@ static int radeon_cp_cmdbuf(DRM_IOCTL_ARGS) | |||
2881 | if (orig_bufsz != 0) { | 2881 | if (orig_bufsz != 0) { |
2882 | kbuf = drm_alloc(cmdbuf.bufsz, DRM_MEM_DRIVER); | 2882 | kbuf = drm_alloc(cmdbuf.bufsz, DRM_MEM_DRIVER); |
2883 | if (kbuf == NULL) | 2883 | if (kbuf == NULL) |
2884 | return DRM_ERR(ENOMEM); | 2884 | return -ENOMEM; |
2885 | if (DRM_COPY_FROM_USER(kbuf, (void __user *)cmdbuf.buf, | 2885 | if (DRM_COPY_FROM_USER(kbuf, (void __user *)cmdbuf.buf, |
2886 | cmdbuf.bufsz)) { | 2886 | cmdbuf.bufsz)) { |
2887 | drm_free(kbuf, orig_bufsz, DRM_MEM_DRIVER); | 2887 | drm_free(kbuf, orig_bufsz, DRM_MEM_DRIVER); |
2888 | return DRM_ERR(EFAULT); | 2888 | return -EFAULT; |
2889 | } | 2889 | } |
2890 | cmdbuf.buf = kbuf; | 2890 | cmdbuf.buf = kbuf; |
2891 | } | 2891 | } |
@@ -3012,7 +3012,7 @@ static int radeon_cp_cmdbuf(DRM_IOCTL_ARGS) | |||
3012 | err: | 3012 | err: |
3013 | if (orig_bufsz != 0) | 3013 | if (orig_bufsz != 0) |
3014 | drm_free(kbuf, orig_bufsz, DRM_MEM_DRIVER); | 3014 | drm_free(kbuf, orig_bufsz, DRM_MEM_DRIVER); |
3015 | return DRM_ERR(EINVAL); | 3015 | return -EINVAL; |
3016 | } | 3016 | } |
3017 | 3017 | ||
3018 | static int radeon_cp_getparam(DRM_IOCTL_ARGS) | 3018 | static int radeon_cp_getparam(DRM_IOCTL_ARGS) |
@@ -3074,7 +3074,7 @@ static int radeon_cp_getparam(DRM_IOCTL_ARGS) | |||
3074 | break; | 3074 | break; |
3075 | case RADEON_PARAM_SCRATCH_OFFSET: | 3075 | case RADEON_PARAM_SCRATCH_OFFSET: |
3076 | if (!dev_priv->writeback_works) | 3076 | if (!dev_priv->writeback_works) |
3077 | return DRM_ERR(EINVAL); | 3077 | return -EINVAL; |
3078 | value = RADEON_SCRATCH_REG_OFFSET; | 3078 | value = RADEON_SCRATCH_REG_OFFSET; |
3079 | break; | 3079 | break; |
3080 | case RADEON_PARAM_CARD_TYPE: | 3080 | case RADEON_PARAM_CARD_TYPE: |
@@ -3090,12 +3090,12 @@ static int radeon_cp_getparam(DRM_IOCTL_ARGS) | |||
3090 | break; | 3090 | break; |
3091 | default: | 3091 | default: |
3092 | DRM_DEBUG("Invalid parameter %d\n", param.param); | 3092 | DRM_DEBUG("Invalid parameter %d\n", param.param); |
3093 | return DRM_ERR(EINVAL); | 3093 | return -EINVAL; |
3094 | } | 3094 | } |
3095 | 3095 | ||
3096 | if (DRM_COPY_TO_USER(param.value, &value, sizeof(int))) { | 3096 | if (DRM_COPY_TO_USER(param.value, &value, sizeof(int))) { |
3097 | DRM_ERROR("copy_to_user\n"); | 3097 | DRM_ERROR("copy_to_user\n"); |
3098 | return DRM_ERR(EFAULT); | 3098 | return -EFAULT; |
3099 | } | 3099 | } |
3100 | 3100 | ||
3101 | return 0; | 3101 | return 0; |
@@ -3149,7 +3149,7 @@ static int radeon_cp_setparam(DRM_IOCTL_ARGS) | |||
3149 | break; | 3149 | break; |
3150 | default: | 3150 | default: |
3151 | DRM_DEBUG("Invalid parameter %d\n", sp.param); | 3151 | DRM_DEBUG("Invalid parameter %d\n", sp.param); |
3152 | return DRM_ERR(EINVAL); | 3152 | return -EINVAL; |
3153 | } | 3153 | } |
3154 | 3154 | ||
3155 | return 0; | 3155 | return 0; |