diff options
author | Eric Anholt <eric@anholt.net> | 2007-09-02 22:06:45 -0400 |
---|---|---|
committer | Dave Airlie <airlied@optimus.(none)> | 2007-10-14 20:38:20 -0400 |
commit | c153f45f9b7e30289157bba3ff5682291df16caa (patch) | |
tree | 33f21e1ebd83ec548751f3d490afe6230ab99972 /drivers/char/drm/radeon_state.c | |
parent | b589ee5943a9610ebaea6e4e3433f2ae4d812b0b (diff) |
drm: Replace DRM_IOCTL_ARGS with (dev, data, file_priv) and remove DRM_DEVICE.
The data is now in kernel space, copied in/out as appropriate according to t
This results in DRM_COPY_{TO,FROM}_USER going away, and error paths to deal
with those failures. This also means that XFree86 4.2.0 support for i810 DR
is lost.
Signed-off-by: Dave Airlie <airlied@linux.ie>
Diffstat (limited to 'drivers/char/drm/radeon_state.c')
-rw-r--r-- | drivers/char/drm/radeon_state.c | 344 |
1 files changed, 147 insertions, 197 deletions
diff --git a/drivers/char/drm/radeon_state.c b/drivers/char/drm/radeon_state.c index bd1aafdc3c29..ada820717ade 100644 --- a/drivers/char/drm/radeon_state.c +++ b/drivers/char/drm/radeon_state.c | |||
@@ -2075,61 +2075,48 @@ static void radeon_surfaces_release(struct drm_file *file_priv, | |||
2075 | /* ================================================================ | 2075 | /* ================================================================ |
2076 | * IOCTL functions | 2076 | * IOCTL functions |
2077 | */ | 2077 | */ |
2078 | static int radeon_surface_alloc(DRM_IOCTL_ARGS) | 2078 | static int radeon_surface_alloc(struct drm_device *dev, void *data, struct drm_file *file_priv) |
2079 | { | 2079 | { |
2080 | DRM_DEVICE; | ||
2081 | drm_radeon_private_t *dev_priv = dev->dev_private; | 2080 | drm_radeon_private_t *dev_priv = dev->dev_private; |
2082 | drm_radeon_surface_alloc_t alloc; | 2081 | drm_radeon_surface_alloc_t *alloc = data; |
2083 | 2082 | ||
2084 | DRM_COPY_FROM_USER_IOCTL(alloc, | 2083 | if (alloc_surface(alloc, dev_priv, file_priv) == -1) |
2085 | (drm_radeon_surface_alloc_t __user *) data, | ||
2086 | sizeof(alloc)); | ||
2087 | |||
2088 | if (alloc_surface(&alloc, dev_priv, file_priv) == -1) | ||
2089 | return -EINVAL; | 2084 | return -EINVAL; |
2090 | else | 2085 | else |
2091 | return 0; | 2086 | return 0; |
2092 | } | 2087 | } |
2093 | 2088 | ||
2094 | static int radeon_surface_free(DRM_IOCTL_ARGS) | 2089 | static int radeon_surface_free(struct drm_device *dev, void *data, struct drm_file *file_priv) |
2095 | { | 2090 | { |
2096 | DRM_DEVICE; | ||
2097 | drm_radeon_private_t *dev_priv = dev->dev_private; | 2091 | drm_radeon_private_t *dev_priv = dev->dev_private; |
2098 | drm_radeon_surface_free_t memfree; | 2092 | drm_radeon_surface_free_t *memfree = data; |
2099 | |||
2100 | DRM_COPY_FROM_USER_IOCTL(memfree, (drm_radeon_surface_free_t __user *) data, | ||
2101 | sizeof(memfree)); | ||
2102 | 2093 | ||
2103 | if (free_surface(file_priv, dev_priv, memfree.address)) | 2094 | if (free_surface(file_priv, dev_priv, memfree->address)) |
2104 | return -EINVAL; | 2095 | return -EINVAL; |
2105 | else | 2096 | else |
2106 | return 0; | 2097 | return 0; |
2107 | } | 2098 | } |
2108 | 2099 | ||
2109 | static int radeon_cp_clear(DRM_IOCTL_ARGS) | 2100 | static int radeon_cp_clear(struct drm_device *dev, void *data, struct drm_file *file_priv) |
2110 | { | 2101 | { |
2111 | DRM_DEVICE; | ||
2112 | drm_radeon_private_t *dev_priv = dev->dev_private; | 2102 | drm_radeon_private_t *dev_priv = dev->dev_private; |
2113 | drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; | 2103 | drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; |
2114 | drm_radeon_clear_t clear; | 2104 | drm_radeon_clear_t *clear = data; |
2115 | drm_radeon_clear_rect_t depth_boxes[RADEON_NR_SAREA_CLIPRECTS]; | 2105 | drm_radeon_clear_rect_t depth_boxes[RADEON_NR_SAREA_CLIPRECTS]; |
2116 | DRM_DEBUG("\n"); | 2106 | DRM_DEBUG("\n"); |
2117 | 2107 | ||
2118 | LOCK_TEST_WITH_RETURN(dev, file_priv); | 2108 | LOCK_TEST_WITH_RETURN(dev, file_priv); |
2119 | 2109 | ||
2120 | DRM_COPY_FROM_USER_IOCTL(clear, (drm_radeon_clear_t __user *) data, | ||
2121 | sizeof(clear)); | ||
2122 | |||
2123 | RING_SPACE_TEST_WITH_RETURN(dev_priv); | 2110 | RING_SPACE_TEST_WITH_RETURN(dev_priv); |
2124 | 2111 | ||
2125 | if (sarea_priv->nbox > RADEON_NR_SAREA_CLIPRECTS) | 2112 | if (sarea_priv->nbox > RADEON_NR_SAREA_CLIPRECTS) |
2126 | sarea_priv->nbox = RADEON_NR_SAREA_CLIPRECTS; | 2113 | sarea_priv->nbox = RADEON_NR_SAREA_CLIPRECTS; |
2127 | 2114 | ||
2128 | if (DRM_COPY_FROM_USER(&depth_boxes, clear.depth_boxes, | 2115 | if (DRM_COPY_FROM_USER(&depth_boxes, clear->depth_boxes, |
2129 | sarea_priv->nbox * sizeof(depth_boxes[0]))) | 2116 | sarea_priv->nbox * sizeof(depth_boxes[0]))) |
2130 | return -EFAULT; | 2117 | return -EFAULT; |
2131 | 2118 | ||
2132 | radeon_cp_dispatch_clear(dev, &clear, depth_boxes); | 2119 | radeon_cp_dispatch_clear(dev, clear, depth_boxes); |
2133 | 2120 | ||
2134 | COMMIT_RING(); | 2121 | COMMIT_RING(); |
2135 | return 0; | 2122 | return 0; |
@@ -2165,9 +2152,8 @@ static int radeon_do_init_pageflip(struct drm_device * dev) | |||
2165 | /* Swapping and flipping are different operations, need different ioctls. | 2152 | /* Swapping and flipping are different operations, need different ioctls. |
2166 | * They can & should be intermixed to support multiple 3d windows. | 2153 | * They can & should be intermixed to support multiple 3d windows. |
2167 | */ | 2154 | */ |
2168 | static int radeon_cp_flip(DRM_IOCTL_ARGS) | 2155 | static int radeon_cp_flip(struct drm_device *dev, void *data, struct drm_file *file_priv) |
2169 | { | 2156 | { |
2170 | DRM_DEVICE; | ||
2171 | drm_radeon_private_t *dev_priv = dev->dev_private; | 2157 | drm_radeon_private_t *dev_priv = dev->dev_private; |
2172 | DRM_DEBUG("\n"); | 2158 | DRM_DEBUG("\n"); |
2173 | 2159 | ||
@@ -2184,9 +2170,8 @@ static int radeon_cp_flip(DRM_IOCTL_ARGS) | |||
2184 | return 0; | 2170 | return 0; |
2185 | } | 2171 | } |
2186 | 2172 | ||
2187 | static int radeon_cp_swap(DRM_IOCTL_ARGS) | 2173 | static int radeon_cp_swap(struct drm_device *dev, void *data, struct drm_file *file_priv) |
2188 | { | 2174 | { |
2189 | DRM_DEVICE; | ||
2190 | drm_radeon_private_t *dev_priv = dev->dev_private; | 2175 | drm_radeon_private_t *dev_priv = dev->dev_private; |
2191 | drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; | 2176 | drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; |
2192 | DRM_DEBUG("\n"); | 2177 | DRM_DEBUG("\n"); |
@@ -2205,38 +2190,34 @@ static int radeon_cp_swap(DRM_IOCTL_ARGS) | |||
2205 | return 0; | 2190 | return 0; |
2206 | } | 2191 | } |
2207 | 2192 | ||
2208 | static int radeon_cp_vertex(DRM_IOCTL_ARGS) | 2193 | static int radeon_cp_vertex(struct drm_device *dev, void *data, struct drm_file *file_priv) |
2209 | { | 2194 | { |
2210 | DRM_DEVICE; | ||
2211 | drm_radeon_private_t *dev_priv = dev->dev_private; | 2195 | drm_radeon_private_t *dev_priv = dev->dev_private; |
2212 | drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; | 2196 | drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; |
2213 | struct drm_device_dma *dma = dev->dma; | 2197 | struct drm_device_dma *dma = dev->dma; |
2214 | struct drm_buf *buf; | 2198 | struct drm_buf *buf; |
2215 | drm_radeon_vertex_t vertex; | 2199 | drm_radeon_vertex_t *vertex = data; |
2216 | drm_radeon_tcl_prim_t prim; | 2200 | drm_radeon_tcl_prim_t prim; |
2217 | 2201 | ||
2218 | LOCK_TEST_WITH_RETURN(dev, file_priv); | 2202 | LOCK_TEST_WITH_RETURN(dev, file_priv); |
2219 | 2203 | ||
2220 | DRM_COPY_FROM_USER_IOCTL(vertex, (drm_radeon_vertex_t __user *) data, | ||
2221 | sizeof(vertex)); | ||
2222 | |||
2223 | DRM_DEBUG("pid=%d index=%d count=%d discard=%d\n", | 2204 | DRM_DEBUG("pid=%d index=%d count=%d discard=%d\n", |
2224 | DRM_CURRENTPID, vertex.idx, vertex.count, vertex.discard); | 2205 | DRM_CURRENTPID, vertex->idx, vertex->count, vertex->discard); |
2225 | 2206 | ||
2226 | if (vertex.idx < 0 || vertex.idx >= dma->buf_count) { | 2207 | if (vertex->idx < 0 || vertex->idx >= dma->buf_count) { |
2227 | DRM_ERROR("buffer index %d (of %d max)\n", | 2208 | DRM_ERROR("buffer index %d (of %d max)\n", |
2228 | vertex.idx, dma->buf_count - 1); | 2209 | vertex->idx, dma->buf_count - 1); |
2229 | return -EINVAL; | 2210 | return -EINVAL; |
2230 | } | 2211 | } |
2231 | if (vertex.prim < 0 || vertex.prim > RADEON_PRIM_TYPE_3VRT_LINE_LIST) { | 2212 | if (vertex->prim < 0 || vertex->prim > RADEON_PRIM_TYPE_3VRT_LINE_LIST) { |
2232 | DRM_ERROR("buffer prim %d\n", vertex.prim); | 2213 | DRM_ERROR("buffer prim %d\n", vertex->prim); |
2233 | return -EINVAL; | 2214 | return -EINVAL; |
2234 | } | 2215 | } |
2235 | 2216 | ||
2236 | RING_SPACE_TEST_WITH_RETURN(dev_priv); | 2217 | RING_SPACE_TEST_WITH_RETURN(dev_priv); |
2237 | VB_AGE_TEST_WITH_RETURN(dev_priv); | 2218 | VB_AGE_TEST_WITH_RETURN(dev_priv); |
2238 | 2219 | ||
2239 | buf = dma->buflist[vertex.idx]; | 2220 | buf = dma->buflist[vertex->idx]; |
2240 | 2221 | ||
2241 | if (buf->file_priv != file_priv) { | 2222 | if (buf->file_priv != file_priv) { |
2242 | DRM_ERROR("process %d using buffer owned by %p\n", | 2223 | DRM_ERROR("process %d using buffer owned by %p\n", |
@@ -2244,14 +2225,14 @@ static int radeon_cp_vertex(DRM_IOCTL_ARGS) | |||
2244 | return -EINVAL; | 2225 | return -EINVAL; |
2245 | } | 2226 | } |
2246 | if (buf->pending) { | 2227 | if (buf->pending) { |
2247 | DRM_ERROR("sending pending buffer %d\n", vertex.idx); | 2228 | DRM_ERROR("sending pending buffer %d\n", vertex->idx); |
2248 | return -EINVAL; | 2229 | return -EINVAL; |
2249 | } | 2230 | } |
2250 | 2231 | ||
2251 | /* Build up a prim_t record: | 2232 | /* Build up a prim_t record: |
2252 | */ | 2233 | */ |
2253 | if (vertex.count) { | 2234 | if (vertex->count) { |
2254 | buf->used = vertex.count; /* not used? */ | 2235 | buf->used = vertex->count; /* not used? */ |
2255 | 2236 | ||
2256 | if (sarea_priv->dirty & ~RADEON_UPLOAD_CLIPRECTS) { | 2237 | if (sarea_priv->dirty & ~RADEON_UPLOAD_CLIPRECTS) { |
2257 | if (radeon_emit_state(dev_priv, file_priv, | 2238 | if (radeon_emit_state(dev_priv, file_priv, |
@@ -2269,15 +2250,15 @@ static int radeon_cp_vertex(DRM_IOCTL_ARGS) | |||
2269 | } | 2250 | } |
2270 | 2251 | ||
2271 | prim.start = 0; | 2252 | prim.start = 0; |
2272 | prim.finish = vertex.count; /* unused */ | 2253 | prim.finish = vertex->count; /* unused */ |
2273 | prim.prim = vertex.prim; | 2254 | prim.prim = vertex->prim; |
2274 | prim.numverts = vertex.count; | 2255 | prim.numverts = vertex->count; |
2275 | prim.vc_format = dev_priv->sarea_priv->vc_format; | 2256 | prim.vc_format = dev_priv->sarea_priv->vc_format; |
2276 | 2257 | ||
2277 | radeon_cp_dispatch_vertex(dev, buf, &prim); | 2258 | radeon_cp_dispatch_vertex(dev, buf, &prim); |
2278 | } | 2259 | } |
2279 | 2260 | ||
2280 | if (vertex.discard) { | 2261 | if (vertex->discard) { |
2281 | radeon_cp_discard_buffer(dev, buf); | 2262 | radeon_cp_discard_buffer(dev, buf); |
2282 | } | 2263 | } |
2283 | 2264 | ||
@@ -2285,39 +2266,36 @@ static int radeon_cp_vertex(DRM_IOCTL_ARGS) | |||
2285 | return 0; | 2266 | return 0; |
2286 | } | 2267 | } |
2287 | 2268 | ||
2288 | static int radeon_cp_indices(DRM_IOCTL_ARGS) | 2269 | static int radeon_cp_indices(struct drm_device *dev, void *data, struct drm_file *file_priv) |
2289 | { | 2270 | { |
2290 | DRM_DEVICE; | ||
2291 | drm_radeon_private_t *dev_priv = dev->dev_private; | 2271 | drm_radeon_private_t *dev_priv = dev->dev_private; |
2292 | drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; | 2272 | drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; |
2293 | struct drm_device_dma *dma = dev->dma; | 2273 | struct drm_device_dma *dma = dev->dma; |
2294 | struct drm_buf *buf; | 2274 | struct drm_buf *buf; |
2295 | drm_radeon_indices_t elts; | 2275 | drm_radeon_indices_t *elts = data; |
2296 | drm_radeon_tcl_prim_t prim; | 2276 | drm_radeon_tcl_prim_t prim; |
2297 | int count; | 2277 | int count; |
2298 | 2278 | ||
2299 | LOCK_TEST_WITH_RETURN(dev, file_priv); | 2279 | LOCK_TEST_WITH_RETURN(dev, file_priv); |
2300 | 2280 | ||
2301 | DRM_COPY_FROM_USER_IOCTL(elts, (drm_radeon_indices_t __user *) data, | ||
2302 | sizeof(elts)); | ||
2303 | |||
2304 | DRM_DEBUG("pid=%d index=%d start=%d end=%d discard=%d\n", | 2281 | DRM_DEBUG("pid=%d index=%d start=%d end=%d discard=%d\n", |
2305 | DRM_CURRENTPID, elts.idx, elts.start, elts.end, elts.discard); | 2282 | DRM_CURRENTPID, elts->idx, elts->start, elts->end, |
2283 | elts->discard); | ||
2306 | 2284 | ||
2307 | if (elts.idx < 0 || elts.idx >= dma->buf_count) { | 2285 | if (elts->idx < 0 || elts->idx >= dma->buf_count) { |
2308 | DRM_ERROR("buffer index %d (of %d max)\n", | 2286 | DRM_ERROR("buffer index %d (of %d max)\n", |
2309 | elts.idx, dma->buf_count - 1); | 2287 | elts->idx, dma->buf_count - 1); |
2310 | return -EINVAL; | 2288 | return -EINVAL; |
2311 | } | 2289 | } |
2312 | if (elts.prim < 0 || elts.prim > RADEON_PRIM_TYPE_3VRT_LINE_LIST) { | 2290 | if (elts->prim < 0 || elts->prim > RADEON_PRIM_TYPE_3VRT_LINE_LIST) { |
2313 | DRM_ERROR("buffer prim %d\n", elts.prim); | 2291 | DRM_ERROR("buffer prim %d\n", elts->prim); |
2314 | return -EINVAL; | 2292 | return -EINVAL; |
2315 | } | 2293 | } |
2316 | 2294 | ||
2317 | RING_SPACE_TEST_WITH_RETURN(dev_priv); | 2295 | RING_SPACE_TEST_WITH_RETURN(dev_priv); |
2318 | VB_AGE_TEST_WITH_RETURN(dev_priv); | 2296 | VB_AGE_TEST_WITH_RETURN(dev_priv); |
2319 | 2297 | ||
2320 | buf = dma->buflist[elts.idx]; | 2298 | buf = dma->buflist[elts->idx]; |
2321 | 2299 | ||
2322 | if (buf->file_priv != file_priv) { | 2300 | if (buf->file_priv != file_priv) { |
2323 | DRM_ERROR("process %d using buffer owned by %p\n", | 2301 | DRM_ERROR("process %d using buffer owned by %p\n", |
@@ -2325,23 +2303,23 @@ static int radeon_cp_indices(DRM_IOCTL_ARGS) | |||
2325 | return -EINVAL; | 2303 | return -EINVAL; |
2326 | } | 2304 | } |
2327 | if (buf->pending) { | 2305 | if (buf->pending) { |
2328 | DRM_ERROR("sending pending buffer %d\n", elts.idx); | 2306 | DRM_ERROR("sending pending buffer %d\n", elts->idx); |
2329 | return -EINVAL; | 2307 | return -EINVAL; |
2330 | } | 2308 | } |
2331 | 2309 | ||
2332 | count = (elts.end - elts.start) / sizeof(u16); | 2310 | count = (elts->end - elts->start) / sizeof(u16); |
2333 | elts.start -= RADEON_INDEX_PRIM_OFFSET; | 2311 | elts->start -= RADEON_INDEX_PRIM_OFFSET; |
2334 | 2312 | ||
2335 | if (elts.start & 0x7) { | 2313 | if (elts->start & 0x7) { |
2336 | DRM_ERROR("misaligned buffer 0x%x\n", elts.start); | 2314 | DRM_ERROR("misaligned buffer 0x%x\n", elts->start); |
2337 | return -EINVAL; | 2315 | return -EINVAL; |
2338 | } | 2316 | } |
2339 | if (elts.start < buf->used) { | 2317 | if (elts->start < buf->used) { |
2340 | DRM_ERROR("no header 0x%x - 0x%x\n", elts.start, buf->used); | 2318 | DRM_ERROR("no header 0x%x - 0x%x\n", elts->start, buf->used); |
2341 | return -EINVAL; | 2319 | return -EINVAL; |
2342 | } | 2320 | } |
2343 | 2321 | ||
2344 | buf->used = elts.end; | 2322 | buf->used = elts->end; |
2345 | 2323 | ||
2346 | if (sarea_priv->dirty & ~RADEON_UPLOAD_CLIPRECTS) { | 2324 | if (sarea_priv->dirty & ~RADEON_UPLOAD_CLIPRECTS) { |
2347 | if (radeon_emit_state(dev_priv, file_priv, | 2325 | if (radeon_emit_state(dev_priv, file_priv, |
@@ -2360,15 +2338,15 @@ static int radeon_cp_indices(DRM_IOCTL_ARGS) | |||
2360 | 2338 | ||
2361 | /* Build up a prim_t record: | 2339 | /* Build up a prim_t record: |
2362 | */ | 2340 | */ |
2363 | prim.start = elts.start; | 2341 | prim.start = elts->start; |
2364 | prim.finish = elts.end; | 2342 | prim.finish = elts->end; |
2365 | prim.prim = elts.prim; | 2343 | prim.prim = elts->prim; |
2366 | prim.offset = 0; /* offset from start of dma buffers */ | 2344 | prim.offset = 0; /* offset from start of dma buffers */ |
2367 | prim.numverts = RADEON_MAX_VB_VERTS; /* duh */ | 2345 | prim.numverts = RADEON_MAX_VB_VERTS; /* duh */ |
2368 | prim.vc_format = dev_priv->sarea_priv->vc_format; | 2346 | prim.vc_format = dev_priv->sarea_priv->vc_format; |
2369 | 2347 | ||
2370 | radeon_cp_dispatch_indices(dev, buf, &prim); | 2348 | radeon_cp_dispatch_indices(dev, buf, &prim); |
2371 | if (elts.discard) { | 2349 | if (elts->discard) { |
2372 | radeon_cp_discard_buffer(dev, buf); | 2350 | radeon_cp_discard_buffer(dev, buf); |
2373 | } | 2351 | } |
2374 | 2352 | ||
@@ -2376,51 +2354,43 @@ static int radeon_cp_indices(DRM_IOCTL_ARGS) | |||
2376 | return 0; | 2354 | return 0; |
2377 | } | 2355 | } |
2378 | 2356 | ||
2379 | static int radeon_cp_texture(DRM_IOCTL_ARGS) | 2357 | static int radeon_cp_texture(struct drm_device *dev, void *data, struct drm_file *file_priv) |
2380 | { | 2358 | { |
2381 | DRM_DEVICE; | ||
2382 | drm_radeon_private_t *dev_priv = dev->dev_private; | 2359 | drm_radeon_private_t *dev_priv = dev->dev_private; |
2383 | drm_radeon_texture_t tex; | 2360 | drm_radeon_texture_t *tex = data; |
2384 | drm_radeon_tex_image_t image; | 2361 | drm_radeon_tex_image_t image; |
2385 | int ret; | 2362 | int ret; |
2386 | 2363 | ||
2387 | LOCK_TEST_WITH_RETURN(dev, file_priv); | 2364 | LOCK_TEST_WITH_RETURN(dev, file_priv); |
2388 | 2365 | ||
2389 | DRM_COPY_FROM_USER_IOCTL(tex, (drm_radeon_texture_t __user *) data, | 2366 | if (tex->image == NULL) { |
2390 | sizeof(tex)); | ||
2391 | |||
2392 | if (tex.image == NULL) { | ||
2393 | DRM_ERROR("null texture image!\n"); | 2367 | DRM_ERROR("null texture image!\n"); |
2394 | return -EINVAL; | 2368 | return -EINVAL; |
2395 | } | 2369 | } |
2396 | 2370 | ||
2397 | if (DRM_COPY_FROM_USER(&image, | 2371 | if (DRM_COPY_FROM_USER(&image, |
2398 | (drm_radeon_tex_image_t __user *) tex.image, | 2372 | (drm_radeon_tex_image_t __user *) tex->image, |
2399 | sizeof(image))) | 2373 | sizeof(image))) |
2400 | return -EFAULT; | 2374 | return -EFAULT; |
2401 | 2375 | ||
2402 | RING_SPACE_TEST_WITH_RETURN(dev_priv); | 2376 | RING_SPACE_TEST_WITH_RETURN(dev_priv); |
2403 | VB_AGE_TEST_WITH_RETURN(dev_priv); | 2377 | VB_AGE_TEST_WITH_RETURN(dev_priv); |
2404 | 2378 | ||
2405 | ret = radeon_cp_dispatch_texture(dev, file_priv, &tex, &image); | 2379 | ret = radeon_cp_dispatch_texture(dev, file_priv, tex, &image); |
2406 | 2380 | ||
2407 | COMMIT_RING(); | 2381 | COMMIT_RING(); |
2408 | return ret; | 2382 | return ret; |
2409 | } | 2383 | } |
2410 | 2384 | ||
2411 | static int radeon_cp_stipple(DRM_IOCTL_ARGS) | 2385 | static int radeon_cp_stipple(struct drm_device *dev, void *data, struct drm_file *file_priv) |
2412 | { | 2386 | { |
2413 | DRM_DEVICE; | ||
2414 | drm_radeon_private_t *dev_priv = dev->dev_private; | 2387 | drm_radeon_private_t *dev_priv = dev->dev_private; |
2415 | drm_radeon_stipple_t stipple; | 2388 | drm_radeon_stipple_t *stipple = data; |
2416 | u32 mask[32]; | 2389 | u32 mask[32]; |
2417 | 2390 | ||
2418 | LOCK_TEST_WITH_RETURN(dev, file_priv); | 2391 | LOCK_TEST_WITH_RETURN(dev, file_priv); |
2419 | 2392 | ||
2420 | DRM_COPY_FROM_USER_IOCTL(stipple, (drm_radeon_stipple_t __user *) data, | 2393 | if (DRM_COPY_FROM_USER(&mask, stipple->mask, 32 * sizeof(u32))) |
2421 | sizeof(stipple)); | ||
2422 | |||
2423 | if (DRM_COPY_FROM_USER(&mask, stipple.mask, 32 * sizeof(u32))) | ||
2424 | return -EFAULT; | 2394 | return -EFAULT; |
2425 | 2395 | ||
2426 | RING_SPACE_TEST_WITH_RETURN(dev_priv); | 2396 | RING_SPACE_TEST_WITH_RETURN(dev_priv); |
@@ -2431,31 +2401,27 @@ static int radeon_cp_stipple(DRM_IOCTL_ARGS) | |||
2431 | return 0; | 2401 | return 0; |
2432 | } | 2402 | } |
2433 | 2403 | ||
2434 | static int radeon_cp_indirect(DRM_IOCTL_ARGS) | 2404 | static int radeon_cp_indirect(struct drm_device *dev, void *data, struct drm_file *file_priv) |
2435 | { | 2405 | { |
2436 | DRM_DEVICE; | ||
2437 | drm_radeon_private_t *dev_priv = dev->dev_private; | 2406 | drm_radeon_private_t *dev_priv = dev->dev_private; |
2438 | struct drm_device_dma *dma = dev->dma; | 2407 | struct drm_device_dma *dma = dev->dma; |
2439 | struct drm_buf *buf; | 2408 | struct drm_buf *buf; |
2440 | drm_radeon_indirect_t indirect; | 2409 | drm_radeon_indirect_t *indirect = data; |
2441 | RING_LOCALS; | 2410 | RING_LOCALS; |
2442 | 2411 | ||
2443 | LOCK_TEST_WITH_RETURN(dev, file_priv); | 2412 | LOCK_TEST_WITH_RETURN(dev, file_priv); |
2444 | 2413 | ||
2445 | DRM_COPY_FROM_USER_IOCTL(indirect, | ||
2446 | (drm_radeon_indirect_t __user *) data, | ||
2447 | sizeof(indirect)); | ||
2448 | |||
2449 | DRM_DEBUG("indirect: idx=%d s=%d e=%d d=%d\n", | 2414 | DRM_DEBUG("indirect: idx=%d s=%d e=%d d=%d\n", |
2450 | indirect.idx, indirect.start, indirect.end, indirect.discard); | 2415 | indirect->idx, indirect->start, indirect->end, |
2416 | indirect->discard); | ||
2451 | 2417 | ||
2452 | if (indirect.idx < 0 || indirect.idx >= dma->buf_count) { | 2418 | if (indirect->idx < 0 || indirect->idx >= dma->buf_count) { |
2453 | DRM_ERROR("buffer index %d (of %d max)\n", | 2419 | DRM_ERROR("buffer index %d (of %d max)\n", |
2454 | indirect.idx, dma->buf_count - 1); | 2420 | indirect->idx, dma->buf_count - 1); |
2455 | return -EINVAL; | 2421 | return -EINVAL; |
2456 | } | 2422 | } |
2457 | 2423 | ||
2458 | buf = dma->buflist[indirect.idx]; | 2424 | buf = dma->buflist[indirect->idx]; |
2459 | 2425 | ||
2460 | if (buf->file_priv != file_priv) { | 2426 | if (buf->file_priv != file_priv) { |
2461 | DRM_ERROR("process %d using buffer owned by %p\n", | 2427 | DRM_ERROR("process %d using buffer owned by %p\n", |
@@ -2463,20 +2429,20 @@ static int radeon_cp_indirect(DRM_IOCTL_ARGS) | |||
2463 | return -EINVAL; | 2429 | return -EINVAL; |
2464 | } | 2430 | } |
2465 | if (buf->pending) { | 2431 | if (buf->pending) { |
2466 | DRM_ERROR("sending pending buffer %d\n", indirect.idx); | 2432 | DRM_ERROR("sending pending buffer %d\n", indirect->idx); |
2467 | return -EINVAL; | 2433 | return -EINVAL; |
2468 | } | 2434 | } |
2469 | 2435 | ||
2470 | if (indirect.start < buf->used) { | 2436 | if (indirect->start < buf->used) { |
2471 | DRM_ERROR("reusing indirect: start=0x%x actual=0x%x\n", | 2437 | DRM_ERROR("reusing indirect: start=0x%x actual=0x%x\n", |
2472 | indirect.start, buf->used); | 2438 | indirect->start, buf->used); |
2473 | return -EINVAL; | 2439 | return -EINVAL; |
2474 | } | 2440 | } |
2475 | 2441 | ||
2476 | RING_SPACE_TEST_WITH_RETURN(dev_priv); | 2442 | RING_SPACE_TEST_WITH_RETURN(dev_priv); |
2477 | VB_AGE_TEST_WITH_RETURN(dev_priv); | 2443 | VB_AGE_TEST_WITH_RETURN(dev_priv); |
2478 | 2444 | ||
2479 | buf->used = indirect.end; | 2445 | buf->used = indirect->end; |
2480 | 2446 | ||
2481 | /* Wait for the 3D stream to idle before the indirect buffer | 2447 | /* Wait for the 3D stream to idle before the indirect buffer |
2482 | * containing 2D acceleration commands is processed. | 2448 | * containing 2D acceleration commands is processed. |
@@ -2491,8 +2457,8 @@ static int radeon_cp_indirect(DRM_IOCTL_ARGS) | |||
2491 | * X server. This is insecure and is thus only available to | 2457 | * X server. This is insecure and is thus only available to |
2492 | * privileged clients. | 2458 | * privileged clients. |
2493 | */ | 2459 | */ |
2494 | radeon_cp_dispatch_indirect(dev, buf, indirect.start, indirect.end); | 2460 | radeon_cp_dispatch_indirect(dev, buf, indirect->start, indirect->end); |
2495 | if (indirect.discard) { | 2461 | if (indirect->discard) { |
2496 | radeon_cp_discard_buffer(dev, buf); | 2462 | radeon_cp_discard_buffer(dev, buf); |
2497 | } | 2463 | } |
2498 | 2464 | ||
@@ -2500,35 +2466,31 @@ static int radeon_cp_indirect(DRM_IOCTL_ARGS) | |||
2500 | return 0; | 2466 | return 0; |
2501 | } | 2467 | } |
2502 | 2468 | ||
2503 | static int radeon_cp_vertex2(DRM_IOCTL_ARGS) | 2469 | static int radeon_cp_vertex2(struct drm_device *dev, void *data, struct drm_file *file_priv) |
2504 | { | 2470 | { |
2505 | DRM_DEVICE; | ||
2506 | drm_radeon_private_t *dev_priv = dev->dev_private; | 2471 | drm_radeon_private_t *dev_priv = dev->dev_private; |
2507 | drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; | 2472 | drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; |
2508 | struct drm_device_dma *dma = dev->dma; | 2473 | struct drm_device_dma *dma = dev->dma; |
2509 | struct drm_buf *buf; | 2474 | struct drm_buf *buf; |
2510 | drm_radeon_vertex2_t vertex; | 2475 | drm_radeon_vertex2_t *vertex = data; |
2511 | int i; | 2476 | int i; |
2512 | unsigned char laststate; | 2477 | unsigned char laststate; |
2513 | 2478 | ||
2514 | LOCK_TEST_WITH_RETURN(dev, file_priv); | 2479 | LOCK_TEST_WITH_RETURN(dev, file_priv); |
2515 | 2480 | ||
2516 | DRM_COPY_FROM_USER_IOCTL(vertex, (drm_radeon_vertex2_t __user *) data, | ||
2517 | sizeof(vertex)); | ||
2518 | |||
2519 | DRM_DEBUG("pid=%d index=%d discard=%d\n", | 2481 | DRM_DEBUG("pid=%d index=%d discard=%d\n", |
2520 | DRM_CURRENTPID, vertex.idx, vertex.discard); | 2482 | DRM_CURRENTPID, vertex->idx, vertex->discard); |
2521 | 2483 | ||
2522 | if (vertex.idx < 0 || vertex.idx >= dma->buf_count) { | 2484 | if (vertex->idx < 0 || vertex->idx >= dma->buf_count) { |
2523 | DRM_ERROR("buffer index %d (of %d max)\n", | 2485 | DRM_ERROR("buffer index %d (of %d max)\n", |
2524 | vertex.idx, dma->buf_count - 1); | 2486 | vertex->idx, dma->buf_count - 1); |
2525 | return -EINVAL; | 2487 | return -EINVAL; |
2526 | } | 2488 | } |
2527 | 2489 | ||
2528 | RING_SPACE_TEST_WITH_RETURN(dev_priv); | 2490 | RING_SPACE_TEST_WITH_RETURN(dev_priv); |
2529 | VB_AGE_TEST_WITH_RETURN(dev_priv); | 2491 | VB_AGE_TEST_WITH_RETURN(dev_priv); |
2530 | 2492 | ||
2531 | buf = dma->buflist[vertex.idx]; | 2493 | buf = dma->buflist[vertex->idx]; |
2532 | 2494 | ||
2533 | if (buf->file_priv != file_priv) { | 2495 | if (buf->file_priv != file_priv) { |
2534 | DRM_ERROR("process %d using buffer owned by %p\n", | 2496 | DRM_ERROR("process %d using buffer owned by %p\n", |
@@ -2537,25 +2499,25 @@ static int radeon_cp_vertex2(DRM_IOCTL_ARGS) | |||
2537 | } | 2499 | } |
2538 | 2500 | ||
2539 | if (buf->pending) { | 2501 | if (buf->pending) { |
2540 | DRM_ERROR("sending pending buffer %d\n", vertex.idx); | 2502 | DRM_ERROR("sending pending buffer %d\n", vertex->idx); |
2541 | return -EINVAL; | 2503 | return -EINVAL; |
2542 | } | 2504 | } |
2543 | 2505 | ||
2544 | if (sarea_priv->nbox > RADEON_NR_SAREA_CLIPRECTS) | 2506 | if (sarea_priv->nbox > RADEON_NR_SAREA_CLIPRECTS) |
2545 | return -EINVAL; | 2507 | return -EINVAL; |
2546 | 2508 | ||
2547 | for (laststate = 0xff, i = 0; i < vertex.nr_prims; i++) { | 2509 | for (laststate = 0xff, i = 0; i < vertex->nr_prims; i++) { |
2548 | drm_radeon_prim_t prim; | 2510 | drm_radeon_prim_t prim; |
2549 | drm_radeon_tcl_prim_t tclprim; | 2511 | drm_radeon_tcl_prim_t tclprim; |
2550 | 2512 | ||
2551 | if (DRM_COPY_FROM_USER(&prim, &vertex.prim[i], sizeof(prim))) | 2513 | if (DRM_COPY_FROM_USER(&prim, &vertex->prim[i], sizeof(prim))) |
2552 | return -EFAULT; | 2514 | return -EFAULT; |
2553 | 2515 | ||
2554 | if (prim.stateidx != laststate) { | 2516 | if (prim.stateidx != laststate) { |
2555 | drm_radeon_state_t state; | 2517 | drm_radeon_state_t state; |
2556 | 2518 | ||
2557 | if (DRM_COPY_FROM_USER(&state, | 2519 | if (DRM_COPY_FROM_USER(&state, |
2558 | &vertex.state[prim.stateidx], | 2520 | &vertex->state[prim.stateidx], |
2559 | sizeof(state))) | 2521 | sizeof(state))) |
2560 | return -EFAULT; | 2522 | return -EFAULT; |
2561 | 2523 | ||
@@ -2588,7 +2550,7 @@ static int radeon_cp_vertex2(DRM_IOCTL_ARGS) | |||
2588 | sarea_priv->nbox = 0; | 2550 | sarea_priv->nbox = 0; |
2589 | } | 2551 | } |
2590 | 2552 | ||
2591 | if (vertex.discard) { | 2553 | if (vertex->discard) { |
2592 | radeon_cp_discard_buffer(dev, buf); | 2554 | radeon_cp_discard_buffer(dev, buf); |
2593 | } | 2555 | } |
2594 | 2556 | ||
@@ -2839,28 +2801,23 @@ static int radeon_emit_wait(struct drm_device * dev, int flags) | |||
2839 | return 0; | 2801 | return 0; |
2840 | } | 2802 | } |
2841 | 2803 | ||
2842 | static int radeon_cp_cmdbuf(DRM_IOCTL_ARGS) | 2804 | static int radeon_cp_cmdbuf(struct drm_device *dev, void *data, struct drm_file *file_priv) |
2843 | { | 2805 | { |
2844 | DRM_DEVICE; | ||
2845 | drm_radeon_private_t *dev_priv = dev->dev_private; | 2806 | drm_radeon_private_t *dev_priv = dev->dev_private; |
2846 | struct drm_device_dma *dma = dev->dma; | 2807 | struct drm_device_dma *dma = dev->dma; |
2847 | struct drm_buf *buf = NULL; | 2808 | struct drm_buf *buf = NULL; |
2848 | int idx; | 2809 | int idx; |
2849 | drm_radeon_kcmd_buffer_t cmdbuf; | 2810 | drm_radeon_kcmd_buffer_t *cmdbuf = data; |
2850 | drm_radeon_cmd_header_t header; | 2811 | drm_radeon_cmd_header_t header; |
2851 | int orig_nbox, orig_bufsz; | 2812 | int orig_nbox, orig_bufsz; |
2852 | char *kbuf = NULL; | 2813 | char *kbuf = NULL; |
2853 | 2814 | ||
2854 | LOCK_TEST_WITH_RETURN(dev, file_priv); | 2815 | LOCK_TEST_WITH_RETURN(dev, file_priv); |
2855 | 2816 | ||
2856 | DRM_COPY_FROM_USER_IOCTL(cmdbuf, | ||
2857 | (drm_radeon_cmd_buffer_t __user *) data, | ||
2858 | sizeof(cmdbuf)); | ||
2859 | |||
2860 | RING_SPACE_TEST_WITH_RETURN(dev_priv); | 2817 | RING_SPACE_TEST_WITH_RETURN(dev_priv); |
2861 | VB_AGE_TEST_WITH_RETURN(dev_priv); | 2818 | VB_AGE_TEST_WITH_RETURN(dev_priv); |
2862 | 2819 | ||
2863 | if (cmdbuf.bufsz > 64 * 1024 || cmdbuf.bufsz < 0) { | 2820 | if (cmdbuf->bufsz > 64 * 1024 || cmdbuf->bufsz < 0) { |
2864 | return -EINVAL; | 2821 | return -EINVAL; |
2865 | } | 2822 | } |
2866 | 2823 | ||
@@ -2868,24 +2825,24 @@ static int radeon_cp_cmdbuf(DRM_IOCTL_ARGS) | |||
2868 | * races between checking values and using those values in other code, | 2825 | * races between checking values and using those values in other code, |
2869 | * and simply to avoid a lot of function calls to copy in data. | 2826 | * and simply to avoid a lot of function calls to copy in data. |
2870 | */ | 2827 | */ |
2871 | orig_bufsz = cmdbuf.bufsz; | 2828 | orig_bufsz = cmdbuf->bufsz; |
2872 | if (orig_bufsz != 0) { | 2829 | if (orig_bufsz != 0) { |
2873 | kbuf = drm_alloc(cmdbuf.bufsz, DRM_MEM_DRIVER); | 2830 | kbuf = drm_alloc(cmdbuf->bufsz, DRM_MEM_DRIVER); |
2874 | if (kbuf == NULL) | 2831 | if (kbuf == NULL) |
2875 | return -ENOMEM; | 2832 | return -ENOMEM; |
2876 | if (DRM_COPY_FROM_USER(kbuf, (void __user *)cmdbuf.buf, | 2833 | if (DRM_COPY_FROM_USER(kbuf, (void __user *)cmdbuf->buf, |
2877 | cmdbuf.bufsz)) { | 2834 | cmdbuf->bufsz)) { |
2878 | drm_free(kbuf, orig_bufsz, DRM_MEM_DRIVER); | 2835 | drm_free(kbuf, orig_bufsz, DRM_MEM_DRIVER); |
2879 | return -EFAULT; | 2836 | return -EFAULT; |
2880 | } | 2837 | } |
2881 | cmdbuf.buf = kbuf; | 2838 | cmdbuf->buf = kbuf; |
2882 | } | 2839 | } |
2883 | 2840 | ||
2884 | orig_nbox = cmdbuf.nbox; | 2841 | orig_nbox = cmdbuf->nbox; |
2885 | 2842 | ||
2886 | if (dev_priv->microcode_version == UCODE_R300) { | 2843 | if (dev_priv->microcode_version == UCODE_R300) { |
2887 | int temp; | 2844 | int temp; |
2888 | temp = r300_do_cp_cmdbuf(dev, file_priv, &cmdbuf); | 2845 | temp = r300_do_cp_cmdbuf(dev, file_priv, cmdbuf); |
2889 | 2846 | ||
2890 | if (orig_bufsz != 0) | 2847 | if (orig_bufsz != 0) |
2891 | drm_free(kbuf, orig_bufsz, DRM_MEM_DRIVER); | 2848 | drm_free(kbuf, orig_bufsz, DRM_MEM_DRIVER); |
@@ -2894,17 +2851,17 @@ static int radeon_cp_cmdbuf(DRM_IOCTL_ARGS) | |||
2894 | } | 2851 | } |
2895 | 2852 | ||
2896 | /* microcode_version != r300 */ | 2853 | /* microcode_version != r300 */ |
2897 | while (cmdbuf.bufsz >= sizeof(header)) { | 2854 | while (cmdbuf->bufsz >= sizeof(header)) { |
2898 | 2855 | ||
2899 | header.i = *(int *)cmdbuf.buf; | 2856 | header.i = *(int *)cmdbuf->buf; |
2900 | cmdbuf.buf += sizeof(header); | 2857 | cmdbuf->buf += sizeof(header); |
2901 | cmdbuf.bufsz -= sizeof(header); | 2858 | cmdbuf->bufsz -= sizeof(header); |
2902 | 2859 | ||
2903 | switch (header.header.cmd_type) { | 2860 | switch (header.header.cmd_type) { |
2904 | case RADEON_CMD_PACKET: | 2861 | case RADEON_CMD_PACKET: |
2905 | DRM_DEBUG("RADEON_CMD_PACKET\n"); | 2862 | DRM_DEBUG("RADEON_CMD_PACKET\n"); |
2906 | if (radeon_emit_packets | 2863 | if (radeon_emit_packets |
2907 | (dev_priv, file_priv, header, &cmdbuf)) { | 2864 | (dev_priv, file_priv, header, cmdbuf)) { |
2908 | DRM_ERROR("radeon_emit_packets failed\n"); | 2865 | DRM_ERROR("radeon_emit_packets failed\n"); |
2909 | goto err; | 2866 | goto err; |
2910 | } | 2867 | } |
@@ -2912,7 +2869,7 @@ static int radeon_cp_cmdbuf(DRM_IOCTL_ARGS) | |||
2912 | 2869 | ||
2913 | case RADEON_CMD_SCALARS: | 2870 | case RADEON_CMD_SCALARS: |
2914 | DRM_DEBUG("RADEON_CMD_SCALARS\n"); | 2871 | DRM_DEBUG("RADEON_CMD_SCALARS\n"); |
2915 | if (radeon_emit_scalars(dev_priv, header, &cmdbuf)) { | 2872 | if (radeon_emit_scalars(dev_priv, header, cmdbuf)) { |
2916 | DRM_ERROR("radeon_emit_scalars failed\n"); | 2873 | DRM_ERROR("radeon_emit_scalars failed\n"); |
2917 | goto err; | 2874 | goto err; |
2918 | } | 2875 | } |
@@ -2920,7 +2877,7 @@ static int radeon_cp_cmdbuf(DRM_IOCTL_ARGS) | |||
2920 | 2877 | ||
2921 | case RADEON_CMD_VECTORS: | 2878 | case RADEON_CMD_VECTORS: |
2922 | DRM_DEBUG("RADEON_CMD_VECTORS\n"); | 2879 | DRM_DEBUG("RADEON_CMD_VECTORS\n"); |
2923 | if (radeon_emit_vectors(dev_priv, header, &cmdbuf)) { | 2880 | if (radeon_emit_vectors(dev_priv, header, cmdbuf)) { |
2924 | DRM_ERROR("radeon_emit_vectors failed\n"); | 2881 | DRM_ERROR("radeon_emit_vectors failed\n"); |
2925 | goto err; | 2882 | goto err; |
2926 | } | 2883 | } |
@@ -2948,7 +2905,7 @@ static int radeon_cp_cmdbuf(DRM_IOCTL_ARGS) | |||
2948 | 2905 | ||
2949 | case RADEON_CMD_PACKET3: | 2906 | case RADEON_CMD_PACKET3: |
2950 | DRM_DEBUG("RADEON_CMD_PACKET3\n"); | 2907 | DRM_DEBUG("RADEON_CMD_PACKET3\n"); |
2951 | if (radeon_emit_packet3(dev, file_priv, &cmdbuf)) { | 2908 | if (radeon_emit_packet3(dev, file_priv, cmdbuf)) { |
2952 | DRM_ERROR("radeon_emit_packet3 failed\n"); | 2909 | DRM_ERROR("radeon_emit_packet3 failed\n"); |
2953 | goto err; | 2910 | goto err; |
2954 | } | 2911 | } |
@@ -2957,7 +2914,7 @@ static int radeon_cp_cmdbuf(DRM_IOCTL_ARGS) | |||
2957 | case RADEON_CMD_PACKET3_CLIP: | 2914 | case RADEON_CMD_PACKET3_CLIP: |
2958 | DRM_DEBUG("RADEON_CMD_PACKET3_CLIP\n"); | 2915 | DRM_DEBUG("RADEON_CMD_PACKET3_CLIP\n"); |
2959 | if (radeon_emit_packet3_cliprect | 2916 | if (radeon_emit_packet3_cliprect |
2960 | (dev, file_priv, &cmdbuf, orig_nbox)) { | 2917 | (dev, file_priv, cmdbuf, orig_nbox)) { |
2961 | DRM_ERROR("radeon_emit_packet3_clip failed\n"); | 2918 | DRM_ERROR("radeon_emit_packet3_clip failed\n"); |
2962 | goto err; | 2919 | goto err; |
2963 | } | 2920 | } |
@@ -2965,7 +2922,7 @@ static int radeon_cp_cmdbuf(DRM_IOCTL_ARGS) | |||
2965 | 2922 | ||
2966 | case RADEON_CMD_SCALARS2: | 2923 | case RADEON_CMD_SCALARS2: |
2967 | DRM_DEBUG("RADEON_CMD_SCALARS2\n"); | 2924 | DRM_DEBUG("RADEON_CMD_SCALARS2\n"); |
2968 | if (radeon_emit_scalars2(dev_priv, header, &cmdbuf)) { | 2925 | if (radeon_emit_scalars2(dev_priv, header, cmdbuf)) { |
2969 | DRM_ERROR("radeon_emit_scalars2 failed\n"); | 2926 | DRM_ERROR("radeon_emit_scalars2 failed\n"); |
2970 | goto err; | 2927 | goto err; |
2971 | } | 2928 | } |
@@ -2980,7 +2937,7 @@ static int radeon_cp_cmdbuf(DRM_IOCTL_ARGS) | |||
2980 | break; | 2937 | break; |
2981 | case RADEON_CMD_VECLINEAR: | 2938 | case RADEON_CMD_VECLINEAR: |
2982 | DRM_DEBUG("RADEON_CMD_VECLINEAR\n"); | 2939 | DRM_DEBUG("RADEON_CMD_VECLINEAR\n"); |
2983 | if (radeon_emit_veclinear(dev_priv, header, &cmdbuf)) { | 2940 | if (radeon_emit_veclinear(dev_priv, header, cmdbuf)) { |
2984 | DRM_ERROR("radeon_emit_veclinear failed\n"); | 2941 | DRM_ERROR("radeon_emit_veclinear failed\n"); |
2985 | goto err; | 2942 | goto err; |
2986 | } | 2943 | } |
@@ -2989,7 +2946,7 @@ static int radeon_cp_cmdbuf(DRM_IOCTL_ARGS) | |||
2989 | default: | 2946 | default: |
2990 | DRM_ERROR("bad cmd_type %d at %p\n", | 2947 | DRM_ERROR("bad cmd_type %d at %p\n", |
2991 | header.header.cmd_type, | 2948 | header.header.cmd_type, |
2992 | cmdbuf.buf - sizeof(header)); | 2949 | cmdbuf->buf - sizeof(header)); |
2993 | goto err; | 2950 | goto err; |
2994 | } | 2951 | } |
2995 | } | 2952 | } |
@@ -3007,19 +2964,15 @@ static int radeon_cp_cmdbuf(DRM_IOCTL_ARGS) | |||
3007 | return -EINVAL; | 2964 | return -EINVAL; |
3008 | } | 2965 | } |
3009 | 2966 | ||
3010 | static int radeon_cp_getparam(DRM_IOCTL_ARGS) | 2967 | static int radeon_cp_getparam(struct drm_device *dev, void *data, struct drm_file *file_priv) |
3011 | { | 2968 | { |
3012 | DRM_DEVICE; | ||
3013 | drm_radeon_private_t *dev_priv = dev->dev_private; | 2969 | drm_radeon_private_t *dev_priv = dev->dev_private; |
3014 | drm_radeon_getparam_t param; | 2970 | drm_radeon_getparam_t *param = data; |
3015 | int value; | 2971 | int value; |
3016 | 2972 | ||
3017 | DRM_COPY_FROM_USER_IOCTL(param, (drm_radeon_getparam_t __user *) data, | ||
3018 | sizeof(param)); | ||
3019 | |||
3020 | DRM_DEBUG("pid=%d\n", DRM_CURRENTPID); | 2973 | DRM_DEBUG("pid=%d\n", DRM_CURRENTPID); |
3021 | 2974 | ||
3022 | switch (param.param) { | 2975 | switch (param->param) { |
3023 | case RADEON_PARAM_GART_BUFFER_OFFSET: | 2976 | case RADEON_PARAM_GART_BUFFER_OFFSET: |
3024 | value = dev_priv->gart_buffers_offset; | 2977 | value = dev_priv->gart_buffers_offset; |
3025 | break; | 2978 | break; |
@@ -3081,11 +3034,11 @@ static int radeon_cp_getparam(DRM_IOCTL_ARGS) | |||
3081 | value = radeon_vblank_crtc_get(dev); | 3034 | value = radeon_vblank_crtc_get(dev); |
3082 | break; | 3035 | break; |
3083 | default: | 3036 | default: |
3084 | DRM_DEBUG("Invalid parameter %d\n", param.param); | 3037 | DRM_DEBUG("Invalid parameter %d\n", param->param); |
3085 | return -EINVAL; | 3038 | return -EINVAL; |
3086 | } | 3039 | } |
3087 | 3040 | ||
3088 | if (DRM_COPY_TO_USER(param.value, &value, sizeof(int))) { | 3041 | if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) { |
3089 | DRM_ERROR("copy_to_user\n"); | 3042 | DRM_ERROR("copy_to_user\n"); |
3090 | return -EFAULT; | 3043 | return -EFAULT; |
3091 | } | 3044 | } |
@@ -3093,28 +3046,25 @@ static int radeon_cp_getparam(DRM_IOCTL_ARGS) | |||
3093 | return 0; | 3046 | return 0; |
3094 | } | 3047 | } |
3095 | 3048 | ||
3096 | static int radeon_cp_setparam(DRM_IOCTL_ARGS) | 3049 | static int radeon_cp_setparam(struct drm_device *dev, void *data, struct drm_file *file_priv) |
3097 | { | 3050 | { |
3098 | DRM_DEVICE; | ||
3099 | drm_radeon_private_t *dev_priv = dev->dev_private; | 3051 | drm_radeon_private_t *dev_priv = dev->dev_private; |
3100 | drm_radeon_setparam_t sp; | 3052 | drm_radeon_setparam_t *sp = data; |
3101 | struct drm_radeon_driver_file_fields *radeon_priv; | 3053 | struct drm_radeon_driver_file_fields *radeon_priv; |
3102 | 3054 | ||
3103 | DRM_COPY_FROM_USER_IOCTL(sp, (drm_radeon_setparam_t __user *) data, | 3055 | switch (sp->param) { |
3104 | sizeof(sp)); | ||
3105 | |||
3106 | switch (sp.param) { | ||
3107 | case RADEON_SETPARAM_FB_LOCATION: | 3056 | case RADEON_SETPARAM_FB_LOCATION: |
3108 | radeon_priv = file_priv->driver_priv; | 3057 | radeon_priv = file_priv->driver_priv; |
3109 | radeon_priv->radeon_fb_delta = dev_priv->fb_location - sp.value; | 3058 | radeon_priv->radeon_fb_delta = dev_priv->fb_location - |
3059 | sp->value; | ||
3110 | break; | 3060 | break; |
3111 | case RADEON_SETPARAM_SWITCH_TILING: | 3061 | case RADEON_SETPARAM_SWITCH_TILING: |
3112 | if (sp.value == 0) { | 3062 | if (sp->value == 0) { |
3113 | DRM_DEBUG("color tiling disabled\n"); | 3063 | DRM_DEBUG("color tiling disabled\n"); |
3114 | dev_priv->front_pitch_offset &= ~RADEON_DST_TILE_MACRO; | 3064 | dev_priv->front_pitch_offset &= ~RADEON_DST_TILE_MACRO; |
3115 | dev_priv->back_pitch_offset &= ~RADEON_DST_TILE_MACRO; | 3065 | dev_priv->back_pitch_offset &= ~RADEON_DST_TILE_MACRO; |
3116 | dev_priv->sarea_priv->tiling_enabled = 0; | 3066 | dev_priv->sarea_priv->tiling_enabled = 0; |
3117 | } else if (sp.value == 1) { | 3067 | } else if (sp->value == 1) { |
3118 | DRM_DEBUG("color tiling enabled\n"); | 3068 | DRM_DEBUG("color tiling enabled\n"); |
3119 | dev_priv->front_pitch_offset |= RADEON_DST_TILE_MACRO; | 3069 | dev_priv->front_pitch_offset |= RADEON_DST_TILE_MACRO; |
3120 | dev_priv->back_pitch_offset |= RADEON_DST_TILE_MACRO; | 3070 | dev_priv->back_pitch_offset |= RADEON_DST_TILE_MACRO; |
@@ -3122,22 +3072,22 @@ static int radeon_cp_setparam(DRM_IOCTL_ARGS) | |||
3122 | } | 3072 | } |
3123 | break; | 3073 | break; |
3124 | case RADEON_SETPARAM_PCIGART_LOCATION: | 3074 | case RADEON_SETPARAM_PCIGART_LOCATION: |
3125 | dev_priv->pcigart_offset = sp.value; | 3075 | dev_priv->pcigart_offset = sp->value; |
3126 | dev_priv->pcigart_offset_set = 1; | 3076 | dev_priv->pcigart_offset_set = 1; |
3127 | break; | 3077 | break; |
3128 | case RADEON_SETPARAM_NEW_MEMMAP: | 3078 | case RADEON_SETPARAM_NEW_MEMMAP: |
3129 | dev_priv->new_memmap = sp.value; | 3079 | dev_priv->new_memmap = sp->value; |
3130 | break; | 3080 | break; |
3131 | case RADEON_SETPARAM_PCIGART_TABLE_SIZE: | 3081 | case RADEON_SETPARAM_PCIGART_TABLE_SIZE: |
3132 | dev_priv->gart_info.table_size = sp.value; | 3082 | dev_priv->gart_info.table_size = sp->value; |
3133 | if (dev_priv->gart_info.table_size < RADEON_PCIGART_TABLE_SIZE) | 3083 | if (dev_priv->gart_info.table_size < RADEON_PCIGART_TABLE_SIZE) |
3134 | dev_priv->gart_info.table_size = RADEON_PCIGART_TABLE_SIZE; | 3084 | dev_priv->gart_info.table_size = RADEON_PCIGART_TABLE_SIZE; |
3135 | break; | 3085 | break; |
3136 | case RADEON_SETPARAM_VBLANK_CRTC: | 3086 | case RADEON_SETPARAM_VBLANK_CRTC: |
3137 | return radeon_vblank_crtc_set(dev, sp.value); | 3087 | return radeon_vblank_crtc_set(dev, sp->value); |
3138 | break; | 3088 | break; |
3139 | default: | 3089 | default: |
3140 | DRM_DEBUG("Invalid parameter %d\n", sp.param); | 3090 | DRM_DEBUG("Invalid parameter %d\n", sp->param); |
3141 | return -EINVAL; | 3091 | return -EINVAL; |
3142 | } | 3092 | } |
3143 | 3093 | ||
@@ -3205,34 +3155,34 @@ void radeon_driver_postclose(struct drm_device *dev, struct drm_file *file_priv) | |||
3205 | drm_free(radeon_priv, sizeof(*radeon_priv), DRM_MEM_FILES); | 3155 | drm_free(radeon_priv, sizeof(*radeon_priv), DRM_MEM_FILES); |
3206 | } | 3156 | } |
3207 | 3157 | ||
3208 | drm_ioctl_desc_t radeon_ioctls[] = { | 3158 | struct drm_ioctl_desc radeon_ioctls[] = { |
3209 | [DRM_IOCTL_NR(DRM_RADEON_CP_INIT)] = {radeon_cp_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY}, | 3159 | DRM_IOCTL_DEF(DRM_RADEON_CP_INIT, radeon_cp_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), |
3210 | [DRM_IOCTL_NR(DRM_RADEON_CP_START)] = {radeon_cp_start, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY}, | 3160 | DRM_IOCTL_DEF(DRM_RADEON_CP_START, radeon_cp_start, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), |
3211 | [DRM_IOCTL_NR(DRM_RADEON_CP_STOP)] = {radeon_cp_stop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY}, | 3161 | DRM_IOCTL_DEF(DRM_RADEON_CP_STOP, radeon_cp_stop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), |
3212 | [DRM_IOCTL_NR(DRM_RADEON_CP_RESET)] = {radeon_cp_reset, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY}, | 3162 | DRM_IOCTL_DEF(DRM_RADEON_CP_RESET, radeon_cp_reset, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), |
3213 | [DRM_IOCTL_NR(DRM_RADEON_CP_IDLE)] = {radeon_cp_idle, DRM_AUTH}, | 3163 | DRM_IOCTL_DEF(DRM_RADEON_CP_IDLE, radeon_cp_idle, DRM_AUTH), |
3214 | [DRM_IOCTL_NR(DRM_RADEON_CP_RESUME)] = {radeon_cp_resume, DRM_AUTH}, | 3164 | DRM_IOCTL_DEF(DRM_RADEON_CP_RESUME, radeon_cp_resume, DRM_AUTH), |
3215 | [DRM_IOCTL_NR(DRM_RADEON_RESET)] = {radeon_engine_reset, DRM_AUTH}, | 3165 | DRM_IOCTL_DEF(DRM_RADEON_RESET, radeon_engine_reset, DRM_AUTH), |
3216 | [DRM_IOCTL_NR(DRM_RADEON_FULLSCREEN)] = {radeon_fullscreen, DRM_AUTH}, | 3166 | DRM_IOCTL_DEF(DRM_RADEON_FULLSCREEN, radeon_fullscreen, DRM_AUTH), |
3217 | [DRM_IOCTL_NR(DRM_RADEON_SWAP)] = {radeon_cp_swap, DRM_AUTH}, | 3167 | DRM_IOCTL_DEF(DRM_RADEON_SWAP, radeon_cp_swap, DRM_AUTH), |
3218 | [DRM_IOCTL_NR(DRM_RADEON_CLEAR)] = {radeon_cp_clear, DRM_AUTH}, | 3168 | DRM_IOCTL_DEF(DRM_RADEON_CLEAR, radeon_cp_clear, DRM_AUTH), |
3219 | [DRM_IOCTL_NR(DRM_RADEON_VERTEX)] = {radeon_cp_vertex, DRM_AUTH}, | 3169 | DRM_IOCTL_DEF(DRM_RADEON_VERTEX, radeon_cp_vertex, DRM_AUTH), |
3220 | [DRM_IOCTL_NR(DRM_RADEON_INDICES)] = {radeon_cp_indices, DRM_AUTH}, | 3170 | DRM_IOCTL_DEF(DRM_RADEON_INDICES, radeon_cp_indices, DRM_AUTH), |
3221 | [DRM_IOCTL_NR(DRM_RADEON_TEXTURE)] = {radeon_cp_texture, DRM_AUTH}, | 3171 | DRM_IOCTL_DEF(DRM_RADEON_TEXTURE, radeon_cp_texture, DRM_AUTH), |
3222 | [DRM_IOCTL_NR(DRM_RADEON_STIPPLE)] = {radeon_cp_stipple, DRM_AUTH}, | 3172 | DRM_IOCTL_DEF(DRM_RADEON_STIPPLE, radeon_cp_stipple, DRM_AUTH), |
3223 | [DRM_IOCTL_NR(DRM_RADEON_INDIRECT)] = {radeon_cp_indirect, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY}, | 3173 | DRM_IOCTL_DEF(DRM_RADEON_INDIRECT, radeon_cp_indirect, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), |
3224 | [DRM_IOCTL_NR(DRM_RADEON_VERTEX2)] = {radeon_cp_vertex2, DRM_AUTH}, | 3174 | DRM_IOCTL_DEF(DRM_RADEON_VERTEX2, radeon_cp_vertex2, DRM_AUTH), |
3225 | [DRM_IOCTL_NR(DRM_RADEON_CMDBUF)] = {radeon_cp_cmdbuf, DRM_AUTH}, | 3175 | DRM_IOCTL_DEF(DRM_RADEON_CMDBUF, radeon_cp_cmdbuf, DRM_AUTH), |
3226 | [DRM_IOCTL_NR(DRM_RADEON_GETPARAM)] = {radeon_cp_getparam, DRM_AUTH}, | 3176 | DRM_IOCTL_DEF(DRM_RADEON_GETPARAM, radeon_cp_getparam, DRM_AUTH), |
3227 | [DRM_IOCTL_NR(DRM_RADEON_FLIP)] = {radeon_cp_flip, DRM_AUTH}, | 3177 | DRM_IOCTL_DEF(DRM_RADEON_FLIP, radeon_cp_flip, DRM_AUTH), |
3228 | [DRM_IOCTL_NR(DRM_RADEON_ALLOC)] = {radeon_mem_alloc, DRM_AUTH}, | 3178 | DRM_IOCTL_DEF(DRM_RADEON_ALLOC, radeon_mem_alloc, DRM_AUTH), |
3229 | [DRM_IOCTL_NR(DRM_RADEON_FREE)] = {radeon_mem_free, DRM_AUTH}, | 3179 | DRM_IOCTL_DEF(DRM_RADEON_FREE, radeon_mem_free, DRM_AUTH), |
3230 | [DRM_IOCTL_NR(DRM_RADEON_INIT_HEAP)] = {radeon_mem_init_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY}, | 3180 | DRM_IOCTL_DEF(DRM_RADEON_INIT_HEAP, radeon_mem_init_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), |
3231 | [DRM_IOCTL_NR(DRM_RADEON_IRQ_EMIT)] = {radeon_irq_emit, DRM_AUTH}, | 3181 | DRM_IOCTL_DEF(DRM_RADEON_IRQ_EMIT, radeon_irq_emit, DRM_AUTH), |
3232 | [DRM_IOCTL_NR(DRM_RADEON_IRQ_WAIT)] = {radeon_irq_wait, DRM_AUTH}, | 3182 | DRM_IOCTL_DEF(DRM_RADEON_IRQ_WAIT, radeon_irq_wait, DRM_AUTH), |
3233 | [DRM_IOCTL_NR(DRM_RADEON_SETPARAM)] = {radeon_cp_setparam, DRM_AUTH}, | 3183 | DRM_IOCTL_DEF(DRM_RADEON_SETPARAM, radeon_cp_setparam, DRM_AUTH), |
3234 | [DRM_IOCTL_NR(DRM_RADEON_SURF_ALLOC)] = {radeon_surface_alloc, DRM_AUTH}, | 3184 | DRM_IOCTL_DEF(DRM_RADEON_SURF_ALLOC, radeon_surface_alloc, DRM_AUTH), |
3235 | [DRM_IOCTL_NR(DRM_RADEON_SURF_FREE)] = {radeon_surface_free, DRM_AUTH} | 3185 | DRM_IOCTL_DEF(DRM_RADEON_SURF_FREE, radeon_surface_free, DRM_AUTH) |
3236 | }; | 3186 | }; |
3237 | 3187 | ||
3238 | int radeon_max_ioctl = DRM_ARRAY_SIZE(radeon_ioctls); | 3188 | int radeon_max_ioctl = DRM_ARRAY_SIZE(radeon_ioctls); |