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authorEric Anholt <eric@anholt.net>2007-08-25 06:23:09 -0400
committerDave Airlie <airlied@optimus.(none)>2007-10-14 20:38:20 -0400
commit6c340eac0285f3d62406d2d902d0e96fbf2a5dc0 (patch)
treea92039951cb7eaced306cfff2bad6af0ac5257ad /drivers/char/drm/radeon_state.c
parent20caafa6ecb2487d9b223aa33e7cc704f912a758 (diff)
drm: Replace filp in ioctl arguments with drm_file *file_priv.
As a fallout, replace filp storage with file_priv storage for "unique identifier of a client" all over the DRM. There is a 1:1 mapping, so this should be a noop. This could be a minor performance improvement, as everyth on Linux dereferenced filp to get file_priv anyway, while only the mmap ioct went the other direction. Signed-off-by: Dave Airlie <airlied@linux.ie>
Diffstat (limited to 'drivers/char/drm/radeon_state.c')
-rw-r--r--drivers/char/drm/radeon_state.c195
1 files changed, 92 insertions, 103 deletions
diff --git a/drivers/char/drm/radeon_state.c b/drivers/char/drm/radeon_state.c
index 4bc0909b226f..bd1aafdc3c29 100644
--- a/drivers/char/drm/radeon_state.c
+++ b/drivers/char/drm/radeon_state.c
@@ -39,7 +39,7 @@
39 39
40static __inline__ int radeon_check_and_fixup_offset(drm_radeon_private_t * 40static __inline__ int radeon_check_and_fixup_offset(drm_radeon_private_t *
41 dev_priv, 41 dev_priv,
42 struct drm_file * filp_priv, 42 struct drm_file * file_priv,
43 u32 *offset) 43 u32 *offset)
44{ 44{
45 u64 off = *offset; 45 u64 off = *offset;
@@ -71,7 +71,7 @@ static __inline__ int radeon_check_and_fixup_offset(drm_radeon_private_t *
71 * magic offset we get from SETPARAM or calculated from fb_location 71 * magic offset we get from SETPARAM or calculated from fb_location
72 */ 72 */
73 if (off < (dev_priv->fb_size + dev_priv->gart_size)) { 73 if (off < (dev_priv->fb_size + dev_priv->gart_size)) {
74 radeon_priv = filp_priv->driver_priv; 74 radeon_priv = file_priv->driver_priv;
75 off += radeon_priv->radeon_fb_delta; 75 off += radeon_priv->radeon_fb_delta;
76 } 76 }
77 77
@@ -90,13 +90,13 @@ static __inline__ int radeon_check_and_fixup_offset(drm_radeon_private_t *
90 90
91static __inline__ int radeon_check_and_fixup_packets(drm_radeon_private_t * 91static __inline__ int radeon_check_and_fixup_packets(drm_radeon_private_t *
92 dev_priv, 92 dev_priv,
93 struct drm_file * filp_priv, 93 struct drm_file *file_priv,
94 int id, u32 *data) 94 int id, u32 *data)
95{ 95{
96 switch (id) { 96 switch (id) {
97 97
98 case RADEON_EMIT_PP_MISC: 98 case RADEON_EMIT_PP_MISC:
99 if (radeon_check_and_fixup_offset(dev_priv, filp_priv, 99 if (radeon_check_and_fixup_offset(dev_priv, file_priv,
100 &data[(RADEON_RB3D_DEPTHOFFSET - RADEON_PP_MISC) / 4])) { 100 &data[(RADEON_RB3D_DEPTHOFFSET - RADEON_PP_MISC) / 4])) {
101 DRM_ERROR("Invalid depth buffer offset\n"); 101 DRM_ERROR("Invalid depth buffer offset\n");
102 return -EINVAL; 102 return -EINVAL;
@@ -104,7 +104,7 @@ static __inline__ int radeon_check_and_fixup_packets(drm_radeon_private_t *
104 break; 104 break;
105 105
106 case RADEON_EMIT_PP_CNTL: 106 case RADEON_EMIT_PP_CNTL:
107 if (radeon_check_and_fixup_offset(dev_priv, filp_priv, 107 if (radeon_check_and_fixup_offset(dev_priv, file_priv,
108 &data[(RADEON_RB3D_COLOROFFSET - RADEON_PP_CNTL) / 4])) { 108 &data[(RADEON_RB3D_COLOROFFSET - RADEON_PP_CNTL) / 4])) {
109 DRM_ERROR("Invalid colour buffer offset\n"); 109 DRM_ERROR("Invalid colour buffer offset\n");
110 return -EINVAL; 110 return -EINVAL;
@@ -117,7 +117,7 @@ static __inline__ int radeon_check_and_fixup_packets(drm_radeon_private_t *
117 case R200_EMIT_PP_TXOFFSET_3: 117 case R200_EMIT_PP_TXOFFSET_3:
118 case R200_EMIT_PP_TXOFFSET_4: 118 case R200_EMIT_PP_TXOFFSET_4:
119 case R200_EMIT_PP_TXOFFSET_5: 119 case R200_EMIT_PP_TXOFFSET_5:
120 if (radeon_check_and_fixup_offset(dev_priv, filp_priv, 120 if (radeon_check_and_fixup_offset(dev_priv, file_priv,
121 &data[0])) { 121 &data[0])) {
122 DRM_ERROR("Invalid R200 texture offset\n"); 122 DRM_ERROR("Invalid R200 texture offset\n");
123 return -EINVAL; 123 return -EINVAL;
@@ -127,7 +127,7 @@ static __inline__ int radeon_check_and_fixup_packets(drm_radeon_private_t *
127 case RADEON_EMIT_PP_TXFILTER_0: 127 case RADEON_EMIT_PP_TXFILTER_0:
128 case RADEON_EMIT_PP_TXFILTER_1: 128 case RADEON_EMIT_PP_TXFILTER_1:
129 case RADEON_EMIT_PP_TXFILTER_2: 129 case RADEON_EMIT_PP_TXFILTER_2:
130 if (radeon_check_and_fixup_offset(dev_priv, filp_priv, 130 if (radeon_check_and_fixup_offset(dev_priv, file_priv,
131 &data[(RADEON_PP_TXOFFSET_0 - RADEON_PP_TXFILTER_0) / 4])) { 131 &data[(RADEON_PP_TXOFFSET_0 - RADEON_PP_TXFILTER_0) / 4])) {
132 DRM_ERROR("Invalid R100 texture offset\n"); 132 DRM_ERROR("Invalid R100 texture offset\n");
133 return -EINVAL; 133 return -EINVAL;
@@ -143,7 +143,7 @@ static __inline__ int radeon_check_and_fixup_packets(drm_radeon_private_t *
143 int i; 143 int i;
144 for (i = 0; i < 5; i++) { 144 for (i = 0; i < 5; i++) {
145 if (radeon_check_and_fixup_offset(dev_priv, 145 if (radeon_check_and_fixup_offset(dev_priv,
146 filp_priv, 146 file_priv,
147 &data[i])) { 147 &data[i])) {
148 DRM_ERROR 148 DRM_ERROR
149 ("Invalid R200 cubic texture offset\n"); 149 ("Invalid R200 cubic texture offset\n");
@@ -159,7 +159,7 @@ static __inline__ int radeon_check_and_fixup_packets(drm_radeon_private_t *
159 int i; 159 int i;
160 for (i = 0; i < 5; i++) { 160 for (i = 0; i < 5; i++) {
161 if (radeon_check_and_fixup_offset(dev_priv, 161 if (radeon_check_and_fixup_offset(dev_priv,
162 filp_priv, 162 file_priv,
163 &data[i])) { 163 &data[i])) {
164 DRM_ERROR 164 DRM_ERROR
165 ("Invalid R100 cubic texture offset\n"); 165 ("Invalid R100 cubic texture offset\n");
@@ -264,7 +264,7 @@ static __inline__ int radeon_check_and_fixup_packets(drm_radeon_private_t *
264 264
265static __inline__ int radeon_check_and_fixup_packet3(drm_radeon_private_t * 265static __inline__ int radeon_check_and_fixup_packet3(drm_radeon_private_t *
266 dev_priv, 266 dev_priv,
267 struct drm_file *filp_priv, 267 struct drm_file *file_priv,
268 drm_radeon_kcmd_buffer_t * 268 drm_radeon_kcmd_buffer_t *
269 cmdbuf, 269 cmdbuf,
270 unsigned int *cmdsz) 270 unsigned int *cmdsz)
@@ -326,7 +326,8 @@ static __inline__ int radeon_check_and_fixup_packet3(drm_radeon_private_t *
326 i = 2; 326 i = 2;
327 while ((k < narrays) && (i < (count + 2))) { 327 while ((k < narrays) && (i < (count + 2))) {
328 i++; /* skip attribute field */ 328 i++; /* skip attribute field */
329 if (radeon_check_and_fixup_offset(dev_priv, filp_priv, &cmd[i])) { 329 if (radeon_check_and_fixup_offset(dev_priv, file_priv,
330 &cmd[i])) {
330 DRM_ERROR 331 DRM_ERROR
331 ("Invalid offset (k=%d i=%d) in 3D_LOAD_VBPNTR packet.\n", 332 ("Invalid offset (k=%d i=%d) in 3D_LOAD_VBPNTR packet.\n",
332 k, i); 333 k, i);
@@ -337,7 +338,9 @@ static __inline__ int radeon_check_and_fixup_packet3(drm_radeon_private_t *
337 if (k == narrays) 338 if (k == narrays)
338 break; 339 break;
339 /* have one more to process, they come in pairs */ 340 /* have one more to process, they come in pairs */
340 if (radeon_check_and_fixup_offset(dev_priv, filp_priv, &cmd[i])) { 341 if (radeon_check_and_fixup_offset(dev_priv,
342 file_priv, &cmd[i]))
343 {
341 DRM_ERROR 344 DRM_ERROR
342 ("Invalid offset (k=%d i=%d) in 3D_LOAD_VBPNTR packet.\n", 345 ("Invalid offset (k=%d i=%d) in 3D_LOAD_VBPNTR packet.\n",
343 k, i); 346 k, i);
@@ -360,7 +363,7 @@ static __inline__ int radeon_check_and_fixup_packet3(drm_radeon_private_t *
360 DRM_ERROR("Invalid 3d packet for r200-class chip\n"); 363 DRM_ERROR("Invalid 3d packet for r200-class chip\n");
361 return -EINVAL; 364 return -EINVAL;
362 } 365 }
363 if (radeon_check_and_fixup_offset(dev_priv, filp_priv, &cmd[1])) { 366 if (radeon_check_and_fixup_offset(dev_priv, file_priv, &cmd[1])) {
364 DRM_ERROR("Invalid rndr_gen_indx offset\n"); 367 DRM_ERROR("Invalid rndr_gen_indx offset\n");
365 return -EINVAL; 368 return -EINVAL;
366 } 369 }
@@ -375,7 +378,7 @@ static __inline__ int radeon_check_and_fixup_packet3(drm_radeon_private_t *
375 DRM_ERROR("Invalid indx_buffer reg address %08X\n", cmd[1]); 378 DRM_ERROR("Invalid indx_buffer reg address %08X\n", cmd[1]);
376 return -EINVAL; 379 return -EINVAL;
377 } 380 }
378 if (radeon_check_and_fixup_offset(dev_priv, filp_priv, &cmd[2])) { 381 if (radeon_check_and_fixup_offset(dev_priv, file_priv, &cmd[2])) {
379 DRM_ERROR("Invalid indx_buffer offset is %08X\n", cmd[2]); 382 DRM_ERROR("Invalid indx_buffer offset is %08X\n", cmd[2]);
380 return -EINVAL; 383 return -EINVAL;
381 } 384 }
@@ -389,7 +392,7 @@ static __inline__ int radeon_check_and_fixup_packet3(drm_radeon_private_t *
389 | RADEON_GMC_DST_PITCH_OFFSET_CNTL)) { 392 | RADEON_GMC_DST_PITCH_OFFSET_CNTL)) {
390 offset = cmd[2] << 10; 393 offset = cmd[2] << 10;
391 if (radeon_check_and_fixup_offset 394 if (radeon_check_and_fixup_offset
392 (dev_priv, filp_priv, &offset)) { 395 (dev_priv, file_priv, &offset)) {
393 DRM_ERROR("Invalid first packet offset\n"); 396 DRM_ERROR("Invalid first packet offset\n");
394 return -EINVAL; 397 return -EINVAL;
395 } 398 }
@@ -400,7 +403,7 @@ static __inline__ int radeon_check_and_fixup_packet3(drm_radeon_private_t *
400 (cmd[1] & RADEON_GMC_DST_PITCH_OFFSET_CNTL)) { 403 (cmd[1] & RADEON_GMC_DST_PITCH_OFFSET_CNTL)) {
401 offset = cmd[3] << 10; 404 offset = cmd[3] << 10;
402 if (radeon_check_and_fixup_offset 405 if (radeon_check_and_fixup_offset
403 (dev_priv, filp_priv, &offset)) { 406 (dev_priv, file_priv, &offset)) {
404 DRM_ERROR("Invalid second packet offset\n"); 407 DRM_ERROR("Invalid second packet offset\n");
405 return -EINVAL; 408 return -EINVAL;
406 } 409 }
@@ -439,7 +442,7 @@ static __inline__ void radeon_emit_clip_rect(drm_radeon_private_t * dev_priv,
439/* Emit 1.1 state 442/* Emit 1.1 state
440 */ 443 */
441static int radeon_emit_state(drm_radeon_private_t * dev_priv, 444static int radeon_emit_state(drm_radeon_private_t * dev_priv,
442 struct drm_file * filp_priv, 445 struct drm_file *file_priv,
443 drm_radeon_context_regs_t * ctx, 446 drm_radeon_context_regs_t * ctx,
444 drm_radeon_texture_regs_t * tex, 447 drm_radeon_texture_regs_t * tex,
445 unsigned int dirty) 448 unsigned int dirty)
@@ -448,13 +451,13 @@ static int radeon_emit_state(drm_radeon_private_t * dev_priv,
448 DRM_DEBUG("dirty=0x%08x\n", dirty); 451 DRM_DEBUG("dirty=0x%08x\n", dirty);
449 452
450 if (dirty & RADEON_UPLOAD_CONTEXT) { 453 if (dirty & RADEON_UPLOAD_CONTEXT) {
451 if (radeon_check_and_fixup_offset(dev_priv, filp_priv, 454 if (radeon_check_and_fixup_offset(dev_priv, file_priv,
452 &ctx->rb3d_depthoffset)) { 455 &ctx->rb3d_depthoffset)) {
453 DRM_ERROR("Invalid depth buffer offset\n"); 456 DRM_ERROR("Invalid depth buffer offset\n");
454 return -EINVAL; 457 return -EINVAL;
455 } 458 }
456 459
457 if (radeon_check_and_fixup_offset(dev_priv, filp_priv, 460 if (radeon_check_and_fixup_offset(dev_priv, file_priv,
458 &ctx->rb3d_coloroffset)) { 461 &ctx->rb3d_coloroffset)) {
459 DRM_ERROR("Invalid depth buffer offset\n"); 462 DRM_ERROR("Invalid depth buffer offset\n");
460 return -EINVAL; 463 return -EINVAL;
@@ -543,7 +546,7 @@ static int radeon_emit_state(drm_radeon_private_t * dev_priv,
543 } 546 }
544 547
545 if (dirty & RADEON_UPLOAD_TEX0) { 548 if (dirty & RADEON_UPLOAD_TEX0) {
546 if (radeon_check_and_fixup_offset(dev_priv, filp_priv, 549 if (radeon_check_and_fixup_offset(dev_priv, file_priv,
547 &tex[0].pp_txoffset)) { 550 &tex[0].pp_txoffset)) {
548 DRM_ERROR("Invalid texture offset for unit 0\n"); 551 DRM_ERROR("Invalid texture offset for unit 0\n");
549 return -EINVAL; 552 return -EINVAL;
@@ -563,7 +566,7 @@ static int radeon_emit_state(drm_radeon_private_t * dev_priv,
563 } 566 }
564 567
565 if (dirty & RADEON_UPLOAD_TEX1) { 568 if (dirty & RADEON_UPLOAD_TEX1) {
566 if (radeon_check_and_fixup_offset(dev_priv, filp_priv, 569 if (radeon_check_and_fixup_offset(dev_priv, file_priv,
567 &tex[1].pp_txoffset)) { 570 &tex[1].pp_txoffset)) {
568 DRM_ERROR("Invalid texture offset for unit 1\n"); 571 DRM_ERROR("Invalid texture offset for unit 1\n");
569 return -EINVAL; 572 return -EINVAL;
@@ -583,7 +586,7 @@ static int radeon_emit_state(drm_radeon_private_t * dev_priv,
583 } 586 }
584 587
585 if (dirty & RADEON_UPLOAD_TEX2) { 588 if (dirty & RADEON_UPLOAD_TEX2) {
586 if (radeon_check_and_fixup_offset(dev_priv, filp_priv, 589 if (radeon_check_and_fixup_offset(dev_priv, file_priv,
587 &tex[2].pp_txoffset)) { 590 &tex[2].pp_txoffset)) {
588 DRM_ERROR("Invalid texture offset for unit 2\n"); 591 DRM_ERROR("Invalid texture offset for unit 2\n");
589 return -EINVAL; 592 return -EINVAL;
@@ -608,7 +611,7 @@ static int radeon_emit_state(drm_radeon_private_t * dev_priv,
608/* Emit 1.2 state 611/* Emit 1.2 state
609 */ 612 */
610static int radeon_emit_state2(drm_radeon_private_t * dev_priv, 613static int radeon_emit_state2(drm_radeon_private_t * dev_priv,
611 struct drm_file * filp_priv, 614 struct drm_file *file_priv,
612 drm_radeon_state_t * state) 615 drm_radeon_state_t * state)
613{ 616{
614 RING_LOCALS; 617 RING_LOCALS;
@@ -621,7 +624,7 @@ static int radeon_emit_state2(drm_radeon_private_t * dev_priv,
621 ADVANCE_RING(); 624 ADVANCE_RING();
622 } 625 }
623 626
624 return radeon_emit_state(dev_priv, filp_priv, &state->context, 627 return radeon_emit_state(dev_priv, file_priv, &state->context,
625 state->tex, state->dirty); 628 state->tex, state->dirty);
626} 629}
627 630
@@ -1646,13 +1649,12 @@ static void radeon_cp_dispatch_indices(struct drm_device * dev,
1646 1649
1647#define RADEON_MAX_TEXTURE_SIZE RADEON_BUFFER_SIZE 1650#define RADEON_MAX_TEXTURE_SIZE RADEON_BUFFER_SIZE
1648 1651
1649static int radeon_cp_dispatch_texture(DRMFILE filp, 1652static int radeon_cp_dispatch_texture(struct drm_device * dev,
1650 struct drm_device * dev, 1653 struct drm_file *file_priv,
1651 drm_radeon_texture_t * tex, 1654 drm_radeon_texture_t * tex,
1652 drm_radeon_tex_image_t * image) 1655 drm_radeon_tex_image_t * image)
1653{ 1656{
1654 drm_radeon_private_t *dev_priv = dev->dev_private; 1657 drm_radeon_private_t *dev_priv = dev->dev_private;
1655 struct drm_file *filp_priv;
1656 struct drm_buf *buf; 1658 struct drm_buf *buf;
1657 u32 format; 1659 u32 format;
1658 u32 *buffer; 1660 u32 *buffer;
@@ -1664,9 +1666,7 @@ static int radeon_cp_dispatch_texture(DRMFILE filp,
1664 u32 offset; 1666 u32 offset;
1665 RING_LOCALS; 1667 RING_LOCALS;
1666 1668
1667 DRM_GET_PRIV_WITH_RETURN(filp_priv, filp); 1669 if (radeon_check_and_fixup_offset(dev_priv, file_priv, &tex->offset)) {
1668
1669 if (radeon_check_and_fixup_offset(dev_priv, filp_priv, &tex->offset)) {
1670 DRM_ERROR("Invalid destination offset\n"); 1670 DRM_ERROR("Invalid destination offset\n");
1671 return -EINVAL; 1671 return -EINVAL;
1672 } 1672 }
@@ -1841,7 +1841,7 @@ static int radeon_cp_dispatch_texture(DRMFILE filp,
1841 } 1841 }
1842 1842
1843#undef RADEON_COPY_MT 1843#undef RADEON_COPY_MT
1844 buf->filp = filp; 1844 buf->file_priv = file_priv;
1845 buf->used = size; 1845 buf->used = size;
1846 offset = dev_priv->gart_buffers_offset + buf->offset; 1846 offset = dev_priv->gart_buffers_offset + buf->offset;
1847 BEGIN_RING(9); 1847 BEGIN_RING(9);
@@ -1929,7 +1929,8 @@ static void radeon_apply_surface_regs(int surf_index,
1929 * not always be available. 1929 * not always be available.
1930 */ 1930 */
1931static int alloc_surface(drm_radeon_surface_alloc_t *new, 1931static int alloc_surface(drm_radeon_surface_alloc_t *new,
1932 drm_radeon_private_t *dev_priv, DRMFILE filp) 1932 drm_radeon_private_t *dev_priv,
1933 struct drm_file *file_priv)
1933{ 1934{
1934 struct radeon_virt_surface *s; 1935 struct radeon_virt_surface *s;
1935 int i; 1936 int i;
@@ -1959,7 +1960,7 @@ static int alloc_surface(drm_radeon_surface_alloc_t *new,
1959 1960
1960 /* find a virtual surface */ 1961 /* find a virtual surface */
1961 for (i = 0; i < 2 * RADEON_MAX_SURFACES; i++) 1962 for (i = 0; i < 2 * RADEON_MAX_SURFACES; i++)
1962 if (dev_priv->virt_surfaces[i].filp == 0) 1963 if (dev_priv->virt_surfaces[i].file_priv == 0)
1963 break; 1964 break;
1964 if (i == 2 * RADEON_MAX_SURFACES) { 1965 if (i == 2 * RADEON_MAX_SURFACES) {
1965 return -1; 1966 return -1;
@@ -1977,7 +1978,7 @@ static int alloc_surface(drm_radeon_surface_alloc_t *new,
1977 s->lower = new_lower; 1978 s->lower = new_lower;
1978 s->upper = new_upper; 1979 s->upper = new_upper;
1979 s->flags = new->flags; 1980 s->flags = new->flags;
1980 s->filp = filp; 1981 s->file_priv = file_priv;
1981 dev_priv->surfaces[i].refcount++; 1982 dev_priv->surfaces[i].refcount++;
1982 dev_priv->surfaces[i].lower = s->lower; 1983 dev_priv->surfaces[i].lower = s->lower;
1983 radeon_apply_surface_regs(s->surface_index, dev_priv); 1984 radeon_apply_surface_regs(s->surface_index, dev_priv);
@@ -1993,7 +1994,7 @@ static int alloc_surface(drm_radeon_surface_alloc_t *new,
1993 s->lower = new_lower; 1994 s->lower = new_lower;
1994 s->upper = new_upper; 1995 s->upper = new_upper;
1995 s->flags = new->flags; 1996 s->flags = new->flags;
1996 s->filp = filp; 1997 s->file_priv = file_priv;
1997 dev_priv->surfaces[i].refcount++; 1998 dev_priv->surfaces[i].refcount++;
1998 dev_priv->surfaces[i].upper = s->upper; 1999 dev_priv->surfaces[i].upper = s->upper;
1999 radeon_apply_surface_regs(s->surface_index, dev_priv); 2000 radeon_apply_surface_regs(s->surface_index, dev_priv);
@@ -2009,7 +2010,7 @@ static int alloc_surface(drm_radeon_surface_alloc_t *new,
2009 s->lower = new_lower; 2010 s->lower = new_lower;
2010 s->upper = new_upper; 2011 s->upper = new_upper;
2011 s->flags = new->flags; 2012 s->flags = new->flags;
2012 s->filp = filp; 2013 s->file_priv = file_priv;
2013 dev_priv->surfaces[i].refcount = 1; 2014 dev_priv->surfaces[i].refcount = 1;
2014 dev_priv->surfaces[i].lower = s->lower; 2015 dev_priv->surfaces[i].lower = s->lower;
2015 dev_priv->surfaces[i].upper = s->upper; 2016 dev_priv->surfaces[i].upper = s->upper;
@@ -2023,7 +2024,8 @@ static int alloc_surface(drm_radeon_surface_alloc_t *new,
2023 return -1; 2024 return -1;
2024} 2025}
2025 2026
2026static int free_surface(DRMFILE filp, drm_radeon_private_t * dev_priv, 2027static int free_surface(struct drm_file *file_priv,
2028 drm_radeon_private_t * dev_priv,
2027 int lower) 2029 int lower)
2028{ 2030{
2029 struct radeon_virt_surface *s; 2031 struct radeon_virt_surface *s;
@@ -2031,8 +2033,9 @@ static int free_surface(DRMFILE filp, drm_radeon_private_t * dev_priv,
2031 /* find the virtual surface */ 2033 /* find the virtual surface */
2032 for (i = 0; i < 2 * RADEON_MAX_SURFACES; i++) { 2034 for (i = 0; i < 2 * RADEON_MAX_SURFACES; i++) {
2033 s = &(dev_priv->virt_surfaces[i]); 2035 s = &(dev_priv->virt_surfaces[i]);
2034 if (s->filp) { 2036 if (s->file_priv) {
2035 if ((lower == s->lower) && (filp == s->filp)) { 2037 if ((lower == s->lower) && (file_priv == s->file_priv))
2038 {
2036 if (dev_priv->surfaces[s->surface_index]. 2039 if (dev_priv->surfaces[s->surface_index].
2037 lower == s->lower) 2040 lower == s->lower)
2038 dev_priv->surfaces[s->surface_index]. 2041 dev_priv->surfaces[s->surface_index].
@@ -2048,7 +2051,7 @@ static int free_surface(DRMFILE filp, drm_radeon_private_t * dev_priv,
2048 refcount == 0) 2051 refcount == 0)
2049 dev_priv->surfaces[s->surface_index]. 2052 dev_priv->surfaces[s->surface_index].
2050 flags = 0; 2053 flags = 0;
2051 s->filp = NULL; 2054 s->file_priv = NULL;
2052 radeon_apply_surface_regs(s->surface_index, 2055 radeon_apply_surface_regs(s->surface_index,
2053 dev_priv); 2056 dev_priv);
2054 return 0; 2057 return 0;
@@ -2058,13 +2061,13 @@ static int free_surface(DRMFILE filp, drm_radeon_private_t * dev_priv,
2058 return 1; 2061 return 1;
2059} 2062}
2060 2063
2061static void radeon_surfaces_release(DRMFILE filp, 2064static void radeon_surfaces_release(struct drm_file *file_priv,
2062 drm_radeon_private_t * dev_priv) 2065 drm_radeon_private_t * dev_priv)
2063{ 2066{
2064 int i; 2067 int i;
2065 for (i = 0; i < 2 * RADEON_MAX_SURFACES; i++) { 2068 for (i = 0; i < 2 * RADEON_MAX_SURFACES; i++) {
2066 if (dev_priv->virt_surfaces[i].filp == filp) 2069 if (dev_priv->virt_surfaces[i].file_priv == file_priv)
2067 free_surface(filp, dev_priv, 2070 free_surface(file_priv, dev_priv,
2068 dev_priv->virt_surfaces[i].lower); 2071 dev_priv->virt_surfaces[i].lower);
2069 } 2072 }
2070} 2073}
@@ -2082,7 +2085,7 @@ static int radeon_surface_alloc(DRM_IOCTL_ARGS)
2082 (drm_radeon_surface_alloc_t __user *) data, 2085 (drm_radeon_surface_alloc_t __user *) data,
2083 sizeof(alloc)); 2086 sizeof(alloc));
2084 2087
2085 if (alloc_surface(&alloc, dev_priv, filp) == -1) 2088 if (alloc_surface(&alloc, dev_priv, file_priv) == -1)
2086 return -EINVAL; 2089 return -EINVAL;
2087 else 2090 else
2088 return 0; 2091 return 0;
@@ -2097,7 +2100,7 @@ static int radeon_surface_free(DRM_IOCTL_ARGS)
2097 DRM_COPY_FROM_USER_IOCTL(memfree, (drm_radeon_surface_free_t __user *) data, 2100 DRM_COPY_FROM_USER_IOCTL(memfree, (drm_radeon_surface_free_t __user *) data,
2098 sizeof(memfree)); 2101 sizeof(memfree));
2099 2102
2100 if (free_surface(filp, dev_priv, memfree.address)) 2103 if (free_surface(file_priv, dev_priv, memfree.address))
2101 return -EINVAL; 2104 return -EINVAL;
2102 else 2105 else
2103 return 0; 2106 return 0;
@@ -2112,7 +2115,7 @@ static int radeon_cp_clear(DRM_IOCTL_ARGS)
2112 drm_radeon_clear_rect_t depth_boxes[RADEON_NR_SAREA_CLIPRECTS]; 2115 drm_radeon_clear_rect_t depth_boxes[RADEON_NR_SAREA_CLIPRECTS];
2113 DRM_DEBUG("\n"); 2116 DRM_DEBUG("\n");
2114 2117
2115 LOCK_TEST_WITH_RETURN(dev, filp); 2118 LOCK_TEST_WITH_RETURN(dev, file_priv);
2116 2119
2117 DRM_COPY_FROM_USER_IOCTL(clear, (drm_radeon_clear_t __user *) data, 2120 DRM_COPY_FROM_USER_IOCTL(clear, (drm_radeon_clear_t __user *) data,
2118 sizeof(clear)); 2121 sizeof(clear));
@@ -2168,7 +2171,7 @@ static int radeon_cp_flip(DRM_IOCTL_ARGS)
2168 drm_radeon_private_t *dev_priv = dev->dev_private; 2171 drm_radeon_private_t *dev_priv = dev->dev_private;
2169 DRM_DEBUG("\n"); 2172 DRM_DEBUG("\n");
2170 2173
2171 LOCK_TEST_WITH_RETURN(dev, filp); 2174 LOCK_TEST_WITH_RETURN(dev, file_priv);
2172 2175
2173 RING_SPACE_TEST_WITH_RETURN(dev_priv); 2176 RING_SPACE_TEST_WITH_RETURN(dev_priv);
2174 2177
@@ -2188,7 +2191,7 @@ static int radeon_cp_swap(DRM_IOCTL_ARGS)
2188 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; 2191 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
2189 DRM_DEBUG("\n"); 2192 DRM_DEBUG("\n");
2190 2193
2191 LOCK_TEST_WITH_RETURN(dev, filp); 2194 LOCK_TEST_WITH_RETURN(dev, file_priv);
2192 2195
2193 RING_SPACE_TEST_WITH_RETURN(dev_priv); 2196 RING_SPACE_TEST_WITH_RETURN(dev_priv);
2194 2197
@@ -2206,16 +2209,13 @@ static int radeon_cp_vertex(DRM_IOCTL_ARGS)
2206{ 2209{
2207 DRM_DEVICE; 2210 DRM_DEVICE;
2208 drm_radeon_private_t *dev_priv = dev->dev_private; 2211 drm_radeon_private_t *dev_priv = dev->dev_private;
2209 struct drm_file *filp_priv;
2210 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; 2212 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
2211 struct drm_device_dma *dma = dev->dma; 2213 struct drm_device_dma *dma = dev->dma;
2212 struct drm_buf *buf; 2214 struct drm_buf *buf;
2213 drm_radeon_vertex_t vertex; 2215 drm_radeon_vertex_t vertex;
2214 drm_radeon_tcl_prim_t prim; 2216 drm_radeon_tcl_prim_t prim;
2215 2217
2216 LOCK_TEST_WITH_RETURN(dev, filp); 2218 LOCK_TEST_WITH_RETURN(dev, file_priv);
2217
2218 DRM_GET_PRIV_WITH_RETURN(filp_priv, filp);
2219 2219
2220 DRM_COPY_FROM_USER_IOCTL(vertex, (drm_radeon_vertex_t __user *) data, 2220 DRM_COPY_FROM_USER_IOCTL(vertex, (drm_radeon_vertex_t __user *) data,
2221 sizeof(vertex)); 2221 sizeof(vertex));
@@ -2238,9 +2238,9 @@ static int radeon_cp_vertex(DRM_IOCTL_ARGS)
2238 2238
2239 buf = dma->buflist[vertex.idx]; 2239 buf = dma->buflist[vertex.idx];
2240 2240
2241 if (buf->filp != filp) { 2241 if (buf->file_priv != file_priv) {
2242 DRM_ERROR("process %d using buffer owned by %p\n", 2242 DRM_ERROR("process %d using buffer owned by %p\n",
2243 DRM_CURRENTPID, buf->filp); 2243 DRM_CURRENTPID, buf->file_priv);
2244 return -EINVAL; 2244 return -EINVAL;
2245 } 2245 }
2246 if (buf->pending) { 2246 if (buf->pending) {
@@ -2254,7 +2254,7 @@ static int radeon_cp_vertex(DRM_IOCTL_ARGS)
2254 buf->used = vertex.count; /* not used? */ 2254 buf->used = vertex.count; /* not used? */
2255 2255
2256 if (sarea_priv->dirty & ~RADEON_UPLOAD_CLIPRECTS) { 2256 if (sarea_priv->dirty & ~RADEON_UPLOAD_CLIPRECTS) {
2257 if (radeon_emit_state(dev_priv, filp_priv, 2257 if (radeon_emit_state(dev_priv, file_priv,
2258 &sarea_priv->context_state, 2258 &sarea_priv->context_state,
2259 sarea_priv->tex_state, 2259 sarea_priv->tex_state,
2260 sarea_priv->dirty)) { 2260 sarea_priv->dirty)) {
@@ -2289,7 +2289,6 @@ static int radeon_cp_indices(DRM_IOCTL_ARGS)
2289{ 2289{
2290 DRM_DEVICE; 2290 DRM_DEVICE;
2291 drm_radeon_private_t *dev_priv = dev->dev_private; 2291 drm_radeon_private_t *dev_priv = dev->dev_private;
2292 struct drm_file *filp_priv;
2293 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; 2292 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
2294 struct drm_device_dma *dma = dev->dma; 2293 struct drm_device_dma *dma = dev->dma;
2295 struct drm_buf *buf; 2294 struct drm_buf *buf;
@@ -2297,9 +2296,7 @@ static int radeon_cp_indices(DRM_IOCTL_ARGS)
2297 drm_radeon_tcl_prim_t prim; 2296 drm_radeon_tcl_prim_t prim;
2298 int count; 2297 int count;
2299 2298
2300 LOCK_TEST_WITH_RETURN(dev, filp); 2299 LOCK_TEST_WITH_RETURN(dev, file_priv);
2301
2302 DRM_GET_PRIV_WITH_RETURN(filp_priv, filp);
2303 2300
2304 DRM_COPY_FROM_USER_IOCTL(elts, (drm_radeon_indices_t __user *) data, 2301 DRM_COPY_FROM_USER_IOCTL(elts, (drm_radeon_indices_t __user *) data,
2305 sizeof(elts)); 2302 sizeof(elts));
@@ -2322,9 +2319,9 @@ static int radeon_cp_indices(DRM_IOCTL_ARGS)
2322 2319
2323 buf = dma->buflist[elts.idx]; 2320 buf = dma->buflist[elts.idx];
2324 2321
2325 if (buf->filp != filp) { 2322 if (buf->file_priv != file_priv) {
2326 DRM_ERROR("process %d using buffer owned by %p\n", 2323 DRM_ERROR("process %d using buffer owned by %p\n",
2327 DRM_CURRENTPID, buf->filp); 2324 DRM_CURRENTPID, buf->file_priv);
2328 return -EINVAL; 2325 return -EINVAL;
2329 } 2326 }
2330 if (buf->pending) { 2327 if (buf->pending) {
@@ -2347,7 +2344,7 @@ static int radeon_cp_indices(DRM_IOCTL_ARGS)
2347 buf->used = elts.end; 2344 buf->used = elts.end;
2348 2345
2349 if (sarea_priv->dirty & ~RADEON_UPLOAD_CLIPRECTS) { 2346 if (sarea_priv->dirty & ~RADEON_UPLOAD_CLIPRECTS) {
2350 if (radeon_emit_state(dev_priv, filp_priv, 2347 if (radeon_emit_state(dev_priv, file_priv,
2351 &sarea_priv->context_state, 2348 &sarea_priv->context_state,
2352 sarea_priv->tex_state, 2349 sarea_priv->tex_state,
2353 sarea_priv->dirty)) { 2350 sarea_priv->dirty)) {
@@ -2387,7 +2384,7 @@ static int radeon_cp_texture(DRM_IOCTL_ARGS)
2387 drm_radeon_tex_image_t image; 2384 drm_radeon_tex_image_t image;
2388 int ret; 2385 int ret;
2389 2386
2390 LOCK_TEST_WITH_RETURN(dev, filp); 2387 LOCK_TEST_WITH_RETURN(dev, file_priv);
2391 2388
2392 DRM_COPY_FROM_USER_IOCTL(tex, (drm_radeon_texture_t __user *) data, 2389 DRM_COPY_FROM_USER_IOCTL(tex, (drm_radeon_texture_t __user *) data,
2393 sizeof(tex)); 2390 sizeof(tex));
@@ -2405,7 +2402,7 @@ static int radeon_cp_texture(DRM_IOCTL_ARGS)
2405 RING_SPACE_TEST_WITH_RETURN(dev_priv); 2402 RING_SPACE_TEST_WITH_RETURN(dev_priv);
2406 VB_AGE_TEST_WITH_RETURN(dev_priv); 2403 VB_AGE_TEST_WITH_RETURN(dev_priv);
2407 2404
2408 ret = radeon_cp_dispatch_texture(filp, dev, &tex, &image); 2405 ret = radeon_cp_dispatch_texture(dev, file_priv, &tex, &image);
2409 2406
2410 COMMIT_RING(); 2407 COMMIT_RING();
2411 return ret; 2408 return ret;
@@ -2418,7 +2415,7 @@ static int radeon_cp_stipple(DRM_IOCTL_ARGS)
2418 drm_radeon_stipple_t stipple; 2415 drm_radeon_stipple_t stipple;
2419 u32 mask[32]; 2416 u32 mask[32];
2420 2417
2421 LOCK_TEST_WITH_RETURN(dev, filp); 2418 LOCK_TEST_WITH_RETURN(dev, file_priv);
2422 2419
2423 DRM_COPY_FROM_USER_IOCTL(stipple, (drm_radeon_stipple_t __user *) data, 2420 DRM_COPY_FROM_USER_IOCTL(stipple, (drm_radeon_stipple_t __user *) data,
2424 sizeof(stipple)); 2421 sizeof(stipple));
@@ -2443,7 +2440,7 @@ static int radeon_cp_indirect(DRM_IOCTL_ARGS)
2443 drm_radeon_indirect_t indirect; 2440 drm_radeon_indirect_t indirect;
2444 RING_LOCALS; 2441 RING_LOCALS;
2445 2442
2446 LOCK_TEST_WITH_RETURN(dev, filp); 2443 LOCK_TEST_WITH_RETURN(dev, file_priv);
2447 2444
2448 DRM_COPY_FROM_USER_IOCTL(indirect, 2445 DRM_COPY_FROM_USER_IOCTL(indirect,
2449 (drm_radeon_indirect_t __user *) data, 2446 (drm_radeon_indirect_t __user *) data,
@@ -2460,9 +2457,9 @@ static int radeon_cp_indirect(DRM_IOCTL_ARGS)
2460 2457
2461 buf = dma->buflist[indirect.idx]; 2458 buf = dma->buflist[indirect.idx];
2462 2459
2463 if (buf->filp != filp) { 2460 if (buf->file_priv != file_priv) {
2464 DRM_ERROR("process %d using buffer owned by %p\n", 2461 DRM_ERROR("process %d using buffer owned by %p\n",
2465 DRM_CURRENTPID, buf->filp); 2462 DRM_CURRENTPID, buf->file_priv);
2466 return -EINVAL; 2463 return -EINVAL;
2467 } 2464 }
2468 if (buf->pending) { 2465 if (buf->pending) {
@@ -2507,7 +2504,6 @@ static int radeon_cp_vertex2(DRM_IOCTL_ARGS)
2507{ 2504{
2508 DRM_DEVICE; 2505 DRM_DEVICE;
2509 drm_radeon_private_t *dev_priv = dev->dev_private; 2506 drm_radeon_private_t *dev_priv = dev->dev_private;
2510 struct drm_file *filp_priv;
2511 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; 2507 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
2512 struct drm_device_dma *dma = dev->dma; 2508 struct drm_device_dma *dma = dev->dma;
2513 struct drm_buf *buf; 2509 struct drm_buf *buf;
@@ -2515,9 +2511,7 @@ static int radeon_cp_vertex2(DRM_IOCTL_ARGS)
2515 int i; 2511 int i;
2516 unsigned char laststate; 2512 unsigned char laststate;
2517 2513
2518 LOCK_TEST_WITH_RETURN(dev, filp); 2514 LOCK_TEST_WITH_RETURN(dev, file_priv);
2519
2520 DRM_GET_PRIV_WITH_RETURN(filp_priv, filp);
2521 2515
2522 DRM_COPY_FROM_USER_IOCTL(vertex, (drm_radeon_vertex2_t __user *) data, 2516 DRM_COPY_FROM_USER_IOCTL(vertex, (drm_radeon_vertex2_t __user *) data,
2523 sizeof(vertex)); 2517 sizeof(vertex));
@@ -2536,9 +2530,9 @@ static int radeon_cp_vertex2(DRM_IOCTL_ARGS)
2536 2530
2537 buf = dma->buflist[vertex.idx]; 2531 buf = dma->buflist[vertex.idx];
2538 2532
2539 if (buf->filp != filp) { 2533 if (buf->file_priv != file_priv) {
2540 DRM_ERROR("process %d using buffer owned by %p\n", 2534 DRM_ERROR("process %d using buffer owned by %p\n",
2541 DRM_CURRENTPID, buf->filp); 2535 DRM_CURRENTPID, buf->file_priv);
2542 return -EINVAL; 2536 return -EINVAL;
2543 } 2537 }
2544 2538
@@ -2565,7 +2559,7 @@ static int radeon_cp_vertex2(DRM_IOCTL_ARGS)
2565 sizeof(state))) 2559 sizeof(state)))
2566 return -EFAULT; 2560 return -EFAULT;
2567 2561
2568 if (radeon_emit_state2(dev_priv, filp_priv, &state)) { 2562 if (radeon_emit_state2(dev_priv, file_priv, &state)) {
2569 DRM_ERROR("radeon_emit_state2 failed\n"); 2563 DRM_ERROR("radeon_emit_state2 failed\n");
2570 return -EINVAL; 2564 return -EINVAL;
2571 } 2565 }
@@ -2603,7 +2597,7 @@ static int radeon_cp_vertex2(DRM_IOCTL_ARGS)
2603} 2597}
2604 2598
2605static int radeon_emit_packets(drm_radeon_private_t * dev_priv, 2599static int radeon_emit_packets(drm_radeon_private_t * dev_priv,
2606 struct drm_file * filp_priv, 2600 struct drm_file *file_priv,
2607 drm_radeon_cmd_header_t header, 2601 drm_radeon_cmd_header_t header,
2608 drm_radeon_kcmd_buffer_t *cmdbuf) 2602 drm_radeon_kcmd_buffer_t *cmdbuf)
2609{ 2603{
@@ -2623,7 +2617,7 @@ static int radeon_emit_packets(drm_radeon_private_t * dev_priv,
2623 return -EINVAL; 2617 return -EINVAL;
2624 } 2618 }
2625 2619
2626 if (radeon_check_and_fixup_packets(dev_priv, filp_priv, id, data)) { 2620 if (radeon_check_and_fixup_packets(dev_priv, file_priv, id, data)) {
2627 DRM_ERROR("Packet verification failed\n"); 2621 DRM_ERROR("Packet verification failed\n");
2628 return -EINVAL; 2622 return -EINVAL;
2629 } 2623 }
@@ -2729,7 +2723,7 @@ static __inline__ int radeon_emit_veclinear(drm_radeon_private_t *dev_priv,
2729} 2723}
2730 2724
2731static int radeon_emit_packet3(struct drm_device * dev, 2725static int radeon_emit_packet3(struct drm_device * dev,
2732 struct drm_file * filp_priv, 2726 struct drm_file *file_priv,
2733 drm_radeon_kcmd_buffer_t *cmdbuf) 2727 drm_radeon_kcmd_buffer_t *cmdbuf)
2734{ 2728{
2735 drm_radeon_private_t *dev_priv = dev->dev_private; 2729 drm_radeon_private_t *dev_priv = dev->dev_private;
@@ -2739,7 +2733,7 @@ static int radeon_emit_packet3(struct drm_device * dev,
2739 2733
2740 DRM_DEBUG("\n"); 2734 DRM_DEBUG("\n");
2741 2735
2742 if ((ret = radeon_check_and_fixup_packet3(dev_priv, filp_priv, 2736 if ((ret = radeon_check_and_fixup_packet3(dev_priv, file_priv,
2743 cmdbuf, &cmdsz))) { 2737 cmdbuf, &cmdsz))) {
2744 DRM_ERROR("Packet verification failed\n"); 2738 DRM_ERROR("Packet verification failed\n");
2745 return ret; 2739 return ret;
@@ -2755,7 +2749,7 @@ static int radeon_emit_packet3(struct drm_device * dev,
2755} 2749}
2756 2750
2757static int radeon_emit_packet3_cliprect(struct drm_device *dev, 2751static int radeon_emit_packet3_cliprect(struct drm_device *dev,
2758 struct drm_file *filp_priv, 2752 struct drm_file *file_priv,
2759 drm_radeon_kcmd_buffer_t *cmdbuf, 2753 drm_radeon_kcmd_buffer_t *cmdbuf,
2760 int orig_nbox) 2754 int orig_nbox)
2761{ 2755{
@@ -2769,7 +2763,7 @@ static int radeon_emit_packet3_cliprect(struct drm_device *dev,
2769 2763
2770 DRM_DEBUG("\n"); 2764 DRM_DEBUG("\n");
2771 2765
2772 if ((ret = radeon_check_and_fixup_packet3(dev_priv, filp_priv, 2766 if ((ret = radeon_check_and_fixup_packet3(dev_priv, file_priv,
2773 cmdbuf, &cmdsz))) { 2767 cmdbuf, &cmdsz))) {
2774 DRM_ERROR("Packet verification failed\n"); 2768 DRM_ERROR("Packet verification failed\n");
2775 return ret; 2769 return ret;
@@ -2849,7 +2843,6 @@ static int radeon_cp_cmdbuf(DRM_IOCTL_ARGS)
2849{ 2843{
2850 DRM_DEVICE; 2844 DRM_DEVICE;
2851 drm_radeon_private_t *dev_priv = dev->dev_private; 2845 drm_radeon_private_t *dev_priv = dev->dev_private;
2852 struct drm_file *filp_priv;
2853 struct drm_device_dma *dma = dev->dma; 2846 struct drm_device_dma *dma = dev->dma;
2854 struct drm_buf *buf = NULL; 2847 struct drm_buf *buf = NULL;
2855 int idx; 2848 int idx;
@@ -2858,9 +2851,7 @@ static int radeon_cp_cmdbuf(DRM_IOCTL_ARGS)
2858 int orig_nbox, orig_bufsz; 2851 int orig_nbox, orig_bufsz;
2859 char *kbuf = NULL; 2852 char *kbuf = NULL;
2860 2853
2861 LOCK_TEST_WITH_RETURN(dev, filp); 2854 LOCK_TEST_WITH_RETURN(dev, file_priv);
2862
2863 DRM_GET_PRIV_WITH_RETURN(filp_priv, filp);
2864 2855
2865 DRM_COPY_FROM_USER_IOCTL(cmdbuf, 2856 DRM_COPY_FROM_USER_IOCTL(cmdbuf,
2866 (drm_radeon_cmd_buffer_t __user *) data, 2857 (drm_radeon_cmd_buffer_t __user *) data,
@@ -2894,7 +2885,7 @@ static int radeon_cp_cmdbuf(DRM_IOCTL_ARGS)
2894 2885
2895 if (dev_priv->microcode_version == UCODE_R300) { 2886 if (dev_priv->microcode_version == UCODE_R300) {
2896 int temp; 2887 int temp;
2897 temp = r300_do_cp_cmdbuf(dev, filp, filp_priv, &cmdbuf); 2888 temp = r300_do_cp_cmdbuf(dev, file_priv, &cmdbuf);
2898 2889
2899 if (orig_bufsz != 0) 2890 if (orig_bufsz != 0)
2900 drm_free(kbuf, orig_bufsz, DRM_MEM_DRIVER); 2891 drm_free(kbuf, orig_bufsz, DRM_MEM_DRIVER);
@@ -2913,7 +2904,7 @@ static int radeon_cp_cmdbuf(DRM_IOCTL_ARGS)
2913 case RADEON_CMD_PACKET: 2904 case RADEON_CMD_PACKET:
2914 DRM_DEBUG("RADEON_CMD_PACKET\n"); 2905 DRM_DEBUG("RADEON_CMD_PACKET\n");
2915 if (radeon_emit_packets 2906 if (radeon_emit_packets
2916 (dev_priv, filp_priv, header, &cmdbuf)) { 2907 (dev_priv, file_priv, header, &cmdbuf)) {
2917 DRM_ERROR("radeon_emit_packets failed\n"); 2908 DRM_ERROR("radeon_emit_packets failed\n");
2918 goto err; 2909 goto err;
2919 } 2910 }
@@ -2945,9 +2936,10 @@ static int radeon_cp_cmdbuf(DRM_IOCTL_ARGS)
2945 } 2936 }
2946 2937
2947 buf = dma->buflist[idx]; 2938 buf = dma->buflist[idx];
2948 if (buf->filp != filp || buf->pending) { 2939 if (buf->file_priv != file_priv || buf->pending) {
2949 DRM_ERROR("bad buffer %p %p %d\n", 2940 DRM_ERROR("bad buffer %p %p %d\n",
2950 buf->filp, filp, buf->pending); 2941 buf->file_priv, file_priv,
2942 buf->pending);
2951 goto err; 2943 goto err;
2952 } 2944 }
2953 2945
@@ -2956,7 +2948,7 @@ static int radeon_cp_cmdbuf(DRM_IOCTL_ARGS)
2956 2948
2957 case RADEON_CMD_PACKET3: 2949 case RADEON_CMD_PACKET3:
2958 DRM_DEBUG("RADEON_CMD_PACKET3\n"); 2950 DRM_DEBUG("RADEON_CMD_PACKET3\n");
2959 if (radeon_emit_packet3(dev, filp_priv, &cmdbuf)) { 2951 if (radeon_emit_packet3(dev, file_priv, &cmdbuf)) {
2960 DRM_ERROR("radeon_emit_packet3 failed\n"); 2952 DRM_ERROR("radeon_emit_packet3 failed\n");
2961 goto err; 2953 goto err;
2962 } 2954 }
@@ -2965,7 +2957,7 @@ static int radeon_cp_cmdbuf(DRM_IOCTL_ARGS)
2965 case RADEON_CMD_PACKET3_CLIP: 2957 case RADEON_CMD_PACKET3_CLIP:
2966 DRM_DEBUG("RADEON_CMD_PACKET3_CLIP\n"); 2958 DRM_DEBUG("RADEON_CMD_PACKET3_CLIP\n");
2967 if (radeon_emit_packet3_cliprect 2959 if (radeon_emit_packet3_cliprect
2968 (dev, filp_priv, &cmdbuf, orig_nbox)) { 2960 (dev, file_priv, &cmdbuf, orig_nbox)) {
2969 DRM_ERROR("radeon_emit_packet3_clip failed\n"); 2961 DRM_ERROR("radeon_emit_packet3_clip failed\n");
2970 goto err; 2962 goto err;
2971 } 2963 }
@@ -3105,18 +3097,15 @@ static int radeon_cp_setparam(DRM_IOCTL_ARGS)
3105{ 3097{
3106 DRM_DEVICE; 3098 DRM_DEVICE;
3107 drm_radeon_private_t *dev_priv = dev->dev_private; 3099 drm_radeon_private_t *dev_priv = dev->dev_private;
3108 struct drm_file *filp_priv;
3109 drm_radeon_setparam_t sp; 3100 drm_radeon_setparam_t sp;
3110 struct drm_radeon_driver_file_fields *radeon_priv; 3101 struct drm_radeon_driver_file_fields *radeon_priv;
3111 3102
3112 DRM_GET_PRIV_WITH_RETURN(filp_priv, filp);
3113
3114 DRM_COPY_FROM_USER_IOCTL(sp, (drm_radeon_setparam_t __user *) data, 3103 DRM_COPY_FROM_USER_IOCTL(sp, (drm_radeon_setparam_t __user *) data,
3115 sizeof(sp)); 3104 sizeof(sp));
3116 3105
3117 switch (sp.param) { 3106 switch (sp.param) {
3118 case RADEON_SETPARAM_FB_LOCATION: 3107 case RADEON_SETPARAM_FB_LOCATION:
3119 radeon_priv = filp_priv->driver_priv; 3108 radeon_priv = file_priv->driver_priv;
3120 radeon_priv->radeon_fb_delta = dev_priv->fb_location - sp.value; 3109 radeon_priv->radeon_fb_delta = dev_priv->fb_location - sp.value;
3121 break; 3110 break;
3122 case RADEON_SETPARAM_SWITCH_TILING: 3111 case RADEON_SETPARAM_SWITCH_TILING:
@@ -3162,14 +3151,14 @@ static int radeon_cp_setparam(DRM_IOCTL_ARGS)
3162 * 3151 *
3163 * DRM infrastructure takes care of reclaiming dma buffers. 3152 * DRM infrastructure takes care of reclaiming dma buffers.
3164 */ 3153 */
3165void radeon_driver_preclose(struct drm_device *dev, DRMFILE filp) 3154void radeon_driver_preclose(struct drm_device *dev, struct drm_file *file_priv)
3166{ 3155{
3167 if (dev->dev_private) { 3156 if (dev->dev_private) {
3168 drm_radeon_private_t *dev_priv = dev->dev_private; 3157 drm_radeon_private_t *dev_priv = dev->dev_private;
3169 dev_priv->page_flipping = 0; 3158 dev_priv->page_flipping = 0;
3170 radeon_mem_release(filp, dev_priv->gart_heap); 3159 radeon_mem_release(file_priv, dev_priv->gart_heap);
3171 radeon_mem_release(filp, dev_priv->fb_heap); 3160 radeon_mem_release(file_priv, dev_priv->fb_heap);
3172 radeon_surfaces_release(filp, dev_priv); 3161 radeon_surfaces_release(file_priv, dev_priv);
3173 } 3162 }
3174} 3163}
3175 3164
@@ -3186,7 +3175,7 @@ void radeon_driver_lastclose(struct drm_device *dev)
3186 radeon_do_release(dev); 3175 radeon_do_release(dev);
3187} 3176}
3188 3177
3189int radeon_driver_open(struct drm_device *dev, struct drm_file *filp_priv) 3178int radeon_driver_open(struct drm_device *dev, struct drm_file *file_priv)
3190{ 3179{
3191 drm_radeon_private_t *dev_priv = dev->dev_private; 3180 drm_radeon_private_t *dev_priv = dev->dev_private;
3192 struct drm_radeon_driver_file_fields *radeon_priv; 3181 struct drm_radeon_driver_file_fields *radeon_priv;
@@ -3199,7 +3188,7 @@ int radeon_driver_open(struct drm_device *dev, struct drm_file *filp_priv)
3199 if (!radeon_priv) 3188 if (!radeon_priv)
3200 return -ENOMEM; 3189 return -ENOMEM;
3201 3190
3202 filp_priv->driver_priv = radeon_priv; 3191 file_priv->driver_priv = radeon_priv;
3203 3192
3204 if (dev_priv) 3193 if (dev_priv)
3205 radeon_priv->radeon_fb_delta = dev_priv->fb_location; 3194 radeon_priv->radeon_fb_delta = dev_priv->fb_location;
@@ -3208,10 +3197,10 @@ int radeon_driver_open(struct drm_device *dev, struct drm_file *filp_priv)
3208 return 0; 3197 return 0;
3209} 3198}
3210 3199
3211void radeon_driver_postclose(struct drm_device *dev, struct drm_file *filp_priv) 3200void radeon_driver_postclose(struct drm_device *dev, struct drm_file *file_priv)
3212{ 3201{
3213 struct drm_radeon_driver_file_fields *radeon_priv = 3202 struct drm_radeon_driver_file_fields *radeon_priv =
3214 filp_priv->driver_priv; 3203 file_priv->driver_priv;
3215 3204
3216 drm_free(radeon_priv, sizeof(*radeon_priv), DRM_MEM_FILES); 3205 drm_free(radeon_priv, sizeof(*radeon_priv), DRM_MEM_FILES);
3217} 3206}
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-05 21:52:20 -0500