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authorDave Airlie <airlied@starflyer.(none)>2005-09-25 00:28:13 -0400
committerDave Airlie <airlied@linux.ie>2005-09-25 00:28:13 -0400
commitb5e89ed53ed8d24f83ba1941c07382af00ed238e (patch)
tree747bae7a565f88a2e1d5974776eeb054a932c505 /drivers/char/drm/radeon_state.c
parent99a2657a29e2d623c3568cd86b27cac13fb63140 (diff)
drm: lindent the drm directory.
I've been threatening this for a while, so no point hanging around. This lindents the DRM code which was always really bad in tabbing department. I've also fixed some misnamed files in comments and removed some trailing whitespace. Signed-off-by: Dave Airlie <airlied@linux.ie>
Diffstat (limited to 'drivers/char/drm/radeon_state.c')
-rw-r--r--drivers/char/drm/radeon_state.c2493
1 files changed, 1270 insertions, 1223 deletions
diff --git a/drivers/char/drm/radeon_state.c b/drivers/char/drm/radeon_state.c
index 74c2fe8033c2..42e8ce4dbe99 100644
--- a/drivers/char/drm/radeon_state.c
+++ b/drivers/char/drm/radeon_state.c
@@ -37,51 +37,58 @@
37 * Helper functions for client state checking and fixup 37 * Helper functions for client state checking and fixup
38 */ 38 */
39 39
40static __inline__ int radeon_check_and_fixup_offset( drm_radeon_private_t *dev_priv, 40static __inline__ int radeon_check_and_fixup_offset(drm_radeon_private_t *
41 drm_file_t *filp_priv, 41 dev_priv,
42 u32 *offset ) { 42 drm_file_t * filp_priv,
43 u32 * offset)
44{
43 u32 off = *offset; 45 u32 off = *offset;
44 struct drm_radeon_driver_file_fields *radeon_priv; 46 struct drm_radeon_driver_file_fields *radeon_priv;
45 47
46 if ( off >= dev_priv->fb_location && 48 if (off >= dev_priv->fb_location &&
47 off < ( dev_priv->gart_vm_start + dev_priv->gart_size ) ) 49 off < (dev_priv->gart_vm_start + dev_priv->gart_size))
48 return 0; 50 return 0;
49 51
50 radeon_priv = filp_priv->driver_priv; 52 radeon_priv = filp_priv->driver_priv;
51 off += radeon_priv->radeon_fb_delta; 53 off += radeon_priv->radeon_fb_delta;
52 54
53 DRM_DEBUG( "offset fixed up to 0x%x\n", off ); 55 DRM_DEBUG("offset fixed up to 0x%x\n", off);
54 56
55 if ( off < dev_priv->fb_location || 57 if (off < dev_priv->fb_location ||
56 off >= ( dev_priv->gart_vm_start + dev_priv->gart_size ) ) 58 off >= (dev_priv->gart_vm_start + dev_priv->gart_size))
57 return DRM_ERR( EINVAL ); 59 return DRM_ERR(EINVAL);
58 60
59 *offset = off; 61 *offset = off;
60 62
61 return 0; 63 return 0;
62} 64}
63 65
64static __inline__ int radeon_check_and_fixup_packets( drm_radeon_private_t *dev_priv, 66static __inline__ int radeon_check_and_fixup_packets(drm_radeon_private_t *
65 drm_file_t *filp_priv, 67 dev_priv,
66 int id, 68 drm_file_t * filp_priv,
67 u32 __user *data ) { 69 int id, u32 __user * data)
68 switch ( id ) { 70{
71 switch (id) {
69 72
70 case RADEON_EMIT_PP_MISC: 73 case RADEON_EMIT_PP_MISC:
71 if ( radeon_check_and_fixup_offset( dev_priv, filp_priv, 74 if (radeon_check_and_fixup_offset(dev_priv, filp_priv,
72 &data[( RADEON_RB3D_DEPTHOFFSET 75 &data[(RADEON_RB3D_DEPTHOFFSET
73 - RADEON_PP_MISC ) / 4] ) ) { 76 -
74 DRM_ERROR( "Invalid depth buffer offset\n" ); 77 RADEON_PP_MISC) /
75 return DRM_ERR( EINVAL ); 78 4])) {
79 DRM_ERROR("Invalid depth buffer offset\n");
80 return DRM_ERR(EINVAL);
76 } 81 }
77 break; 82 break;
78 83
79 case RADEON_EMIT_PP_CNTL: 84 case RADEON_EMIT_PP_CNTL:
80 if ( radeon_check_and_fixup_offset( dev_priv, filp_priv, 85 if (radeon_check_and_fixup_offset(dev_priv, filp_priv,
81 &data[( RADEON_RB3D_COLOROFFSET 86 &data[(RADEON_RB3D_COLOROFFSET
82 - RADEON_PP_CNTL ) / 4] ) ) { 87 -
83 DRM_ERROR( "Invalid colour buffer offset\n" ); 88 RADEON_PP_CNTL) /
84 return DRM_ERR( EINVAL ); 89 4])) {
90 DRM_ERROR("Invalid colour buffer offset\n");
91 return DRM_ERR(EINVAL);
85 } 92 }
86 break; 93 break;
87 94
@@ -91,21 +98,23 @@ static __inline__ int radeon_check_and_fixup_packets( drm_radeon_private_t *dev_
91 case R200_EMIT_PP_TXOFFSET_3: 98 case R200_EMIT_PP_TXOFFSET_3:
92 case R200_EMIT_PP_TXOFFSET_4: 99 case R200_EMIT_PP_TXOFFSET_4:
93 case R200_EMIT_PP_TXOFFSET_5: 100 case R200_EMIT_PP_TXOFFSET_5:
94 if ( radeon_check_and_fixup_offset( dev_priv, filp_priv, 101 if (radeon_check_and_fixup_offset(dev_priv, filp_priv,
95 &data[0] ) ) { 102 &data[0])) {
96 DRM_ERROR( "Invalid R200 texture offset\n" ); 103 DRM_ERROR("Invalid R200 texture offset\n");
97 return DRM_ERR( EINVAL ); 104 return DRM_ERR(EINVAL);
98 } 105 }
99 break; 106 break;
100 107
101 case RADEON_EMIT_PP_TXFILTER_0: 108 case RADEON_EMIT_PP_TXFILTER_0:
102 case RADEON_EMIT_PP_TXFILTER_1: 109 case RADEON_EMIT_PP_TXFILTER_1:
103 case RADEON_EMIT_PP_TXFILTER_2: 110 case RADEON_EMIT_PP_TXFILTER_2:
104 if ( radeon_check_and_fixup_offset( dev_priv, filp_priv, 111 if (radeon_check_and_fixup_offset(dev_priv, filp_priv,
105 &data[( RADEON_PP_TXOFFSET_0 112 &data[(RADEON_PP_TXOFFSET_0
106 - RADEON_PP_TXFILTER_0 ) / 4] ) ) { 113 -
107 DRM_ERROR( "Invalid R100 texture offset\n" ); 114 RADEON_PP_TXFILTER_0) /
108 return DRM_ERR( EINVAL ); 115 4])) {
116 DRM_ERROR("Invalid R100 texture offset\n");
117 return DRM_ERR(EINVAL);
109 } 118 }
110 break; 119 break;
111 120
@@ -114,17 +123,18 @@ static __inline__ int radeon_check_and_fixup_packets( drm_radeon_private_t *dev_
114 case R200_EMIT_PP_CUBIC_OFFSETS_2: 123 case R200_EMIT_PP_CUBIC_OFFSETS_2:
115 case R200_EMIT_PP_CUBIC_OFFSETS_3: 124 case R200_EMIT_PP_CUBIC_OFFSETS_3:
116 case R200_EMIT_PP_CUBIC_OFFSETS_4: 125 case R200_EMIT_PP_CUBIC_OFFSETS_4:
117 case R200_EMIT_PP_CUBIC_OFFSETS_5: { 126 case R200_EMIT_PP_CUBIC_OFFSETS_5:{
118 int i; 127 int i;
119 for ( i = 0; i < 5; i++ ) { 128 for (i = 0; i < 5; i++) {
120 if ( radeon_check_and_fixup_offset( dev_priv, filp_priv, 129 if (radeon_check_and_fixup_offset
121 &data[i] ) ) { 130 (dev_priv, filp_priv, &data[i])) {
122 DRM_ERROR( "Invalid R200 cubic texture offset\n" ); 131 DRM_ERROR
123 return DRM_ERR( EINVAL ); 132 ("Invalid R200 cubic texture offset\n");
133 return DRM_ERR(EINVAL);
134 }
124 } 135 }
136 break;
125 } 137 }
126 break;
127 }
128 138
129 case RADEON_EMIT_PP_CUBIC_OFFSETS_T0: 139 case RADEON_EMIT_PP_CUBIC_OFFSETS_T0:
130 case RADEON_EMIT_PP_CUBIC_OFFSETS_T1: 140 case RADEON_EMIT_PP_CUBIC_OFFSETS_T1:
@@ -220,243 +230,247 @@ static __inline__ int radeon_check_and_fixup_packets( drm_radeon_private_t *dev_
220 break; 230 break;
221 231
222 default: 232 default:
223 DRM_ERROR( "Unknown state packet ID %d\n", id ); 233 DRM_ERROR("Unknown state packet ID %d\n", id);
224 return DRM_ERR( EINVAL ); 234 return DRM_ERR(EINVAL);
225 } 235 }
226 236
227 return 0; 237 return 0;
228} 238}
229 239
230static __inline__ int radeon_check_and_fixup_packet3( drm_radeon_private_t *dev_priv, 240static __inline__ int radeon_check_and_fixup_packet3(drm_radeon_private_t *
231 drm_file_t *filp_priv, 241 dev_priv,
232 drm_radeon_cmd_buffer_t *cmdbuf, 242 drm_file_t * filp_priv,
233 unsigned int *cmdsz ) { 243 drm_radeon_cmd_buffer_t *
244 cmdbuf,
245 unsigned int *cmdsz)
246{
234 u32 *cmd = (u32 *) cmdbuf->buf; 247 u32 *cmd = (u32 *) cmdbuf->buf;
235 248
236 *cmdsz = 2 + ( ( cmd[0] & RADEON_CP_PACKET_COUNT_MASK ) >> 16 ); 249 *cmdsz = 2 + ((cmd[0] & RADEON_CP_PACKET_COUNT_MASK) >> 16);
237 250
238 if ( ( cmd[0] & 0xc0000000 ) != RADEON_CP_PACKET3 ) { 251 if ((cmd[0] & 0xc0000000) != RADEON_CP_PACKET3) {
239 DRM_ERROR( "Not a type 3 packet\n" ); 252 DRM_ERROR("Not a type 3 packet\n");
240 return DRM_ERR( EINVAL ); 253 return DRM_ERR(EINVAL);
241 } 254 }
242 255
243 if ( 4 * *cmdsz > cmdbuf->bufsz ) { 256 if (4 * *cmdsz > cmdbuf->bufsz) {
244 DRM_ERROR( "Packet size larger than size of data provided\n" ); 257 DRM_ERROR("Packet size larger than size of data provided\n");
245 return DRM_ERR( EINVAL ); 258 return DRM_ERR(EINVAL);
246 } 259 }
247 260
248 /* Check client state and fix it up if necessary */ 261 /* Check client state and fix it up if necessary */
249 if ( cmd[0] & 0x8000 ) { /* MSB of opcode: next DWORD GUI_CNTL */ 262 if (cmd[0] & 0x8000) { /* MSB of opcode: next DWORD GUI_CNTL */
250 u32 offset; 263 u32 offset;
251 264
252 if ( cmd[1] & ( RADEON_GMC_SRC_PITCH_OFFSET_CNTL 265 if (cmd[1] & (RADEON_GMC_SRC_PITCH_OFFSET_CNTL
253 | RADEON_GMC_DST_PITCH_OFFSET_CNTL ) ) { 266 | RADEON_GMC_DST_PITCH_OFFSET_CNTL)) {
254 offset = cmd[2] << 10; 267 offset = cmd[2] << 10;
255 if ( radeon_check_and_fixup_offset( dev_priv, filp_priv, &offset ) ) { 268 if (radeon_check_and_fixup_offset
256 DRM_ERROR( "Invalid first packet offset\n" ); 269 (dev_priv, filp_priv, &offset)) {
257 return DRM_ERR( EINVAL ); 270 DRM_ERROR("Invalid first packet offset\n");
271 return DRM_ERR(EINVAL);
258 } 272 }
259 cmd[2] = ( cmd[2] & 0xffc00000 ) | offset >> 10; 273 cmd[2] = (cmd[2] & 0xffc00000) | offset >> 10;
260 } 274 }
261 275
262 if ( ( cmd[1] & RADEON_GMC_SRC_PITCH_OFFSET_CNTL ) && 276 if ((cmd[1] & RADEON_GMC_SRC_PITCH_OFFSET_CNTL) &&
263 ( cmd[1] & RADEON_GMC_DST_PITCH_OFFSET_CNTL ) ) { 277 (cmd[1] & RADEON_GMC_DST_PITCH_OFFSET_CNTL)) {
264 offset = cmd[3] << 10; 278 offset = cmd[3] << 10;
265 if ( radeon_check_and_fixup_offset( dev_priv, filp_priv, &offset ) ) { 279 if (radeon_check_and_fixup_offset
266 DRM_ERROR( "Invalid second packet offset\n" ); 280 (dev_priv, filp_priv, &offset)) {
267 return DRM_ERR( EINVAL ); 281 DRM_ERROR("Invalid second packet offset\n");
282 return DRM_ERR(EINVAL);
268 } 283 }
269 cmd[3] = ( cmd[3] & 0xffc00000 ) | offset >> 10; 284 cmd[3] = (cmd[3] & 0xffc00000) | offset >> 10;
270 } 285 }
271 } 286 }
272 287
273 return 0; 288 return 0;
274} 289}
275 290
276
277/* ================================================================ 291/* ================================================================
278 * CP hardware state programming functions 292 * CP hardware state programming functions
279 */ 293 */
280 294
281static __inline__ void radeon_emit_clip_rect( drm_radeon_private_t *dev_priv, 295static __inline__ void radeon_emit_clip_rect(drm_radeon_private_t * dev_priv,
282 drm_clip_rect_t *box ) 296 drm_clip_rect_t * box)
283{ 297{
284 RING_LOCALS; 298 RING_LOCALS;
285 299
286 DRM_DEBUG( " box: x1=%d y1=%d x2=%d y2=%d\n", 300 DRM_DEBUG(" box: x1=%d y1=%d x2=%d y2=%d\n",
287 box->x1, box->y1, box->x2, box->y2 ); 301 box->x1, box->y1, box->x2, box->y2);
288 302
289 BEGIN_RING( 4 ); 303 BEGIN_RING(4);
290 OUT_RING( CP_PACKET0( RADEON_RE_TOP_LEFT, 0 ) ); 304 OUT_RING(CP_PACKET0(RADEON_RE_TOP_LEFT, 0));
291 OUT_RING( (box->y1 << 16) | box->x1 ); 305 OUT_RING((box->y1 << 16) | box->x1);
292 OUT_RING( CP_PACKET0( RADEON_RE_WIDTH_HEIGHT, 0 ) ); 306 OUT_RING(CP_PACKET0(RADEON_RE_WIDTH_HEIGHT, 0));
293 OUT_RING( ((box->y2 - 1) << 16) | (box->x2 - 1) ); 307 OUT_RING(((box->y2 - 1) << 16) | (box->x2 - 1));
294 ADVANCE_RING(); 308 ADVANCE_RING();
295} 309}
296 310
297/* Emit 1.1 state 311/* Emit 1.1 state
298 */ 312 */
299static int radeon_emit_state( drm_radeon_private_t *dev_priv, 313static int radeon_emit_state(drm_radeon_private_t * dev_priv,
300 drm_file_t *filp_priv, 314 drm_file_t * filp_priv,
301 drm_radeon_context_regs_t *ctx, 315 drm_radeon_context_regs_t * ctx,
302 drm_radeon_texture_regs_t *tex, 316 drm_radeon_texture_regs_t * tex,
303 unsigned int dirty ) 317 unsigned int dirty)
304{ 318{
305 RING_LOCALS; 319 RING_LOCALS;
306 DRM_DEBUG( "dirty=0x%08x\n", dirty ); 320 DRM_DEBUG("dirty=0x%08x\n", dirty);
307 321
308 if ( dirty & RADEON_UPLOAD_CONTEXT ) { 322 if (dirty & RADEON_UPLOAD_CONTEXT) {
309 if ( radeon_check_and_fixup_offset( dev_priv, filp_priv, 323 if (radeon_check_and_fixup_offset(dev_priv, filp_priv,
310 &ctx->rb3d_depthoffset ) ) { 324 &ctx->rb3d_depthoffset)) {
311 DRM_ERROR( "Invalid depth buffer offset\n" ); 325 DRM_ERROR("Invalid depth buffer offset\n");
312 return DRM_ERR( EINVAL ); 326 return DRM_ERR(EINVAL);
313 } 327 }
314 328
315 if ( radeon_check_and_fixup_offset( dev_priv, filp_priv, 329 if (radeon_check_and_fixup_offset(dev_priv, filp_priv,
316 &ctx->rb3d_coloroffset ) ) { 330 &ctx->rb3d_coloroffset)) {
317 DRM_ERROR( "Invalid depth buffer offset\n" ); 331 DRM_ERROR("Invalid depth buffer offset\n");
318 return DRM_ERR( EINVAL ); 332 return DRM_ERR(EINVAL);
319 } 333 }
320 334
321 BEGIN_RING( 14 ); 335 BEGIN_RING(14);
322 OUT_RING( CP_PACKET0( RADEON_PP_MISC, 6 ) ); 336 OUT_RING(CP_PACKET0(RADEON_PP_MISC, 6));
323 OUT_RING( ctx->pp_misc ); 337 OUT_RING(ctx->pp_misc);
324 OUT_RING( ctx->pp_fog_color ); 338 OUT_RING(ctx->pp_fog_color);
325 OUT_RING( ctx->re_solid_color ); 339 OUT_RING(ctx->re_solid_color);
326 OUT_RING( ctx->rb3d_blendcntl ); 340 OUT_RING(ctx->rb3d_blendcntl);
327 OUT_RING( ctx->rb3d_depthoffset ); 341 OUT_RING(ctx->rb3d_depthoffset);
328 OUT_RING( ctx->rb3d_depthpitch ); 342 OUT_RING(ctx->rb3d_depthpitch);
329 OUT_RING( ctx->rb3d_zstencilcntl ); 343 OUT_RING(ctx->rb3d_zstencilcntl);
330 OUT_RING( CP_PACKET0( RADEON_PP_CNTL, 2 ) ); 344 OUT_RING(CP_PACKET0(RADEON_PP_CNTL, 2));
331 OUT_RING( ctx->pp_cntl ); 345 OUT_RING(ctx->pp_cntl);
332 OUT_RING( ctx->rb3d_cntl ); 346 OUT_RING(ctx->rb3d_cntl);
333 OUT_RING( ctx->rb3d_coloroffset ); 347 OUT_RING(ctx->rb3d_coloroffset);
334 OUT_RING( CP_PACKET0( RADEON_RB3D_COLORPITCH, 0 ) ); 348 OUT_RING(CP_PACKET0(RADEON_RB3D_COLORPITCH, 0));
335 OUT_RING( ctx->rb3d_colorpitch ); 349 OUT_RING(ctx->rb3d_colorpitch);
336 ADVANCE_RING(); 350 ADVANCE_RING();
337 } 351 }
338 352
339 if ( dirty & RADEON_UPLOAD_VERTFMT ) { 353 if (dirty & RADEON_UPLOAD_VERTFMT) {
340 BEGIN_RING( 2 ); 354 BEGIN_RING(2);
341 OUT_RING( CP_PACKET0( RADEON_SE_COORD_FMT, 0 ) ); 355 OUT_RING(CP_PACKET0(RADEON_SE_COORD_FMT, 0));
342 OUT_RING( ctx->se_coord_fmt ); 356 OUT_RING(ctx->se_coord_fmt);
343 ADVANCE_RING(); 357 ADVANCE_RING();
344 } 358 }
345 359
346 if ( dirty & RADEON_UPLOAD_LINE ) { 360 if (dirty & RADEON_UPLOAD_LINE) {
347 BEGIN_RING( 5 ); 361 BEGIN_RING(5);
348 OUT_RING( CP_PACKET0( RADEON_RE_LINE_PATTERN, 1 ) ); 362 OUT_RING(CP_PACKET0(RADEON_RE_LINE_PATTERN, 1));
349 OUT_RING( ctx->re_line_pattern ); 363 OUT_RING(ctx->re_line_pattern);
350 OUT_RING( ctx->re_line_state ); 364 OUT_RING(ctx->re_line_state);
351 OUT_RING( CP_PACKET0( RADEON_SE_LINE_WIDTH, 0 ) ); 365 OUT_RING(CP_PACKET0(RADEON_SE_LINE_WIDTH, 0));
352 OUT_RING( ctx->se_line_width ); 366 OUT_RING(ctx->se_line_width);
353 ADVANCE_RING(); 367 ADVANCE_RING();
354 } 368 }
355 369
356 if ( dirty & RADEON_UPLOAD_BUMPMAP ) { 370 if (dirty & RADEON_UPLOAD_BUMPMAP) {
357 BEGIN_RING( 5 ); 371 BEGIN_RING(5);
358 OUT_RING( CP_PACKET0( RADEON_PP_LUM_MATRIX, 0 ) ); 372 OUT_RING(CP_PACKET0(RADEON_PP_LUM_MATRIX, 0));
359 OUT_RING( ctx->pp_lum_matrix ); 373 OUT_RING(ctx->pp_lum_matrix);
360 OUT_RING( CP_PACKET0( RADEON_PP_ROT_MATRIX_0, 1 ) ); 374 OUT_RING(CP_PACKET0(RADEON_PP_ROT_MATRIX_0, 1));
361 OUT_RING( ctx->pp_rot_matrix_0 ); 375 OUT_RING(ctx->pp_rot_matrix_0);
362 OUT_RING( ctx->pp_rot_matrix_1 ); 376 OUT_RING(ctx->pp_rot_matrix_1);
363 ADVANCE_RING(); 377 ADVANCE_RING();
364 } 378 }
365 379
366 if ( dirty & RADEON_UPLOAD_MASKS ) { 380 if (dirty & RADEON_UPLOAD_MASKS) {
367 BEGIN_RING( 4 ); 381 BEGIN_RING(4);
368 OUT_RING( CP_PACKET0( RADEON_RB3D_STENCILREFMASK, 2 ) ); 382 OUT_RING(CP_PACKET0(RADEON_RB3D_STENCILREFMASK, 2));
369 OUT_RING( ctx->rb3d_stencilrefmask ); 383 OUT_RING(ctx->rb3d_stencilrefmask);
370 OUT_RING( ctx->rb3d_ropcntl ); 384 OUT_RING(ctx->rb3d_ropcntl);
371 OUT_RING( ctx->rb3d_planemask ); 385 OUT_RING(ctx->rb3d_planemask);
372 ADVANCE_RING(); 386 ADVANCE_RING();
373 } 387 }
374 388
375 if ( dirty & RADEON_UPLOAD_VIEWPORT ) { 389 if (dirty & RADEON_UPLOAD_VIEWPORT) {
376 BEGIN_RING( 7 ); 390 BEGIN_RING(7);
377 OUT_RING( CP_PACKET0( RADEON_SE_VPORT_XSCALE, 5 ) ); 391 OUT_RING(CP_PACKET0(RADEON_SE_VPORT_XSCALE, 5));
378 OUT_RING( ctx->se_vport_xscale ); 392 OUT_RING(ctx->se_vport_xscale);
379 OUT_RING( ctx->se_vport_xoffset ); 393 OUT_RING(ctx->se_vport_xoffset);
380 OUT_RING( ctx->se_vport_yscale ); 394 OUT_RING(ctx->se_vport_yscale);
381 OUT_RING( ctx->se_vport_yoffset ); 395 OUT_RING(ctx->se_vport_yoffset);
382 OUT_RING( ctx->se_vport_zscale ); 396 OUT_RING(ctx->se_vport_zscale);
383 OUT_RING( ctx->se_vport_zoffset ); 397 OUT_RING(ctx->se_vport_zoffset);
384 ADVANCE_RING(); 398 ADVANCE_RING();
385 } 399 }
386 400
387 if ( dirty & RADEON_UPLOAD_SETUP ) { 401 if (dirty & RADEON_UPLOAD_SETUP) {
388 BEGIN_RING( 4 ); 402 BEGIN_RING(4);
389 OUT_RING( CP_PACKET0( RADEON_SE_CNTL, 0 ) ); 403 OUT_RING(CP_PACKET0(RADEON_SE_CNTL, 0));
390 OUT_RING( ctx->se_cntl ); 404 OUT_RING(ctx->se_cntl);
391 OUT_RING( CP_PACKET0( RADEON_SE_CNTL_STATUS, 0 ) ); 405 OUT_RING(CP_PACKET0(RADEON_SE_CNTL_STATUS, 0));
392 OUT_RING( ctx->se_cntl_status ); 406 OUT_RING(ctx->se_cntl_status);
393 ADVANCE_RING(); 407 ADVANCE_RING();
394 } 408 }
395 409
396 if ( dirty & RADEON_UPLOAD_MISC ) { 410 if (dirty & RADEON_UPLOAD_MISC) {
397 BEGIN_RING( 2 ); 411 BEGIN_RING(2);
398 OUT_RING( CP_PACKET0( RADEON_RE_MISC, 0 ) ); 412 OUT_RING(CP_PACKET0(RADEON_RE_MISC, 0));
399 OUT_RING( ctx->re_misc ); 413 OUT_RING(ctx->re_misc);
400 ADVANCE_RING(); 414 ADVANCE_RING();
401 } 415 }
402 416
403 if ( dirty & RADEON_UPLOAD_TEX0 ) { 417 if (dirty & RADEON_UPLOAD_TEX0) {
404 if ( radeon_check_and_fixup_offset( dev_priv, filp_priv, 418 if (radeon_check_and_fixup_offset(dev_priv, filp_priv,
405 &tex[0].pp_txoffset ) ) { 419 &tex[0].pp_txoffset)) {
406 DRM_ERROR( "Invalid texture offset for unit 0\n" ); 420 DRM_ERROR("Invalid texture offset for unit 0\n");
407 return DRM_ERR( EINVAL ); 421 return DRM_ERR(EINVAL);
408 } 422 }
409 423
410 BEGIN_RING( 9 ); 424 BEGIN_RING(9);
411 OUT_RING( CP_PACKET0( RADEON_PP_TXFILTER_0, 5 ) ); 425 OUT_RING(CP_PACKET0(RADEON_PP_TXFILTER_0, 5));
412 OUT_RING( tex[0].pp_txfilter ); 426 OUT_RING(tex[0].pp_txfilter);
413 OUT_RING( tex[0].pp_txformat ); 427 OUT_RING(tex[0].pp_txformat);
414 OUT_RING( tex[0].pp_txoffset ); 428 OUT_RING(tex[0].pp_txoffset);
415 OUT_RING( tex[0].pp_txcblend ); 429 OUT_RING(tex[0].pp_txcblend);
416 OUT_RING( tex[0].pp_txablend ); 430 OUT_RING(tex[0].pp_txablend);
417 OUT_RING( tex[0].pp_tfactor ); 431 OUT_RING(tex[0].pp_tfactor);
418 OUT_RING( CP_PACKET0( RADEON_PP_BORDER_COLOR_0, 0 ) ); 432 OUT_RING(CP_PACKET0(RADEON_PP_BORDER_COLOR_0, 0));
419 OUT_RING( tex[0].pp_border_color ); 433 OUT_RING(tex[0].pp_border_color);
420 ADVANCE_RING(); 434 ADVANCE_RING();
421 } 435 }
422 436
423 if ( dirty & RADEON_UPLOAD_TEX1 ) { 437 if (dirty & RADEON_UPLOAD_TEX1) {
424 if ( radeon_check_and_fixup_offset( dev_priv, filp_priv, 438 if (radeon_check_and_fixup_offset(dev_priv, filp_priv,
425 &tex[1].pp_txoffset ) ) { 439 &tex[1].pp_txoffset)) {
426 DRM_ERROR( "Invalid texture offset for unit 1\n" ); 440 DRM_ERROR("Invalid texture offset for unit 1\n");
427 return DRM_ERR( EINVAL ); 441 return DRM_ERR(EINVAL);
428 } 442 }
429 443
430 BEGIN_RING( 9 ); 444 BEGIN_RING(9);
431 OUT_RING( CP_PACKET0( RADEON_PP_TXFILTER_1, 5 ) ); 445 OUT_RING(CP_PACKET0(RADEON_PP_TXFILTER_1, 5));
432 OUT_RING( tex[1].pp_txfilter ); 446 OUT_RING(tex[1].pp_txfilter);
433 OUT_RING( tex[1].pp_txformat ); 447 OUT_RING(tex[1].pp_txformat);
434 OUT_RING( tex[1].pp_txoffset ); 448 OUT_RING(tex[1].pp_txoffset);
435 OUT_RING( tex[1].pp_txcblend ); 449 OUT_RING(tex[1].pp_txcblend);
436 OUT_RING( tex[1].pp_txablend ); 450 OUT_RING(tex[1].pp_txablend);
437 OUT_RING( tex[1].pp_tfactor ); 451 OUT_RING(tex[1].pp_tfactor);
438 OUT_RING( CP_PACKET0( RADEON_PP_BORDER_COLOR_1, 0 ) ); 452 OUT_RING(CP_PACKET0(RADEON_PP_BORDER_COLOR_1, 0));
439 OUT_RING( tex[1].pp_border_color ); 453 OUT_RING(tex[1].pp_border_color);
440 ADVANCE_RING(); 454 ADVANCE_RING();
441 } 455 }
442 456
443 if ( dirty & RADEON_UPLOAD_TEX2 ) { 457 if (dirty & RADEON_UPLOAD_TEX2) {
444 if ( radeon_check_and_fixup_offset( dev_priv, filp_priv, 458 if (radeon_check_and_fixup_offset(dev_priv, filp_priv,
445 &tex[2].pp_txoffset ) ) { 459 &tex[2].pp_txoffset)) {
446 DRM_ERROR( "Invalid texture offset for unit 2\n" ); 460 DRM_ERROR("Invalid texture offset for unit 2\n");
447 return DRM_ERR( EINVAL ); 461 return DRM_ERR(EINVAL);
448 } 462 }
449 463
450 BEGIN_RING( 9 ); 464 BEGIN_RING(9);
451 OUT_RING( CP_PACKET0( RADEON_PP_TXFILTER_2, 5 ) ); 465 OUT_RING(CP_PACKET0(RADEON_PP_TXFILTER_2, 5));
452 OUT_RING( tex[2].pp_txfilter ); 466 OUT_RING(tex[2].pp_txfilter);
453 OUT_RING( tex[2].pp_txformat ); 467 OUT_RING(tex[2].pp_txformat);
454 OUT_RING( tex[2].pp_txoffset ); 468 OUT_RING(tex[2].pp_txoffset);
455 OUT_RING( tex[2].pp_txcblend ); 469 OUT_RING(tex[2].pp_txcblend);
456 OUT_RING( tex[2].pp_txablend ); 470 OUT_RING(tex[2].pp_txablend);
457 OUT_RING( tex[2].pp_tfactor ); 471 OUT_RING(tex[2].pp_tfactor);
458 OUT_RING( CP_PACKET0( RADEON_PP_BORDER_COLOR_2, 0 ) ); 472 OUT_RING(CP_PACKET0(RADEON_PP_BORDER_COLOR_2, 0));
459 OUT_RING( tex[2].pp_border_color ); 473 OUT_RING(tex[2].pp_border_color);
460 ADVANCE_RING(); 474 ADVANCE_RING();
461 } 475 }
462 476
@@ -465,138 +479,137 @@ static int radeon_emit_state( drm_radeon_private_t *dev_priv,
465 479
466/* Emit 1.2 state 480/* Emit 1.2 state
467 */ 481 */
468static int radeon_emit_state2( drm_radeon_private_t *dev_priv, 482static int radeon_emit_state2(drm_radeon_private_t * dev_priv,
469 drm_file_t *filp_priv, 483 drm_file_t * filp_priv,
470 drm_radeon_state_t *state ) 484 drm_radeon_state_t * state)
471{ 485{
472 RING_LOCALS; 486 RING_LOCALS;
473 487
474 if (state->dirty & RADEON_UPLOAD_ZBIAS) { 488 if (state->dirty & RADEON_UPLOAD_ZBIAS) {
475 BEGIN_RING( 3 ); 489 BEGIN_RING(3);
476 OUT_RING( CP_PACKET0( RADEON_SE_ZBIAS_FACTOR, 1 ) ); 490 OUT_RING(CP_PACKET0(RADEON_SE_ZBIAS_FACTOR, 1));
477 OUT_RING( state->context2.se_zbias_factor ); 491 OUT_RING(state->context2.se_zbias_factor);
478 OUT_RING( state->context2.se_zbias_constant ); 492 OUT_RING(state->context2.se_zbias_constant);
479 ADVANCE_RING(); 493 ADVANCE_RING();
480 } 494 }
481 495
482 return radeon_emit_state( dev_priv, filp_priv, &state->context, 496 return radeon_emit_state(dev_priv, filp_priv, &state->context,
483 state->tex, state->dirty ); 497 state->tex, state->dirty);
484} 498}
485 499
486/* New (1.3) state mechanism. 3 commands (packet, scalar, vector) in 500/* New (1.3) state mechanism. 3 commands (packet, scalar, vector) in
487 * 1.3 cmdbuffers allow all previous state to be updated as well as 501 * 1.3 cmdbuffers allow all previous state to be updated as well as
488 * the tcl scalar and vector areas. 502 * the tcl scalar and vector areas.
489 */ 503 */
490static struct { 504static struct {
491 int start; 505 int start;
492 int len; 506 int len;
493 const char *name; 507 const char *name;
494} packet[RADEON_MAX_STATE_PACKETS] = { 508} packet[RADEON_MAX_STATE_PACKETS] = {
495 { RADEON_PP_MISC,7,"RADEON_PP_MISC" }, 509 {RADEON_PP_MISC, 7, "RADEON_PP_MISC"},
496 { RADEON_PP_CNTL,3,"RADEON_PP_CNTL" }, 510 {RADEON_PP_CNTL, 3, "RADEON_PP_CNTL"},
497 { RADEON_RB3D_COLORPITCH,1,"RADEON_RB3D_COLORPITCH" }, 511 {RADEON_RB3D_COLORPITCH, 1, "RADEON_RB3D_COLORPITCH"},
498 { RADEON_RE_LINE_PATTERN,2,"RADEON_RE_LINE_PATTERN" }, 512 {RADEON_RE_LINE_PATTERN, 2, "RADEON_RE_LINE_PATTERN"},
499 { RADEON_SE_LINE_WIDTH,1,"RADEON_SE_LINE_WIDTH" }, 513 {RADEON_SE_LINE_WIDTH, 1, "RADEON_SE_LINE_WIDTH"},
500 { RADEON_PP_LUM_MATRIX,1,"RADEON_PP_LUM_MATRIX" }, 514 {RADEON_PP_LUM_MATRIX, 1, "RADEON_PP_LUM_MATRIX"},
501 { RADEON_PP_ROT_MATRIX_0,2,"RADEON_PP_ROT_MATRIX_0" }, 515 {RADEON_PP_ROT_MATRIX_0, 2, "RADEON_PP_ROT_MATRIX_0"},
502 { RADEON_RB3D_STENCILREFMASK,3,"RADEON_RB3D_STENCILREFMASK" }, 516 {RADEON_RB3D_STENCILREFMASK, 3, "RADEON_RB3D_STENCILREFMASK"},
503 { RADEON_SE_VPORT_XSCALE,6,"RADEON_SE_VPORT_XSCALE" }, 517 {RADEON_SE_VPORT_XSCALE, 6, "RADEON_SE_VPORT_XSCALE"},
504 { RADEON_SE_CNTL,2,"RADEON_SE_CNTL" }, 518 {RADEON_SE_CNTL, 2, "RADEON_SE_CNTL"},
505 { RADEON_SE_CNTL_STATUS,1,"RADEON_SE_CNTL_STATUS" }, 519 {RADEON_SE_CNTL_STATUS, 1, "RADEON_SE_CNTL_STATUS"},
506 { RADEON_RE_MISC,1,"RADEON_RE_MISC" }, 520 {RADEON_RE_MISC, 1, "RADEON_RE_MISC"},
507 { RADEON_PP_TXFILTER_0,6,"RADEON_PP_TXFILTER_0" }, 521 {RADEON_PP_TXFILTER_0, 6, "RADEON_PP_TXFILTER_0"},
508 { RADEON_PP_BORDER_COLOR_0,1,"RADEON_PP_BORDER_COLOR_0" }, 522 {RADEON_PP_BORDER_COLOR_0, 1, "RADEON_PP_BORDER_COLOR_0"},
509 { RADEON_PP_TXFILTER_1,6,"RADEON_PP_TXFILTER_1" }, 523 {RADEON_PP_TXFILTER_1, 6, "RADEON_PP_TXFILTER_1"},
510 { RADEON_PP_BORDER_COLOR_1,1,"RADEON_PP_BORDER_COLOR_1" }, 524 {RADEON_PP_BORDER_COLOR_1, 1, "RADEON_PP_BORDER_COLOR_1"},
511 { RADEON_PP_TXFILTER_2,6,"RADEON_PP_TXFILTER_2" }, 525 {RADEON_PP_TXFILTER_2, 6, "RADEON_PP_TXFILTER_2"},
512 { RADEON_PP_BORDER_COLOR_2,1,"RADEON_PP_BORDER_COLOR_2" }, 526 {RADEON_PP_BORDER_COLOR_2, 1, "RADEON_PP_BORDER_COLOR_2"},
513 { RADEON_SE_ZBIAS_FACTOR,2,"RADEON_SE_ZBIAS_FACTOR" }, 527 {RADEON_SE_ZBIAS_FACTOR, 2, "RADEON_SE_ZBIAS_FACTOR"},
514 { RADEON_SE_TCL_OUTPUT_VTX_FMT,11,"RADEON_SE_TCL_OUTPUT_VTX_FMT" }, 528 {RADEON_SE_TCL_OUTPUT_VTX_FMT, 11, "RADEON_SE_TCL_OUTPUT_VTX_FMT"},
515 { RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED,17,"RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED" }, 529 {RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED, 17,
516 { R200_PP_TXCBLEND_0, 4, "R200_PP_TXCBLEND_0" }, 530 "RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED"},
517 { R200_PP_TXCBLEND_1, 4, "R200_PP_TXCBLEND_1" }, 531 {R200_PP_TXCBLEND_0, 4, "R200_PP_TXCBLEND_0"},
518 { R200_PP_TXCBLEND_2, 4, "R200_PP_TXCBLEND_2" }, 532 {R200_PP_TXCBLEND_1, 4, "R200_PP_TXCBLEND_1"},
519 { R200_PP_TXCBLEND_3, 4, "R200_PP_TXCBLEND_3" }, 533 {R200_PP_TXCBLEND_2, 4, "R200_PP_TXCBLEND_2"},
520 { R200_PP_TXCBLEND_4, 4, "R200_PP_TXCBLEND_4" }, 534 {R200_PP_TXCBLEND_3, 4, "R200_PP_TXCBLEND_3"},
521 { R200_PP_TXCBLEND_5, 4, "R200_PP_TXCBLEND_5" }, 535 {R200_PP_TXCBLEND_4, 4, "R200_PP_TXCBLEND_4"},
522 { R200_PP_TXCBLEND_6, 4, "R200_PP_TXCBLEND_6" }, 536 {R200_PP_TXCBLEND_5, 4, "R200_PP_TXCBLEND_5"},
523 { R200_PP_TXCBLEND_7, 4, "R200_PP_TXCBLEND_7" }, 537 {R200_PP_TXCBLEND_6, 4, "R200_PP_TXCBLEND_6"},
524 { R200_SE_TCL_LIGHT_MODEL_CTL_0, 6, "R200_SE_TCL_LIGHT_MODEL_CTL_0" }, 538 {R200_PP_TXCBLEND_7, 4, "R200_PP_TXCBLEND_7"},
525 { R200_PP_TFACTOR_0, 6, "R200_PP_TFACTOR_0" }, 539 {R200_SE_TCL_LIGHT_MODEL_CTL_0, 6, "R200_SE_TCL_LIGHT_MODEL_CTL_0"},
526 { R200_SE_VTX_FMT_0, 4, "R200_SE_VTX_FMT_0" }, 540 {R200_PP_TFACTOR_0, 6, "R200_PP_TFACTOR_0"},
527 { R200_SE_VAP_CNTL, 1, "R200_SE_VAP_CNTL" }, 541 {R200_SE_VTX_FMT_0, 4, "R200_SE_VTX_FMT_0"},
528 { R200_SE_TCL_MATRIX_SEL_0, 5, "R200_SE_TCL_MATRIX_SEL_0" }, 542 {R200_SE_VAP_CNTL, 1, "R200_SE_VAP_CNTL"},
529 { R200_SE_TCL_TEX_PROC_CTL_2, 5, "R200_SE_TCL_TEX_PROC_CTL_2" }, 543 {R200_SE_TCL_MATRIX_SEL_0, 5, "R200_SE_TCL_MATRIX_SEL_0"},
530 { R200_SE_TCL_UCP_VERT_BLEND_CTL, 1, "R200_SE_TCL_UCP_VERT_BLEND_CTL" }, 544 {R200_SE_TCL_TEX_PROC_CTL_2, 5, "R200_SE_TCL_TEX_PROC_CTL_2"},
531 { R200_PP_TXFILTER_0, 6, "R200_PP_TXFILTER_0" }, 545 {R200_SE_TCL_UCP_VERT_BLEND_CTL, 1, "R200_SE_TCL_UCP_VERT_BLEND_CTL"},
532 { R200_PP_TXFILTER_1, 6, "R200_PP_TXFILTER_1" }, 546 {R200_PP_TXFILTER_0, 6, "R200_PP_TXFILTER_0"},
533 { R200_PP_TXFILTER_2, 6, "R200_PP_TXFILTER_2" }, 547 {R200_PP_TXFILTER_1, 6, "R200_PP_TXFILTER_1"},
534 { R200_PP_TXFILTER_3, 6, "R200_PP_TXFILTER_3" }, 548 {R200_PP_TXFILTER_2, 6, "R200_PP_TXFILTER_2"},
535 { R200_PP_TXFILTER_4, 6, "R200_PP_TXFILTER_4" }, 549 {R200_PP_TXFILTER_3, 6, "R200_PP_TXFILTER_3"},
536 { R200_PP_TXFILTER_5, 6, "R200_PP_TXFILTER_5" }, 550 {R200_PP_TXFILTER_4, 6, "R200_PP_TXFILTER_4"},
537 { R200_PP_TXOFFSET_0, 1, "R200_PP_TXOFFSET_0" }, 551 {R200_PP_TXFILTER_5, 6, "R200_PP_TXFILTER_5"},
538 { R200_PP_TXOFFSET_1, 1, "R200_PP_TXOFFSET_1" }, 552 {R200_PP_TXOFFSET_0, 1, "R200_PP_TXOFFSET_0"},
539 { R200_PP_TXOFFSET_2, 1, "R200_PP_TXOFFSET_2" }, 553 {R200_PP_TXOFFSET_1, 1, "R200_PP_TXOFFSET_1"},
540 { R200_PP_TXOFFSET_3, 1, "R200_PP_TXOFFSET_3" }, 554 {R200_PP_TXOFFSET_2, 1, "R200_PP_TXOFFSET_2"},
541 { R200_PP_TXOFFSET_4, 1, "R200_PP_TXOFFSET_4" }, 555 {R200_PP_TXOFFSET_3, 1, "R200_PP_TXOFFSET_3"},
542 { R200_PP_TXOFFSET_5, 1, "R200_PP_TXOFFSET_5" }, 556 {R200_PP_TXOFFSET_4, 1, "R200_PP_TXOFFSET_4"},
543 { R200_SE_VTE_CNTL, 1, "R200_SE_VTE_CNTL" }, 557 {R200_PP_TXOFFSET_5, 1, "R200_PP_TXOFFSET_5"},
544 { R200_SE_TCL_OUTPUT_VTX_COMP_SEL, 1, "R200_SE_TCL_OUTPUT_VTX_COMP_SEL" }, 558 {R200_SE_VTE_CNTL, 1, "R200_SE_VTE_CNTL"},
545 { R200_PP_TAM_DEBUG3, 1, "R200_PP_TAM_DEBUG3" }, 559 {R200_SE_TCL_OUTPUT_VTX_COMP_SEL, 1, "R200_SE_TCL_OUTPUT_VTX_COMP_SEL"},
546 { R200_PP_CNTL_X, 1, "R200_PP_CNTL_X" }, 560 {R200_PP_TAM_DEBUG3, 1, "R200_PP_TAM_DEBUG3"},
547 { R200_RB3D_DEPTHXY_OFFSET, 1, "R200_RB3D_DEPTHXY_OFFSET" }, 561 {R200_PP_CNTL_X, 1, "R200_PP_CNTL_X"},
548 { R200_RE_AUX_SCISSOR_CNTL, 1, "R200_RE_AUX_SCISSOR_CNTL" }, 562 {R200_RB3D_DEPTHXY_OFFSET, 1, "R200_RB3D_DEPTHXY_OFFSET"},
549 { R200_RE_SCISSOR_TL_0, 2, "R200_RE_SCISSOR_TL_0" }, 563 {R200_RE_AUX_SCISSOR_CNTL, 1, "R200_RE_AUX_SCISSOR_CNTL"},
550 { R200_RE_SCISSOR_TL_1, 2, "R200_RE_SCISSOR_TL_1" }, 564 {R200_RE_SCISSOR_TL_0, 2, "R200_RE_SCISSOR_TL_0"},
551 { R200_RE_SCISSOR_TL_2, 2, "R200_RE_SCISSOR_TL_2" }, 565 {R200_RE_SCISSOR_TL_1, 2, "R200_RE_SCISSOR_TL_1"},
552 { R200_SE_VAP_CNTL_STATUS, 1, "R200_SE_VAP_CNTL_STATUS" }, 566 {R200_RE_SCISSOR_TL_2, 2, "R200_RE_SCISSOR_TL_2"},
553 { R200_SE_VTX_STATE_CNTL, 1, "R200_SE_VTX_STATE_CNTL" }, 567 {R200_SE_VAP_CNTL_STATUS, 1, "R200_SE_VAP_CNTL_STATUS"},
554 { R200_RE_POINTSIZE, 1, "R200_RE_POINTSIZE" }, 568 {R200_SE_VTX_STATE_CNTL, 1, "R200_SE_VTX_STATE_CNTL"},
555 { R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0, 4, "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0" }, 569 {R200_RE_POINTSIZE, 1, "R200_RE_POINTSIZE"},
556 { R200_PP_CUBIC_FACES_0, 1, "R200_PP_CUBIC_FACES_0" }, /* 61 */ 570 {R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0, 4,
557 { R200_PP_CUBIC_OFFSET_F1_0, 5, "R200_PP_CUBIC_OFFSET_F1_0" }, /* 62 */ 571 "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0"},
558 { R200_PP_CUBIC_FACES_1, 1, "R200_PP_CUBIC_FACES_1" }, 572 {R200_PP_CUBIC_FACES_0, 1, "R200_PP_CUBIC_FACES_0"}, /* 61 */
559 { R200_PP_CUBIC_OFFSET_F1_1, 5, "R200_PP_CUBIC_OFFSET_F1_1" }, 573 {R200_PP_CUBIC_OFFSET_F1_0, 5, "R200_PP_CUBIC_OFFSET_F1_0"}, /* 62 */
560 { R200_PP_CUBIC_FACES_2, 1, "R200_PP_CUBIC_FACES_2" }, 574 {R200_PP_CUBIC_FACES_1, 1, "R200_PP_CUBIC_FACES_1"},
561 { R200_PP_CUBIC_OFFSET_F1_2, 5, "R200_PP_CUBIC_OFFSET_F1_2" }, 575 {R200_PP_CUBIC_OFFSET_F1_1, 5, "R200_PP_CUBIC_OFFSET_F1_1"},
562 { R200_PP_CUBIC_FACES_3, 1, "R200_PP_CUBIC_FACES_3" }, 576 {R200_PP_CUBIC_FACES_2, 1, "R200_PP_CUBIC_FACES_2"},
563 { R200_PP_CUBIC_OFFSET_F1_3, 5, "R200_PP_CUBIC_OFFSET_F1_3" }, 577 {R200_PP_CUBIC_OFFSET_F1_2, 5, "R200_PP_CUBIC_OFFSET_F1_2"},
564 { R200_PP_CUBIC_FACES_4, 1, "R200_PP_CUBIC_FACES_4" }, 578 {R200_PP_CUBIC_FACES_3, 1, "R200_PP_CUBIC_FACES_3"},
565 { R200_PP_CUBIC_OFFSET_F1_4, 5, "R200_PP_CUBIC_OFFSET_F1_4" }, 579 {R200_PP_CUBIC_OFFSET_F1_3, 5, "R200_PP_CUBIC_OFFSET_F1_3"},
566 { R200_PP_CUBIC_FACES_5, 1, "R200_PP_CUBIC_FACES_5" }, 580 {R200_PP_CUBIC_FACES_4, 1, "R200_PP_CUBIC_FACES_4"},
567 { R200_PP_CUBIC_OFFSET_F1_5, 5, "R200_PP_CUBIC_OFFSET_F1_5" }, 581 {R200_PP_CUBIC_OFFSET_F1_4, 5, "R200_PP_CUBIC_OFFSET_F1_4"},
568 { RADEON_PP_TEX_SIZE_0, 2, "RADEON_PP_TEX_SIZE_0" }, 582 {R200_PP_CUBIC_FACES_5, 1, "R200_PP_CUBIC_FACES_5"},
569 { RADEON_PP_TEX_SIZE_1, 2, "RADEON_PP_TEX_SIZE_1" }, 583 {R200_PP_CUBIC_OFFSET_F1_5, 5, "R200_PP_CUBIC_OFFSET_F1_5"},
570 { RADEON_PP_TEX_SIZE_2, 2, "RADEON_PP_TEX_SIZE_2" }, 584 {RADEON_PP_TEX_SIZE_0, 2, "RADEON_PP_TEX_SIZE_0"},
571 { R200_RB3D_BLENDCOLOR, 3, "R200_RB3D_BLENDCOLOR" }, 585 {RADEON_PP_TEX_SIZE_1, 2, "RADEON_PP_TEX_SIZE_1"},
572 { R200_SE_TCL_POINT_SPRITE_CNTL, 1, "R200_SE_TCL_POINT_SPRITE_CNTL" }, 586 {RADEON_PP_TEX_SIZE_2, 2, "RADEON_PP_TEX_SIZE_2"},
573 { RADEON_PP_CUBIC_FACES_0, 1, "RADEON_PP_CUBIC_FACES_0"}, 587 {R200_RB3D_BLENDCOLOR, 3, "R200_RB3D_BLENDCOLOR"},
574 { RADEON_PP_CUBIC_OFFSET_T0_0, 5, "RADEON_PP_CUBIC_OFFSET_T0_0"}, 588 {R200_SE_TCL_POINT_SPRITE_CNTL, 1, "R200_SE_TCL_POINT_SPRITE_CNTL"},
575 { RADEON_PP_CUBIC_FACES_1, 1, "RADEON_PP_CUBIC_FACES_1"}, 589 {RADEON_PP_CUBIC_FACES_0, 1, "RADEON_PP_CUBIC_FACES_0"},
576 { RADEON_PP_CUBIC_OFFSET_T1_0, 5, "RADEON_PP_CUBIC_OFFSET_T1_0"}, 590 {RADEON_PP_CUBIC_OFFSET_T0_0, 5, "RADEON_PP_CUBIC_OFFSET_T0_0"},
577 { RADEON_PP_CUBIC_FACES_2, 1, "RADEON_PP_CUBIC_FACES_2"}, 591 {RADEON_PP_CUBIC_FACES_1, 1, "RADEON_PP_CUBIC_FACES_1"},
578 { RADEON_PP_CUBIC_OFFSET_T2_0, 5, "RADEON_PP_CUBIC_OFFSET_T2_0"}, 592 {RADEON_PP_CUBIC_OFFSET_T1_0, 5, "RADEON_PP_CUBIC_OFFSET_T1_0"},
579 { R200_PP_TRI_PERF, 2, "R200_PP_TRI_PERF"}, 593 {RADEON_PP_CUBIC_FACES_2, 1, "RADEON_PP_CUBIC_FACES_2"},
580 { R200_PP_AFS_0, 32, "R200_PP_AFS_0"}, /* 85 */ 594 {RADEON_PP_CUBIC_OFFSET_T2_0, 5, "RADEON_PP_CUBIC_OFFSET_T2_0"},
581 { R200_PP_AFS_1, 32, "R200_PP_AFS_1"}, 595 {R200_PP_TRI_PERF, 2, "R200_PP_TRI_PERF"},
582 { R200_PP_TFACTOR_0, 8, "R200_ATF_TFACTOR"}, 596 {R200_PP_AFS_0, 32, "R200_PP_AFS_0"}, /* 85 */
583 { R200_PP_TXFILTER_0, 8, "R200_PP_TXCTLALL_0"}, 597 {R200_PP_AFS_1, 32, "R200_PP_AFS_1"},
584 { R200_PP_TXFILTER_1, 8, "R200_PP_TXCTLALL_1"}, 598 {R200_PP_TFACTOR_0, 8, "R200_ATF_TFACTOR"},
585 { R200_PP_TXFILTER_2, 8, "R200_PP_TXCTLALL_2"}, 599 {R200_PP_TXFILTER_0, 8, "R200_PP_TXCTLALL_0"},
586 { R200_PP_TXFILTER_3, 8, "R200_PP_TXCTLALL_3"}, 600 {R200_PP_TXFILTER_1, 8, "R200_PP_TXCTLALL_1"},
587 { R200_PP_TXFILTER_4, 8, "R200_PP_TXCTLALL_4"}, 601 {R200_PP_TXFILTER_2, 8, "R200_PP_TXCTLALL_2"},
588 { R200_PP_TXFILTER_5, 8, "R200_PP_TXCTLALL_5"}, 602 {R200_PP_TXFILTER_3, 8, "R200_PP_TXCTLALL_3"},
603 {R200_PP_TXFILTER_4, 8, "R200_PP_TXCTLALL_4"},
604 {R200_PP_TXFILTER_5, 8, "R200_PP_TXCTLALL_5"},
589}; 605};
590 606
591
592
593/* ================================================================ 607/* ================================================================
594 * Performance monitoring functions 608 * Performance monitoring functions
595 */ 609 */
596 610
597static void radeon_clear_box( drm_radeon_private_t *dev_priv, 611static void radeon_clear_box(drm_radeon_private_t * dev_priv,
598 int x, int y, int w, int h, 612 int x, int y, int w, int h, int r, int g, int b)
599 int r, int g, int b )
600{ 613{
601 u32 color; 614 u32 color;
602 RING_LOCALS; 615 RING_LOCALS;
@@ -604,49 +617,47 @@ static void radeon_clear_box( drm_radeon_private_t *dev_priv,
604 x += dev_priv->sarea_priv->boxes[0].x1; 617 x += dev_priv->sarea_priv->boxes[0].x1;
605 y += dev_priv->sarea_priv->boxes[0].y1; 618 y += dev_priv->sarea_priv->boxes[0].y1;
606 619
607 switch ( dev_priv->color_fmt ) { 620 switch (dev_priv->color_fmt) {
608 case RADEON_COLOR_FORMAT_RGB565: 621 case RADEON_COLOR_FORMAT_RGB565:
609 color = (((r & 0xf8) << 8) | 622 color = (((r & 0xf8) << 8) |
610 ((g & 0xfc) << 3) | 623 ((g & 0xfc) << 3) | ((b & 0xf8) >> 3));
611 ((b & 0xf8) >> 3));
612 break; 624 break;
613 case RADEON_COLOR_FORMAT_ARGB8888: 625 case RADEON_COLOR_FORMAT_ARGB8888:
614 default: 626 default:
615 color = (((0xff) << 24) | (r << 16) | (g << 8) | b); 627 color = (((0xff) << 24) | (r << 16) | (g << 8) | b);
616 break; 628 break;
617 } 629 }
618 630
619 BEGIN_RING( 4 ); 631 BEGIN_RING(4);
620 RADEON_WAIT_UNTIL_3D_IDLE(); 632 RADEON_WAIT_UNTIL_3D_IDLE();
621 OUT_RING( CP_PACKET0( RADEON_DP_WRITE_MASK, 0 ) ); 633 OUT_RING(CP_PACKET0(RADEON_DP_WRITE_MASK, 0));
622 OUT_RING( 0xffffffff ); 634 OUT_RING(0xffffffff);
623 ADVANCE_RING(); 635 ADVANCE_RING();
624 636
625 BEGIN_RING( 6 ); 637 BEGIN_RING(6);
626 638
627 OUT_RING( CP_PACKET3( RADEON_CNTL_PAINT_MULTI, 4 ) ); 639 OUT_RING(CP_PACKET3(RADEON_CNTL_PAINT_MULTI, 4));
628 OUT_RING( RADEON_GMC_DST_PITCH_OFFSET_CNTL | 640 OUT_RING(RADEON_GMC_DST_PITCH_OFFSET_CNTL |
629 RADEON_GMC_BRUSH_SOLID_COLOR | 641 RADEON_GMC_BRUSH_SOLID_COLOR |
630 (dev_priv->color_fmt << 8) | 642 (dev_priv->color_fmt << 8) |
631 RADEON_GMC_SRC_DATATYPE_COLOR | 643 RADEON_GMC_SRC_DATATYPE_COLOR |
632 RADEON_ROP3_P | 644 RADEON_ROP3_P | RADEON_GMC_CLR_CMP_CNTL_DIS);
633 RADEON_GMC_CLR_CMP_CNTL_DIS );
634 645
635 if ( dev_priv->page_flipping && dev_priv->current_page == 1 ) { 646 if (dev_priv->page_flipping && dev_priv->current_page == 1) {
636 OUT_RING( dev_priv->front_pitch_offset ); 647 OUT_RING(dev_priv->front_pitch_offset);
637 } else { 648 } else {
638 OUT_RING( dev_priv->back_pitch_offset ); 649 OUT_RING(dev_priv->back_pitch_offset);
639 } 650 }
640 651
641 OUT_RING( color ); 652 OUT_RING(color);
642 653
643 OUT_RING( (x << 16) | y ); 654 OUT_RING((x << 16) | y);
644 OUT_RING( (w << 16) | h ); 655 OUT_RING((w << 16) | h);
645 656
646 ADVANCE_RING(); 657 ADVANCE_RING();
647} 658}
648 659
649static void radeon_cp_performance_boxes( drm_radeon_private_t *dev_priv ) 660static void radeon_cp_performance_boxes(drm_radeon_private_t * dev_priv)
650{ 661{
651 /* Collapse various things into a wait flag -- trying to 662 /* Collapse various things into a wait flag -- trying to
652 * guess if userspase slept -- better just to have them tell us. 663 * guess if userspase slept -- better just to have them tell us.
@@ -662,50 +673,50 @@ static void radeon_cp_performance_boxes( drm_radeon_private_t *dev_priv )
662 673
663 /* Purple box for page flipping 674 /* Purple box for page flipping
664 */ 675 */
665 if ( dev_priv->stats.boxes & RADEON_BOX_FLIP ) 676 if (dev_priv->stats.boxes & RADEON_BOX_FLIP)
666 radeon_clear_box( dev_priv, 4, 4, 8, 8, 255, 0, 255 ); 677 radeon_clear_box(dev_priv, 4, 4, 8, 8, 255, 0, 255);
667 678
668 /* Red box if we have to wait for idle at any point 679 /* Red box if we have to wait for idle at any point
669 */ 680 */
670 if ( dev_priv->stats.boxes & RADEON_BOX_WAIT_IDLE ) 681 if (dev_priv->stats.boxes & RADEON_BOX_WAIT_IDLE)
671 radeon_clear_box( dev_priv, 16, 4, 8, 8, 255, 0, 0 ); 682 radeon_clear_box(dev_priv, 16, 4, 8, 8, 255, 0, 0);
672 683
673 /* Blue box: lost context? 684 /* Blue box: lost context?
674 */ 685 */
675 686
676 /* Yellow box for texture swaps 687 /* Yellow box for texture swaps
677 */ 688 */
678 if ( dev_priv->stats.boxes & RADEON_BOX_TEXTURE_LOAD ) 689 if (dev_priv->stats.boxes & RADEON_BOX_TEXTURE_LOAD)
679 radeon_clear_box( dev_priv, 40, 4, 8, 8, 255, 255, 0 ); 690 radeon_clear_box(dev_priv, 40, 4, 8, 8, 255, 255, 0);
680 691
681 /* Green box if hardware never idles (as far as we can tell) 692 /* Green box if hardware never idles (as far as we can tell)
682 */ 693 */
683 if ( !(dev_priv->stats.boxes & RADEON_BOX_DMA_IDLE) ) 694 if (!(dev_priv->stats.boxes & RADEON_BOX_DMA_IDLE))
684 radeon_clear_box( dev_priv, 64, 4, 8, 8, 0, 255, 0 ); 695 radeon_clear_box(dev_priv, 64, 4, 8, 8, 0, 255, 0);
685
686 696
687 /* Draw bars indicating number of buffers allocated 697 /* Draw bars indicating number of buffers allocated
688 * (not a great measure, easily confused) 698 * (not a great measure, easily confused)
689 */ 699 */
690 if (dev_priv->stats.requested_bufs) { 700 if (dev_priv->stats.requested_bufs) {
691 if (dev_priv->stats.requested_bufs > 100) 701 if (dev_priv->stats.requested_bufs > 100)
692 dev_priv->stats.requested_bufs = 100; 702 dev_priv->stats.requested_bufs = 100;
693 703
694 radeon_clear_box( dev_priv, 4, 16, 704 radeon_clear_box(dev_priv, 4, 16,
695 dev_priv->stats.requested_bufs, 4, 705 dev_priv->stats.requested_bufs, 4,
696 196, 128, 128 ); 706 196, 128, 128);
697 } 707 }
698 708
699 memset( &dev_priv->stats, 0, sizeof(dev_priv->stats) ); 709 memset(&dev_priv->stats, 0, sizeof(dev_priv->stats));
700 710
701} 711}
712
702/* ================================================================ 713/* ================================================================
703 * CP command dispatch functions 714 * CP command dispatch functions
704 */ 715 */
705 716
706static void radeon_cp_dispatch_clear( drm_device_t *dev, 717static void radeon_cp_dispatch_clear(drm_device_t * dev,
707 drm_radeon_clear_t *clear, 718 drm_radeon_clear_t * clear,
708 drm_radeon_clear_rect_t *depth_boxes ) 719 drm_radeon_clear_rect_t * depth_boxes)
709{ 720{
710 drm_radeon_private_t *dev_priv = dev->dev_private; 721 drm_radeon_private_t *dev_priv = dev->dev_private;
711 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; 722 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
@@ -713,32 +724,34 @@ static void radeon_cp_dispatch_clear( drm_device_t *dev,
713 int nbox = sarea_priv->nbox; 724 int nbox = sarea_priv->nbox;
714 drm_clip_rect_t *pbox = sarea_priv->boxes; 725 drm_clip_rect_t *pbox = sarea_priv->boxes;
715 unsigned int flags = clear->flags; 726 unsigned int flags = clear->flags;
716 u32 rb3d_cntl = 0, rb3d_stencilrefmask= 0; 727 u32 rb3d_cntl = 0, rb3d_stencilrefmask = 0;
717 int i; 728 int i;
718 RING_LOCALS; 729 RING_LOCALS;
719 DRM_DEBUG( "flags = 0x%x\n", flags ); 730 DRM_DEBUG("flags = 0x%x\n", flags);
720 731
721 dev_priv->stats.clears++; 732 dev_priv->stats.clears++;
722 733
723 if ( dev_priv->page_flipping && dev_priv->current_page == 1 ) { 734 if (dev_priv->page_flipping && dev_priv->current_page == 1) {
724 unsigned int tmp = flags; 735 unsigned int tmp = flags;
725 736
726 flags &= ~(RADEON_FRONT | RADEON_BACK); 737 flags &= ~(RADEON_FRONT | RADEON_BACK);
727 if ( tmp & RADEON_FRONT ) flags |= RADEON_BACK; 738 if (tmp & RADEON_FRONT)
728 if ( tmp & RADEON_BACK ) flags |= RADEON_FRONT; 739 flags |= RADEON_BACK;
740 if (tmp & RADEON_BACK)
741 flags |= RADEON_FRONT;
729 } 742 }
730 743
731 if ( flags & (RADEON_FRONT | RADEON_BACK) ) { 744 if (flags & (RADEON_FRONT | RADEON_BACK)) {
732 745
733 BEGIN_RING( 4 ); 746 BEGIN_RING(4);
734 747
735 /* Ensure the 3D stream is idle before doing a 748 /* Ensure the 3D stream is idle before doing a
736 * 2D fill to clear the front or back buffer. 749 * 2D fill to clear the front or back buffer.
737 */ 750 */
738 RADEON_WAIT_UNTIL_3D_IDLE(); 751 RADEON_WAIT_UNTIL_3D_IDLE();
739 752
740 OUT_RING( CP_PACKET0( RADEON_DP_WRITE_MASK, 0 ) ); 753 OUT_RING(CP_PACKET0(RADEON_DP_WRITE_MASK, 0));
741 OUT_RING( clear->color_mask ); 754 OUT_RING(clear->color_mask);
742 755
743 ADVANCE_RING(); 756 ADVANCE_RING();
744 757
@@ -746,121 +759,130 @@ static void radeon_cp_dispatch_clear( drm_device_t *dev,
746 */ 759 */
747 dev_priv->sarea_priv->ctx_owner = 0; 760 dev_priv->sarea_priv->ctx_owner = 0;
748 761
749 for ( i = 0 ; i < nbox ; i++ ) { 762 for (i = 0; i < nbox; i++) {
750 int x = pbox[i].x1; 763 int x = pbox[i].x1;
751 int y = pbox[i].y1; 764 int y = pbox[i].y1;
752 int w = pbox[i].x2 - x; 765 int w = pbox[i].x2 - x;
753 int h = pbox[i].y2 - y; 766 int h = pbox[i].y2 - y;
754 767
755 DRM_DEBUG( "dispatch clear %d,%d-%d,%d flags 0x%x\n", 768 DRM_DEBUG("dispatch clear %d,%d-%d,%d flags 0x%x\n",
756 x, y, w, h, flags ); 769 x, y, w, h, flags);
757 770
758 if ( flags & RADEON_FRONT ) { 771 if (flags & RADEON_FRONT) {
759 BEGIN_RING( 6 ); 772 BEGIN_RING(6);
760 773
761 OUT_RING( CP_PACKET3( RADEON_CNTL_PAINT_MULTI, 4 ) ); 774 OUT_RING(CP_PACKET3
762 OUT_RING( RADEON_GMC_DST_PITCH_OFFSET_CNTL | 775 (RADEON_CNTL_PAINT_MULTI, 4));
763 RADEON_GMC_BRUSH_SOLID_COLOR | 776 OUT_RING(RADEON_GMC_DST_PITCH_OFFSET_CNTL |
764 (dev_priv->color_fmt << 8) | 777 RADEON_GMC_BRUSH_SOLID_COLOR |
765 RADEON_GMC_SRC_DATATYPE_COLOR | 778 (dev_priv->
766 RADEON_ROP3_P | 779 color_fmt << 8) |
767 RADEON_GMC_CLR_CMP_CNTL_DIS ); 780 RADEON_GMC_SRC_DATATYPE_COLOR |
768 781 RADEON_ROP3_P |
769 OUT_RING( dev_priv->front_pitch_offset ); 782 RADEON_GMC_CLR_CMP_CNTL_DIS);
770 OUT_RING( clear->clear_color ); 783
771 784 OUT_RING(dev_priv->front_pitch_offset);
772 OUT_RING( (x << 16) | y ); 785 OUT_RING(clear->clear_color);
773 OUT_RING( (w << 16) | h ); 786
774 787 OUT_RING((x << 16) | y);
788 OUT_RING((w << 16) | h);
789
775 ADVANCE_RING(); 790 ADVANCE_RING();
776 } 791 }
777 792
778 if ( flags & RADEON_BACK ) { 793 if (flags & RADEON_BACK) {
779 BEGIN_RING( 6 ); 794 BEGIN_RING(6);
780 795
781 OUT_RING( CP_PACKET3( RADEON_CNTL_PAINT_MULTI, 4 ) ); 796 OUT_RING(CP_PACKET3
782 OUT_RING( RADEON_GMC_DST_PITCH_OFFSET_CNTL | 797 (RADEON_CNTL_PAINT_MULTI, 4));
783 RADEON_GMC_BRUSH_SOLID_COLOR | 798 OUT_RING(RADEON_GMC_DST_PITCH_OFFSET_CNTL |
784 (dev_priv->color_fmt << 8) | 799 RADEON_GMC_BRUSH_SOLID_COLOR |
785 RADEON_GMC_SRC_DATATYPE_COLOR | 800 (dev_priv->
786 RADEON_ROP3_P | 801 color_fmt << 8) |
787 RADEON_GMC_CLR_CMP_CNTL_DIS ); 802 RADEON_GMC_SRC_DATATYPE_COLOR |
788 803 RADEON_ROP3_P |
789 OUT_RING( dev_priv->back_pitch_offset ); 804 RADEON_GMC_CLR_CMP_CNTL_DIS);
790 OUT_RING( clear->clear_color ); 805
791 806 OUT_RING(dev_priv->back_pitch_offset);
792 OUT_RING( (x << 16) | y ); 807 OUT_RING(clear->clear_color);
793 OUT_RING( (w << 16) | h ); 808
809 OUT_RING((x << 16) | y);
810 OUT_RING((w << 16) | h);
794 811
795 ADVANCE_RING(); 812 ADVANCE_RING();
796 } 813 }
797 } 814 }
798 } 815 }
799 816
800 /* hyper z clear */ 817 /* hyper z clear */
801 /* no docs available, based on reverse engeneering by Stephane Marchesin */ 818 /* no docs available, based on reverse engeneering by Stephane Marchesin */
802 if ((flags & (RADEON_DEPTH | RADEON_STENCIL)) && (flags & RADEON_CLEAR_FASTZ)) { 819 if ((flags & (RADEON_DEPTH | RADEON_STENCIL))
820 && (flags & RADEON_CLEAR_FASTZ)) {
803 821
804 int i; 822 int i;
805 int depthpixperline = dev_priv->depth_fmt==RADEON_DEPTH_FORMAT_16BIT_INT_Z? 823 int depthpixperline =
806 (dev_priv->depth_pitch / 2): (dev_priv->depth_pitch / 4); 824 dev_priv->depth_fmt ==
807 825 RADEON_DEPTH_FORMAT_16BIT_INT_Z ? (dev_priv->depth_pitch /
826 2) : (dev_priv->
827 depth_pitch / 4);
828
808 u32 clearmask; 829 u32 clearmask;
809 830
810 u32 tempRB3D_DEPTHCLEARVALUE = clear->clear_depth | 831 u32 tempRB3D_DEPTHCLEARVALUE = clear->clear_depth |
811 ((clear->depth_mask & 0xff) << 24); 832 ((clear->depth_mask & 0xff) << 24);
812 833
813
814 /* Make sure we restore the 3D state next time. 834 /* Make sure we restore the 3D state next time.
815 * we haven't touched any "normal" state - still need this? 835 * we haven't touched any "normal" state - still need this?
816 */ 836 */
817 dev_priv->sarea_priv->ctx_owner = 0; 837 dev_priv->sarea_priv->ctx_owner = 0;
818 838
819 if ((dev_priv->flags & CHIP_HAS_HIERZ) && (flags & RADEON_USE_HIERZ)) { 839 if ((dev_priv->flags & CHIP_HAS_HIERZ)
820 /* FIXME : reverse engineer that for Rx00 cards */ 840 && (flags & RADEON_USE_HIERZ)) {
821 /* FIXME : the mask supposedly contains low-res z values. So can't set 841 /* FIXME : reverse engineer that for Rx00 cards */
822 just to the max (0xff? or actually 0x3fff?), need to take z clear 842 /* FIXME : the mask supposedly contains low-res z values. So can't set
823 value into account? */ 843 just to the max (0xff? or actually 0x3fff?), need to take z clear
824 /* pattern seems to work for r100, though get slight 844 value into account? */
825 rendering errors with glxgears. If hierz is not enabled for r100, 845 /* pattern seems to work for r100, though get slight
826 only 4 bits which indicate clear (15,16,31,32, all zero) matter, the 846 rendering errors with glxgears. If hierz is not enabled for r100,
827 other ones are ignored, and the same clear mask can be used. That's 847 only 4 bits which indicate clear (15,16,31,32, all zero) matter, the
828 very different behaviour than R200 which needs different clear mask 848 other ones are ignored, and the same clear mask can be used. That's
829 and different number of tiles to clear if hierz is enabled or not !?! 849 very different behaviour than R200 which needs different clear mask
830 */ 850 and different number of tiles to clear if hierz is enabled or not !?!
831 clearmask = (0xff<<22)|(0xff<<6)| 0x003f003f; 851 */
832 } 852 clearmask = (0xff << 22) | (0xff << 6) | 0x003f003f;
833 else { 853 } else {
834 /* clear mask : chooses the clearing pattern. 854 /* clear mask : chooses the clearing pattern.
835 rv250: could be used to clear only parts of macrotiles 855 rv250: could be used to clear only parts of macrotiles
836 (but that would get really complicated...)? 856 (but that would get really complicated...)?
837 bit 0 and 1 (either or both of them ?!?!) are used to 857 bit 0 and 1 (either or both of them ?!?!) are used to
838 not clear tile (or maybe one of the bits indicates if the tile is 858 not clear tile (or maybe one of the bits indicates if the tile is
839 compressed or not), bit 2 and 3 to not clear tile 1,...,. 859 compressed or not), bit 2 and 3 to not clear tile 1,...,.
840 Pattern is as follows: 860 Pattern is as follows:
841 | 0,1 | 4,5 | 8,9 |12,13|16,17|20,21|24,25|28,29| 861 | 0,1 | 4,5 | 8,9 |12,13|16,17|20,21|24,25|28,29|
842 bits ------------------------------------------------- 862 bits -------------------------------------------------
843 | 2,3 | 6,7 |10,11|14,15|18,19|22,23|26,27|30,31| 863 | 2,3 | 6,7 |10,11|14,15|18,19|22,23|26,27|30,31|
844 rv100: clearmask covers 2x8 4x1 tiles, but one clear still 864 rv100: clearmask covers 2x8 4x1 tiles, but one clear still
845 covers 256 pixels ?!? 865 covers 256 pixels ?!?
846 */ 866 */
847 clearmask = 0x0; 867 clearmask = 0x0;
848 } 868 }
849 869
850 BEGIN_RING( 8 ); 870 BEGIN_RING(8);
851 RADEON_WAIT_UNTIL_2D_IDLE(); 871 RADEON_WAIT_UNTIL_2D_IDLE();
852 OUT_RING_REG( RADEON_RB3D_DEPTHCLEARVALUE, 872 OUT_RING_REG(RADEON_RB3D_DEPTHCLEARVALUE,
853 tempRB3D_DEPTHCLEARVALUE); 873 tempRB3D_DEPTHCLEARVALUE);
854 /* what offset is this exactly ? */ 874 /* what offset is this exactly ? */
855 OUT_RING_REG( RADEON_RB3D_ZMASKOFFSET, 0 ); 875 OUT_RING_REG(RADEON_RB3D_ZMASKOFFSET, 0);
856 /* need ctlstat, otherwise get some strange black flickering */ 876 /* need ctlstat, otherwise get some strange black flickering */
857 OUT_RING_REG( RADEON_RB3D_ZCACHE_CTLSTAT, RADEON_RB3D_ZC_FLUSH_ALL ); 877 OUT_RING_REG(RADEON_RB3D_ZCACHE_CTLSTAT,
878 RADEON_RB3D_ZC_FLUSH_ALL);
858 ADVANCE_RING(); 879 ADVANCE_RING();
859 880
860 for (i = 0; i < nbox; i++) { 881 for (i = 0; i < nbox; i++) {
861 int tileoffset, nrtilesx, nrtilesy, j; 882 int tileoffset, nrtilesx, nrtilesy, j;
862 /* it looks like r200 needs rv-style clears, at least if hierz is not enabled? */ 883 /* it looks like r200 needs rv-style clears, at least if hierz is not enabled? */
863 if ((dev_priv->flags&CHIP_HAS_HIERZ) && !(dev_priv->microcode_version==UCODE_R200)) { 884 if ((dev_priv->flags & CHIP_HAS_HIERZ)
885 && !(dev_priv->microcode_version == UCODE_R200)) {
864 /* FIXME : figure this out for r200 (when hierz is enabled). Or 886 /* FIXME : figure this out for r200 (when hierz is enabled). Or
865 maybe r200 actually doesn't need to put the low-res z value into 887 maybe r200 actually doesn't need to put the low-res z value into
866 the tile cache like r100, but just needs to clear the hi-level z-buffer? 888 the tile cache like r100, but just needs to clear the hi-level z-buffer?
@@ -868,59 +890,74 @@ static void radeon_cp_dispatch_clear( drm_device_t *dev,
868 R100 seems to operate on 2x1 8x8 tiles, but... 890 R100 seems to operate on 2x1 8x8 tiles, but...
869 odd: offset/nrtiles need to be 64 pix (4 block) aligned? Potentially 891 odd: offset/nrtiles need to be 64 pix (4 block) aligned? Potentially
870 problematic with resolutions which are not 64 pix aligned? */ 892 problematic with resolutions which are not 64 pix aligned? */
871 tileoffset = ((pbox[i].y1 >> 3) * depthpixperline + pbox[i].x1) >> 6; 893 tileoffset =
872 nrtilesx = ((pbox[i].x2 & ~63) - (pbox[i].x1 & ~63)) >> 4; 894 ((pbox[i].y1 >> 3) * depthpixperline +
873 nrtilesy = (pbox[i].y2 >> 3) - (pbox[i].y1 >> 3); 895 pbox[i].x1) >> 6;
896 nrtilesx =
897 ((pbox[i].x2 & ~63) -
898 (pbox[i].x1 & ~63)) >> 4;
899 nrtilesy =
900 (pbox[i].y2 >> 3) - (pbox[i].y1 >> 3);
874 for (j = 0; j <= nrtilesy; j++) { 901 for (j = 0; j <= nrtilesy; j++) {
875 BEGIN_RING( 4 ); 902 BEGIN_RING(4);
876 OUT_RING( CP_PACKET3( RADEON_3D_CLEAR_ZMASK, 2 ) ); 903 OUT_RING(CP_PACKET3
904 (RADEON_3D_CLEAR_ZMASK, 2));
877 /* first tile */ 905 /* first tile */
878 OUT_RING( tileoffset * 8 ); 906 OUT_RING(tileoffset * 8);
879 /* the number of tiles to clear */ 907 /* the number of tiles to clear */
880 OUT_RING( nrtilesx + 4 ); 908 OUT_RING(nrtilesx + 4);
881 /* clear mask : chooses the clearing pattern. */ 909 /* clear mask : chooses the clearing pattern. */
882 OUT_RING( clearmask ); 910 OUT_RING(clearmask);
883 ADVANCE_RING(); 911 ADVANCE_RING();
884 tileoffset += depthpixperline >> 6; 912 tileoffset += depthpixperline >> 6;
885 } 913 }
886 } 914 } else if (dev_priv->microcode_version == UCODE_R200) {
887 else if (dev_priv->microcode_version==UCODE_R200) {
888 /* works for rv250. */ 915 /* works for rv250. */
889 /* find first macro tile (8x2 4x4 z-pixels on rv250) */ 916 /* find first macro tile (8x2 4x4 z-pixels on rv250) */
890 tileoffset = ((pbox[i].y1 >> 3) * depthpixperline + pbox[i].x1) >> 5; 917 tileoffset =
891 nrtilesx = (pbox[i].x2 >> 5) - (pbox[i].x1 >> 5); 918 ((pbox[i].y1 >> 3) * depthpixperline +
892 nrtilesy = (pbox[i].y2 >> 3) - (pbox[i].y1 >> 3); 919 pbox[i].x1) >> 5;
920 nrtilesx =
921 (pbox[i].x2 >> 5) - (pbox[i].x1 >> 5);
922 nrtilesy =
923 (pbox[i].y2 >> 3) - (pbox[i].y1 >> 3);
893 for (j = 0; j <= nrtilesy; j++) { 924 for (j = 0; j <= nrtilesy; j++) {
894 BEGIN_RING( 4 ); 925 BEGIN_RING(4);
895 OUT_RING( CP_PACKET3( RADEON_3D_CLEAR_ZMASK, 2 ) ); 926 OUT_RING(CP_PACKET3
927 (RADEON_3D_CLEAR_ZMASK, 2));
896 /* first tile */ 928 /* first tile */
897 /* judging by the first tile offset needed, could possibly 929 /* judging by the first tile offset needed, could possibly
898 directly address/clear 4x4 tiles instead of 8x2 * 4x4 930 directly address/clear 4x4 tiles instead of 8x2 * 4x4
899 macro tiles, though would still need clear mask for 931 macro tiles, though would still need clear mask for
900 right/bottom if truely 4x4 granularity is desired ? */ 932 right/bottom if truely 4x4 granularity is desired ? */
901 OUT_RING( tileoffset * 16 ); 933 OUT_RING(tileoffset * 16);
902 /* the number of tiles to clear */ 934 /* the number of tiles to clear */
903 OUT_RING( nrtilesx + 1 ); 935 OUT_RING(nrtilesx + 1);
904 /* clear mask : chooses the clearing pattern. */ 936 /* clear mask : chooses the clearing pattern. */
905 OUT_RING( clearmask ); 937 OUT_RING(clearmask);
906 ADVANCE_RING(); 938 ADVANCE_RING();
907 tileoffset += depthpixperline >> 5; 939 tileoffset += depthpixperline >> 5;
908 } 940 }
909 } 941 } else { /* rv 100 */
910 else { /* rv 100 */
911 /* rv100 might not need 64 pix alignment, who knows */ 942 /* rv100 might not need 64 pix alignment, who knows */
912 /* offsets are, hmm, weird */ 943 /* offsets are, hmm, weird */
913 tileoffset = ((pbox[i].y1 >> 4) * depthpixperline + pbox[i].x1) >> 6; 944 tileoffset =
914 nrtilesx = ((pbox[i].x2 & ~63) - (pbox[i].x1 & ~63)) >> 4; 945 ((pbox[i].y1 >> 4) * depthpixperline +
915 nrtilesy = (pbox[i].y2 >> 4) - (pbox[i].y1 >> 4); 946 pbox[i].x1) >> 6;
947 nrtilesx =
948 ((pbox[i].x2 & ~63) -
949 (pbox[i].x1 & ~63)) >> 4;
950 nrtilesy =
951 (pbox[i].y2 >> 4) - (pbox[i].y1 >> 4);
916 for (j = 0; j <= nrtilesy; j++) { 952 for (j = 0; j <= nrtilesy; j++) {
917 BEGIN_RING( 4 ); 953 BEGIN_RING(4);
918 OUT_RING( CP_PACKET3( RADEON_3D_CLEAR_ZMASK, 2 ) ); 954 OUT_RING(CP_PACKET3
919 OUT_RING( tileoffset * 128 ); 955 (RADEON_3D_CLEAR_ZMASK, 2));
956 OUT_RING(tileoffset * 128);
920 /* the number of tiles to clear */ 957 /* the number of tiles to clear */
921 OUT_RING( nrtilesx + 4 ); 958 OUT_RING(nrtilesx + 4);
922 /* clear mask : chooses the clearing pattern. */ 959 /* clear mask : chooses the clearing pattern. */
923 OUT_RING( clearmask ); 960 OUT_RING(clearmask);
924 ADVANCE_RING(); 961 ADVANCE_RING();
925 tileoffset += depthpixperline >> 6; 962 tileoffset += depthpixperline >> 6;
926 } 963 }
@@ -928,18 +965,19 @@ static void radeon_cp_dispatch_clear( drm_device_t *dev,
928 } 965 }
929 966
930 /* TODO don't always clear all hi-level z tiles */ 967 /* TODO don't always clear all hi-level z tiles */
931 if ((dev_priv->flags & CHIP_HAS_HIERZ) && (dev_priv->microcode_version==UCODE_R200) 968 if ((dev_priv->flags & CHIP_HAS_HIERZ)
932 && (flags & RADEON_USE_HIERZ)) 969 && (dev_priv->microcode_version == UCODE_R200)
933 /* r100 and cards without hierarchical z-buffer have no high-level z-buffer */ 970 && (flags & RADEON_USE_HIERZ))
934 /* FIXME : the mask supposedly contains low-res z values. So can't set 971 /* r100 and cards without hierarchical z-buffer have no high-level z-buffer */
935 just to the max (0xff? or actually 0x3fff?), need to take z clear 972 /* FIXME : the mask supposedly contains low-res z values. So can't set
936 value into account? */ 973 just to the max (0xff? or actually 0x3fff?), need to take z clear
974 value into account? */
937 { 975 {
938 BEGIN_RING( 4 ); 976 BEGIN_RING(4);
939 OUT_RING( CP_PACKET3( RADEON_3D_CLEAR_HIZ, 2 ) ); 977 OUT_RING(CP_PACKET3(RADEON_3D_CLEAR_HIZ, 2));
940 OUT_RING( 0x0 ); /* First tile */ 978 OUT_RING(0x0); /* First tile */
941 OUT_RING( 0x3cc0 ); 979 OUT_RING(0x3cc0);
942 OUT_RING( (0xff<<22)|(0xff<<6)| 0x003f003f); 980 OUT_RING((0xff << 22) | (0xff << 6) | 0x003f003f);
943 ADVANCE_RING(); 981 ADVANCE_RING();
944 } 982 }
945 } 983 }
@@ -974,30 +1012,27 @@ static void radeon_cp_dispatch_clear( drm_device_t *dev,
974 1012
975 tempSE_CNTL = depth_clear->se_cntl; 1013 tempSE_CNTL = depth_clear->se_cntl;
976 1014
977
978
979 /* Disable TCL */ 1015 /* Disable TCL */
980 1016
981 tempSE_VAP_CNTL = (/* SE_VAP_CNTL__FORCE_W_TO_ONE_MASK | */ 1017 tempSE_VAP_CNTL = ( /* SE_VAP_CNTL__FORCE_W_TO_ONE_MASK | */
982 (0x9 << SE_VAP_CNTL__VF_MAX_VTX_NUM__SHIFT)); 1018 (0x9 <<
1019 SE_VAP_CNTL__VF_MAX_VTX_NUM__SHIFT));
983 1020
984 tempRB3D_PLANEMASK = 0x0; 1021 tempRB3D_PLANEMASK = 0x0;
985 1022
986 tempRE_AUX_SCISSOR_CNTL = 0x0; 1023 tempRE_AUX_SCISSOR_CNTL = 0x0;
987 1024
988 tempSE_VTE_CNTL = 1025 tempSE_VTE_CNTL =
989 SE_VTE_CNTL__VTX_XY_FMT_MASK | 1026 SE_VTE_CNTL__VTX_XY_FMT_MASK | SE_VTE_CNTL__VTX_Z_FMT_MASK;
990 SE_VTE_CNTL__VTX_Z_FMT_MASK;
991 1027
992 /* Vertex format (X, Y, Z, W)*/ 1028 /* Vertex format (X, Y, Z, W) */
993 tempSE_VTX_FMT_0 = 1029 tempSE_VTX_FMT_0 =
994 SE_VTX_FMT_0__VTX_Z0_PRESENT_MASK | 1030 SE_VTX_FMT_0__VTX_Z0_PRESENT_MASK |
995 SE_VTX_FMT_0__VTX_W0_PRESENT_MASK; 1031 SE_VTX_FMT_0__VTX_W0_PRESENT_MASK;
996 tempSE_VTX_FMT_1 = 0x0; 1032 tempSE_VTX_FMT_1 = 0x0;
997 1033
998 1034 /*
999 /* 1035 * Depth buffer specific enables
1000 * Depth buffer specific enables
1001 */ 1036 */
1002 if (flags & RADEON_DEPTH) { 1037 if (flags & RADEON_DEPTH) {
1003 /* Enable depth buffer */ 1038 /* Enable depth buffer */
@@ -1007,12 +1042,12 @@ static void radeon_cp_dispatch_clear( drm_device_t *dev,
1007 tempRB3D_CNTL &= ~RADEON_Z_ENABLE; 1042 tempRB3D_CNTL &= ~RADEON_Z_ENABLE;
1008 } 1043 }
1009 1044
1010 /* 1045 /*
1011 * Stencil buffer specific enables 1046 * Stencil buffer specific enables
1012 */ 1047 */
1013 if ( flags & RADEON_STENCIL ) { 1048 if (flags & RADEON_STENCIL) {
1014 tempRB3D_CNTL |= RADEON_STENCIL_ENABLE; 1049 tempRB3D_CNTL |= RADEON_STENCIL_ENABLE;
1015 tempRB3D_STENCILREFMASK = clear->depth_mask; 1050 tempRB3D_STENCILREFMASK = clear->depth_mask;
1016 } else { 1051 } else {
1017 tempRB3D_CNTL &= ~RADEON_STENCIL_ENABLE; 1052 tempRB3D_CNTL &= ~RADEON_STENCIL_ENABLE;
1018 tempRB3D_STENCILREFMASK = 0x00000000; 1053 tempRB3D_STENCILREFMASK = 0x00000000;
@@ -1020,79 +1055,75 @@ static void radeon_cp_dispatch_clear( drm_device_t *dev,
1020 1055
1021 if (flags & RADEON_USE_COMP_ZBUF) { 1056 if (flags & RADEON_USE_COMP_ZBUF) {
1022 tempRB3D_ZSTENCILCNTL |= RADEON_Z_COMPRESSION_ENABLE | 1057 tempRB3D_ZSTENCILCNTL |= RADEON_Z_COMPRESSION_ENABLE |
1023 RADEON_Z_DECOMPRESSION_ENABLE; 1058 RADEON_Z_DECOMPRESSION_ENABLE;
1024 } 1059 }
1025 if (flags & RADEON_USE_HIERZ) { 1060 if (flags & RADEON_USE_HIERZ) {
1026 tempRB3D_ZSTENCILCNTL |= RADEON_Z_HIERARCHY_ENABLE; 1061 tempRB3D_ZSTENCILCNTL |= RADEON_Z_HIERARCHY_ENABLE;
1027 } 1062 }
1028 1063
1029 BEGIN_RING( 26 ); 1064 BEGIN_RING(26);
1030 RADEON_WAIT_UNTIL_2D_IDLE(); 1065 RADEON_WAIT_UNTIL_2D_IDLE();
1031 1066
1032 OUT_RING_REG( RADEON_PP_CNTL, tempPP_CNTL ); 1067 OUT_RING_REG(RADEON_PP_CNTL, tempPP_CNTL);
1033 OUT_RING_REG( R200_RE_CNTL, tempRE_CNTL ); 1068 OUT_RING_REG(R200_RE_CNTL, tempRE_CNTL);
1034 OUT_RING_REG( RADEON_RB3D_CNTL, tempRB3D_CNTL ); 1069 OUT_RING_REG(RADEON_RB3D_CNTL, tempRB3D_CNTL);
1035 OUT_RING_REG( RADEON_RB3D_ZSTENCILCNTL, 1070 OUT_RING_REG(RADEON_RB3D_ZSTENCILCNTL, tempRB3D_ZSTENCILCNTL);
1036 tempRB3D_ZSTENCILCNTL ); 1071 OUT_RING_REG(RADEON_RB3D_STENCILREFMASK,
1037 OUT_RING_REG( RADEON_RB3D_STENCILREFMASK, 1072 tempRB3D_STENCILREFMASK);
1038 tempRB3D_STENCILREFMASK ); 1073 OUT_RING_REG(RADEON_RB3D_PLANEMASK, tempRB3D_PLANEMASK);
1039 OUT_RING_REG( RADEON_RB3D_PLANEMASK, tempRB3D_PLANEMASK ); 1074 OUT_RING_REG(RADEON_SE_CNTL, tempSE_CNTL);
1040 OUT_RING_REG( RADEON_SE_CNTL, tempSE_CNTL ); 1075 OUT_RING_REG(R200_SE_VTE_CNTL, tempSE_VTE_CNTL);
1041 OUT_RING_REG( R200_SE_VTE_CNTL, tempSE_VTE_CNTL ); 1076 OUT_RING_REG(R200_SE_VTX_FMT_0, tempSE_VTX_FMT_0);
1042 OUT_RING_REG( R200_SE_VTX_FMT_0, tempSE_VTX_FMT_0 ); 1077 OUT_RING_REG(R200_SE_VTX_FMT_1, tempSE_VTX_FMT_1);
1043 OUT_RING_REG( R200_SE_VTX_FMT_1, tempSE_VTX_FMT_1 ); 1078 OUT_RING_REG(R200_SE_VAP_CNTL, tempSE_VAP_CNTL);
1044 OUT_RING_REG( R200_SE_VAP_CNTL, tempSE_VAP_CNTL ); 1079 OUT_RING_REG(R200_RE_AUX_SCISSOR_CNTL, tempRE_AUX_SCISSOR_CNTL);
1045 OUT_RING_REG( R200_RE_AUX_SCISSOR_CNTL,
1046 tempRE_AUX_SCISSOR_CNTL );
1047 ADVANCE_RING(); 1080 ADVANCE_RING();
1048 1081
1049 /* Make sure we restore the 3D state next time. 1082 /* Make sure we restore the 3D state next time.
1050 */ 1083 */
1051 dev_priv->sarea_priv->ctx_owner = 0; 1084 dev_priv->sarea_priv->ctx_owner = 0;
1052 1085
1053 for ( i = 0 ; i < nbox ; i++ ) { 1086 for (i = 0; i < nbox; i++) {
1054 1087
1055 /* Funny that this should be required -- 1088 /* Funny that this should be required --
1056 * sets top-left? 1089 * sets top-left?
1057 */ 1090 */
1058 radeon_emit_clip_rect( dev_priv, 1091 radeon_emit_clip_rect(dev_priv, &sarea_priv->boxes[i]);
1059 &sarea_priv->boxes[i] ); 1092
1060 1093 BEGIN_RING(14);
1061 BEGIN_RING( 14 ); 1094 OUT_RING(CP_PACKET3(R200_3D_DRAW_IMMD_2, 12));
1062 OUT_RING( CP_PACKET3( R200_3D_DRAW_IMMD_2, 12 ) ); 1095 OUT_RING((RADEON_PRIM_TYPE_RECT_LIST |
1063 OUT_RING( (RADEON_PRIM_TYPE_RECT_LIST | 1096 RADEON_PRIM_WALK_RING |
1064 RADEON_PRIM_WALK_RING | 1097 (3 << RADEON_NUM_VERTICES_SHIFT)));
1065 (3 << RADEON_NUM_VERTICES_SHIFT)) ); 1098 OUT_RING(depth_boxes[i].ui[CLEAR_X1]);
1066 OUT_RING( depth_boxes[i].ui[CLEAR_X1] ); 1099 OUT_RING(depth_boxes[i].ui[CLEAR_Y1]);
1067 OUT_RING( depth_boxes[i].ui[CLEAR_Y1] ); 1100 OUT_RING(depth_boxes[i].ui[CLEAR_DEPTH]);
1068 OUT_RING( depth_boxes[i].ui[CLEAR_DEPTH] ); 1101 OUT_RING(0x3f800000);
1069 OUT_RING( 0x3f800000 ); 1102 OUT_RING(depth_boxes[i].ui[CLEAR_X1]);
1070 OUT_RING( depth_boxes[i].ui[CLEAR_X1] ); 1103 OUT_RING(depth_boxes[i].ui[CLEAR_Y2]);
1071 OUT_RING( depth_boxes[i].ui[CLEAR_Y2] ); 1104 OUT_RING(depth_boxes[i].ui[CLEAR_DEPTH]);
1072 OUT_RING( depth_boxes[i].ui[CLEAR_DEPTH] ); 1105 OUT_RING(0x3f800000);
1073 OUT_RING( 0x3f800000 ); 1106 OUT_RING(depth_boxes[i].ui[CLEAR_X2]);
1074 OUT_RING( depth_boxes[i].ui[CLEAR_X2] ); 1107 OUT_RING(depth_boxes[i].ui[CLEAR_Y2]);
1075 OUT_RING( depth_boxes[i].ui[CLEAR_Y2] ); 1108 OUT_RING(depth_boxes[i].ui[CLEAR_DEPTH]);
1076 OUT_RING( depth_boxes[i].ui[CLEAR_DEPTH] ); 1109 OUT_RING(0x3f800000);
1077 OUT_RING( 0x3f800000 );
1078 ADVANCE_RING(); 1110 ADVANCE_RING();
1079 } 1111 }
1080 } 1112 } else if ((flags & (RADEON_DEPTH | RADEON_STENCIL))) {
1081 else if ( (flags & (RADEON_DEPTH | RADEON_STENCIL)) ) {
1082 1113
1083 int tempRB3D_ZSTENCILCNTL = depth_clear->rb3d_zstencilcntl; 1114 int tempRB3D_ZSTENCILCNTL = depth_clear->rb3d_zstencilcntl;
1084 1115
1085 rb3d_cntl = depth_clear->rb3d_cntl; 1116 rb3d_cntl = depth_clear->rb3d_cntl;
1086 1117
1087 if ( flags & RADEON_DEPTH ) { 1118 if (flags & RADEON_DEPTH) {
1088 rb3d_cntl |= RADEON_Z_ENABLE; 1119 rb3d_cntl |= RADEON_Z_ENABLE;
1089 } else { 1120 } else {
1090 rb3d_cntl &= ~RADEON_Z_ENABLE; 1121 rb3d_cntl &= ~RADEON_Z_ENABLE;
1091 } 1122 }
1092 1123
1093 if ( flags & RADEON_STENCIL ) { 1124 if (flags & RADEON_STENCIL) {
1094 rb3d_cntl |= RADEON_STENCIL_ENABLE; 1125 rb3d_cntl |= RADEON_STENCIL_ENABLE;
1095 rb3d_stencilrefmask = clear->depth_mask; /* misnamed field */ 1126 rb3d_stencilrefmask = clear->depth_mask; /* misnamed field */
1096 } else { 1127 } else {
1097 rb3d_cntl &= ~RADEON_STENCIL_ENABLE; 1128 rb3d_cntl &= ~RADEON_STENCIL_ENABLE;
1098 rb3d_stencilrefmask = 0x00000000; 1129 rb3d_stencilrefmask = 0x00000000;
@@ -1100,66 +1131,61 @@ static void radeon_cp_dispatch_clear( drm_device_t *dev,
1100 1131
1101 if (flags & RADEON_USE_COMP_ZBUF) { 1132 if (flags & RADEON_USE_COMP_ZBUF) {
1102 tempRB3D_ZSTENCILCNTL |= RADEON_Z_COMPRESSION_ENABLE | 1133 tempRB3D_ZSTENCILCNTL |= RADEON_Z_COMPRESSION_ENABLE |
1103 RADEON_Z_DECOMPRESSION_ENABLE; 1134 RADEON_Z_DECOMPRESSION_ENABLE;
1104 } 1135 }
1105 if (flags & RADEON_USE_HIERZ) { 1136 if (flags & RADEON_USE_HIERZ) {
1106 tempRB3D_ZSTENCILCNTL |= RADEON_Z_HIERARCHY_ENABLE; 1137 tempRB3D_ZSTENCILCNTL |= RADEON_Z_HIERARCHY_ENABLE;
1107 } 1138 }
1108 1139
1109 BEGIN_RING( 13 ); 1140 BEGIN_RING(13);
1110 RADEON_WAIT_UNTIL_2D_IDLE(); 1141 RADEON_WAIT_UNTIL_2D_IDLE();
1111 1142
1112 OUT_RING( CP_PACKET0( RADEON_PP_CNTL, 1 ) ); 1143 OUT_RING(CP_PACKET0(RADEON_PP_CNTL, 1));
1113 OUT_RING( 0x00000000 ); 1144 OUT_RING(0x00000000);
1114 OUT_RING( rb3d_cntl ); 1145 OUT_RING(rb3d_cntl);
1115 1146
1116 OUT_RING_REG( RADEON_RB3D_ZSTENCILCNTL, tempRB3D_ZSTENCILCNTL ); 1147 OUT_RING_REG(RADEON_RB3D_ZSTENCILCNTL, tempRB3D_ZSTENCILCNTL);
1117 OUT_RING_REG( RADEON_RB3D_STENCILREFMASK, 1148 OUT_RING_REG(RADEON_RB3D_STENCILREFMASK, rb3d_stencilrefmask);
1118 rb3d_stencilrefmask ); 1149 OUT_RING_REG(RADEON_RB3D_PLANEMASK, 0x00000000);
1119 OUT_RING_REG( RADEON_RB3D_PLANEMASK, 1150 OUT_RING_REG(RADEON_SE_CNTL, depth_clear->se_cntl);
1120 0x00000000 );
1121 OUT_RING_REG( RADEON_SE_CNTL,
1122 depth_clear->se_cntl );
1123 ADVANCE_RING(); 1151 ADVANCE_RING();
1124 1152
1125 /* Make sure we restore the 3D state next time. 1153 /* Make sure we restore the 3D state next time.
1126 */ 1154 */
1127 dev_priv->sarea_priv->ctx_owner = 0; 1155 dev_priv->sarea_priv->ctx_owner = 0;
1128 1156
1129 for ( i = 0 ; i < nbox ; i++ ) { 1157 for (i = 0; i < nbox; i++) {
1130 1158
1131 /* Funny that this should be required -- 1159 /* Funny that this should be required --
1132 * sets top-left? 1160 * sets top-left?
1133 */ 1161 */
1134 radeon_emit_clip_rect( dev_priv, 1162 radeon_emit_clip_rect(dev_priv, &sarea_priv->boxes[i]);
1135 &sarea_priv->boxes[i] ); 1163
1136 1164 BEGIN_RING(15);
1137 BEGIN_RING( 15 ); 1165
1138 1166 OUT_RING(CP_PACKET3(RADEON_3D_DRAW_IMMD, 13));
1139 OUT_RING( CP_PACKET3( RADEON_3D_DRAW_IMMD, 13 ) ); 1167 OUT_RING(RADEON_VTX_Z_PRESENT |
1140 OUT_RING( RADEON_VTX_Z_PRESENT | 1168 RADEON_VTX_PKCOLOR_PRESENT);
1141 RADEON_VTX_PKCOLOR_PRESENT); 1169 OUT_RING((RADEON_PRIM_TYPE_RECT_LIST |
1142 OUT_RING( (RADEON_PRIM_TYPE_RECT_LIST | 1170 RADEON_PRIM_WALK_RING |
1143 RADEON_PRIM_WALK_RING | 1171 RADEON_MAOS_ENABLE |
1144 RADEON_MAOS_ENABLE | 1172 RADEON_VTX_FMT_RADEON_MODE |
1145 RADEON_VTX_FMT_RADEON_MODE | 1173 (3 << RADEON_NUM_VERTICES_SHIFT)));
1146 (3 << RADEON_NUM_VERTICES_SHIFT)) ); 1174
1147 1175 OUT_RING(depth_boxes[i].ui[CLEAR_X1]);
1148 1176 OUT_RING(depth_boxes[i].ui[CLEAR_Y1]);
1149 OUT_RING( depth_boxes[i].ui[CLEAR_X1] ); 1177 OUT_RING(depth_boxes[i].ui[CLEAR_DEPTH]);
1150 OUT_RING( depth_boxes[i].ui[CLEAR_Y1] ); 1178 OUT_RING(0x0);
1151 OUT_RING( depth_boxes[i].ui[CLEAR_DEPTH] ); 1179
1152 OUT_RING( 0x0 ); 1180 OUT_RING(depth_boxes[i].ui[CLEAR_X1]);
1153 1181 OUT_RING(depth_boxes[i].ui[CLEAR_Y2]);
1154 OUT_RING( depth_boxes[i].ui[CLEAR_X1] ); 1182 OUT_RING(depth_boxes[i].ui[CLEAR_DEPTH]);
1155 OUT_RING( depth_boxes[i].ui[CLEAR_Y2] ); 1183 OUT_RING(0x0);
1156 OUT_RING( depth_boxes[i].ui[CLEAR_DEPTH] ); 1184
1157 OUT_RING( 0x0 ); 1185 OUT_RING(depth_boxes[i].ui[CLEAR_X2]);
1158 1186 OUT_RING(depth_boxes[i].ui[CLEAR_Y2]);
1159 OUT_RING( depth_boxes[i].ui[CLEAR_X2] ); 1187 OUT_RING(depth_boxes[i].ui[CLEAR_DEPTH]);
1160 OUT_RING( depth_boxes[i].ui[CLEAR_Y2] ); 1188 OUT_RING(0x0);
1161 OUT_RING( depth_boxes[i].ui[CLEAR_DEPTH] );
1162 OUT_RING( 0x0 );
1163 1189
1164 ADVANCE_RING(); 1190 ADVANCE_RING();
1165 } 1191 }
@@ -1171,15 +1197,15 @@ static void radeon_cp_dispatch_clear( drm_device_t *dev,
1171 */ 1197 */
1172 dev_priv->sarea_priv->last_clear++; 1198 dev_priv->sarea_priv->last_clear++;
1173 1199
1174 BEGIN_RING( 4 ); 1200 BEGIN_RING(4);
1175 1201
1176 RADEON_CLEAR_AGE( dev_priv->sarea_priv->last_clear ); 1202 RADEON_CLEAR_AGE(dev_priv->sarea_priv->last_clear);
1177 RADEON_WAIT_UNTIL_IDLE(); 1203 RADEON_WAIT_UNTIL_IDLE();
1178 1204
1179 ADVANCE_RING(); 1205 ADVANCE_RING();
1180} 1206}
1181 1207
1182static void radeon_cp_dispatch_swap( drm_device_t *dev ) 1208static void radeon_cp_dispatch_swap(drm_device_t * dev)
1183{ 1209{
1184 drm_radeon_private_t *dev_priv = dev->dev_private; 1210 drm_radeon_private_t *dev_priv = dev->dev_private;
1185 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; 1211 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
@@ -1187,59 +1213,55 @@ static void radeon_cp_dispatch_swap( drm_device_t *dev )
1187 drm_clip_rect_t *pbox = sarea_priv->boxes; 1213 drm_clip_rect_t *pbox = sarea_priv->boxes;
1188 int i; 1214 int i;
1189 RING_LOCALS; 1215 RING_LOCALS;
1190 DRM_DEBUG( "\n" ); 1216 DRM_DEBUG("\n");
1191 1217
1192 /* Do some trivial performance monitoring... 1218 /* Do some trivial performance monitoring...
1193 */ 1219 */
1194 if (dev_priv->do_boxes) 1220 if (dev_priv->do_boxes)
1195 radeon_cp_performance_boxes( dev_priv ); 1221 radeon_cp_performance_boxes(dev_priv);
1196
1197 1222
1198 /* Wait for the 3D stream to idle before dispatching the bitblt. 1223 /* Wait for the 3D stream to idle before dispatching the bitblt.
1199 * This will prevent data corruption between the two streams. 1224 * This will prevent data corruption between the two streams.
1200 */ 1225 */
1201 BEGIN_RING( 2 ); 1226 BEGIN_RING(2);
1202 1227
1203 RADEON_WAIT_UNTIL_3D_IDLE(); 1228 RADEON_WAIT_UNTIL_3D_IDLE();
1204 1229
1205 ADVANCE_RING(); 1230 ADVANCE_RING();
1206 1231
1207 for ( i = 0 ; i < nbox ; i++ ) { 1232 for (i = 0; i < nbox; i++) {
1208 int x = pbox[i].x1; 1233 int x = pbox[i].x1;
1209 int y = pbox[i].y1; 1234 int y = pbox[i].y1;
1210 int w = pbox[i].x2 - x; 1235 int w = pbox[i].x2 - x;
1211 int h = pbox[i].y2 - y; 1236 int h = pbox[i].y2 - y;
1212 1237
1213 DRM_DEBUG( "dispatch swap %d,%d-%d,%d\n", 1238 DRM_DEBUG("dispatch swap %d,%d-%d,%d\n", x, y, w, h);
1214 x, y, w, h ); 1239
1215 1240 BEGIN_RING(7);
1216 BEGIN_RING( 7 ); 1241
1217 1242 OUT_RING(CP_PACKET3(RADEON_CNTL_BITBLT_MULTI, 5));
1218 OUT_RING( CP_PACKET3( RADEON_CNTL_BITBLT_MULTI, 5 ) ); 1243 OUT_RING(RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
1219 OUT_RING( RADEON_GMC_SRC_PITCH_OFFSET_CNTL | 1244 RADEON_GMC_DST_PITCH_OFFSET_CNTL |
1220 RADEON_GMC_DST_PITCH_OFFSET_CNTL | 1245 RADEON_GMC_BRUSH_NONE |
1221 RADEON_GMC_BRUSH_NONE | 1246 (dev_priv->color_fmt << 8) |
1222 (dev_priv->color_fmt << 8) | 1247 RADEON_GMC_SRC_DATATYPE_COLOR |
1223 RADEON_GMC_SRC_DATATYPE_COLOR | 1248 RADEON_ROP3_S |
1224 RADEON_ROP3_S | 1249 RADEON_DP_SRC_SOURCE_MEMORY |
1225 RADEON_DP_SRC_SOURCE_MEMORY | 1250 RADEON_GMC_CLR_CMP_CNTL_DIS | RADEON_GMC_WR_MSK_DIS);
1226 RADEON_GMC_CLR_CMP_CNTL_DIS | 1251
1227 RADEON_GMC_WR_MSK_DIS );
1228
1229 /* Make this work even if front & back are flipped: 1252 /* Make this work even if front & back are flipped:
1230 */ 1253 */
1231 if (dev_priv->current_page == 0) { 1254 if (dev_priv->current_page == 0) {
1232 OUT_RING( dev_priv->back_pitch_offset ); 1255 OUT_RING(dev_priv->back_pitch_offset);
1233 OUT_RING( dev_priv->front_pitch_offset ); 1256 OUT_RING(dev_priv->front_pitch_offset);
1234 } 1257 } else {
1235 else { 1258 OUT_RING(dev_priv->front_pitch_offset);
1236 OUT_RING( dev_priv->front_pitch_offset ); 1259 OUT_RING(dev_priv->back_pitch_offset);
1237 OUT_RING( dev_priv->back_pitch_offset );
1238 } 1260 }
1239 1261
1240 OUT_RING( (x << 16) | y ); 1262 OUT_RING((x << 16) | y);
1241 OUT_RING( (x << 16) | y ); 1263 OUT_RING((x << 16) | y);
1242 OUT_RING( (w << 16) | h ); 1264 OUT_RING((w << 16) | h);
1243 1265
1244 ADVANCE_RING(); 1266 ADVANCE_RING();
1245 } 1267 }
@@ -1250,44 +1272,43 @@ static void radeon_cp_dispatch_swap( drm_device_t *dev )
1250 */ 1272 */
1251 dev_priv->sarea_priv->last_frame++; 1273 dev_priv->sarea_priv->last_frame++;
1252 1274
1253 BEGIN_RING( 4 ); 1275 BEGIN_RING(4);
1254 1276
1255 RADEON_FRAME_AGE( dev_priv->sarea_priv->last_frame ); 1277 RADEON_FRAME_AGE(dev_priv->sarea_priv->last_frame);
1256 RADEON_WAIT_UNTIL_2D_IDLE(); 1278 RADEON_WAIT_UNTIL_2D_IDLE();
1257 1279
1258 ADVANCE_RING(); 1280 ADVANCE_RING();
1259} 1281}
1260 1282
1261static void radeon_cp_dispatch_flip( drm_device_t *dev ) 1283static void radeon_cp_dispatch_flip(drm_device_t * dev)
1262{ 1284{
1263 drm_radeon_private_t *dev_priv = dev->dev_private; 1285 drm_radeon_private_t *dev_priv = dev->dev_private;
1264 drm_sarea_t *sarea = (drm_sarea_t *)dev_priv->sarea->handle; 1286 drm_sarea_t *sarea = (drm_sarea_t *) dev_priv->sarea->handle;
1265 int offset = (dev_priv->current_page == 1) 1287 int offset = (dev_priv->current_page == 1)
1266 ? dev_priv->front_offset : dev_priv->back_offset; 1288 ? dev_priv->front_offset : dev_priv->back_offset;
1267 RING_LOCALS; 1289 RING_LOCALS;
1268 DRM_DEBUG( "%s: page=%d pfCurrentPage=%d\n", 1290 DRM_DEBUG("%s: page=%d pfCurrentPage=%d\n",
1269 __FUNCTION__, 1291 __FUNCTION__,
1270 dev_priv->current_page, 1292 dev_priv->current_page, dev_priv->sarea_priv->pfCurrentPage);
1271 dev_priv->sarea_priv->pfCurrentPage);
1272 1293
1273 /* Do some trivial performance monitoring... 1294 /* Do some trivial performance monitoring...
1274 */ 1295 */
1275 if (dev_priv->do_boxes) { 1296 if (dev_priv->do_boxes) {
1276 dev_priv->stats.boxes |= RADEON_BOX_FLIP; 1297 dev_priv->stats.boxes |= RADEON_BOX_FLIP;
1277 radeon_cp_performance_boxes( dev_priv ); 1298 radeon_cp_performance_boxes(dev_priv);
1278 } 1299 }
1279 1300
1280 /* Update the frame offsets for both CRTCs 1301 /* Update the frame offsets for both CRTCs
1281 */ 1302 */
1282 BEGIN_RING( 6 ); 1303 BEGIN_RING(6);
1283 1304
1284 RADEON_WAIT_UNTIL_3D_IDLE(); 1305 RADEON_WAIT_UNTIL_3D_IDLE();
1285 OUT_RING_REG( RADEON_CRTC_OFFSET, ( ( sarea->frame.y * dev_priv->front_pitch 1306 OUT_RING_REG(RADEON_CRTC_OFFSET,
1286 + sarea->frame.x 1307 ((sarea->frame.y * dev_priv->front_pitch +
1287 * ( dev_priv->color_fmt - 2 ) ) & ~7 ) 1308 sarea->frame.x * (dev_priv->color_fmt - 2)) & ~7)
1288 + offset ); 1309 + offset);
1289 OUT_RING_REG( RADEON_CRTC2_OFFSET, dev_priv->sarea_priv->crtc2_base 1310 OUT_RING_REG(RADEON_CRTC2_OFFSET, dev_priv->sarea_priv->crtc2_base
1290 + offset ); 1311 + offset);
1291 1312
1292 ADVANCE_RING(); 1313 ADVANCE_RING();
1293 1314
@@ -1297,16 +1318,16 @@ static void radeon_cp_dispatch_flip( drm_device_t *dev )
1297 */ 1318 */
1298 dev_priv->sarea_priv->last_frame++; 1319 dev_priv->sarea_priv->last_frame++;
1299 dev_priv->sarea_priv->pfCurrentPage = dev_priv->current_page = 1320 dev_priv->sarea_priv->pfCurrentPage = dev_priv->current_page =
1300 1 - dev_priv->current_page; 1321 1 - dev_priv->current_page;
1301 1322
1302 BEGIN_RING( 2 ); 1323 BEGIN_RING(2);
1303 1324
1304 RADEON_FRAME_AGE( dev_priv->sarea_priv->last_frame ); 1325 RADEON_FRAME_AGE(dev_priv->sarea_priv->last_frame);
1305 1326
1306 ADVANCE_RING(); 1327 ADVANCE_RING();
1307} 1328}
1308 1329
1309static int bad_prim_vertex_nr( int primitive, int nr ) 1330static int bad_prim_vertex_nr(int primitive, int nr)
1310{ 1331{
1311 switch (primitive & RADEON_PRIM_TYPE_MASK) { 1332 switch (primitive & RADEON_PRIM_TYPE_MASK) {
1312 case RADEON_PRIM_TYPE_NONE: 1333 case RADEON_PRIM_TYPE_NONE:
@@ -1326,24 +1347,21 @@ static int bad_prim_vertex_nr( int primitive, int nr )
1326 return nr < 3; 1347 return nr < 3;
1327 default: 1348 default:
1328 return 1; 1349 return 1;
1329 } 1350 }
1330} 1351}
1331 1352
1332
1333
1334typedef struct { 1353typedef struct {
1335 unsigned int start; 1354 unsigned int start;
1336 unsigned int finish; 1355 unsigned int finish;
1337 unsigned int prim; 1356 unsigned int prim;
1338 unsigned int numverts; 1357 unsigned int numverts;
1339 unsigned int offset; 1358 unsigned int offset;
1340 unsigned int vc_format; 1359 unsigned int vc_format;
1341} drm_radeon_tcl_prim_t; 1360} drm_radeon_tcl_prim_t;
1342 1361
1343static void radeon_cp_dispatch_vertex( drm_device_t *dev, 1362static void radeon_cp_dispatch_vertex(drm_device_t * dev,
1344 drm_buf_t *buf, 1363 drm_buf_t * buf,
1345 drm_radeon_tcl_prim_t *prim ) 1364 drm_radeon_tcl_prim_t * prim)
1346
1347{ 1365{
1348 drm_radeon_private_t *dev_priv = dev->dev_private; 1366 drm_radeon_private_t *dev_priv = dev->dev_private;
1349 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; 1367 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
@@ -1355,45 +1373,39 @@ static void radeon_cp_dispatch_vertex( drm_device_t *dev,
1355 1373
1356 DRM_DEBUG("hwprim 0x%x vfmt 0x%x %d..%d %d verts\n", 1374 DRM_DEBUG("hwprim 0x%x vfmt 0x%x %d..%d %d verts\n",
1357 prim->prim, 1375 prim->prim,
1358 prim->vc_format, 1376 prim->vc_format, prim->start, prim->finish, prim->numverts);
1359 prim->start,
1360 prim->finish,
1361 prim->numverts);
1362 1377
1363 if (bad_prim_vertex_nr( prim->prim, prim->numverts )) { 1378 if (bad_prim_vertex_nr(prim->prim, prim->numverts)) {
1364 DRM_ERROR( "bad prim %x numverts %d\n", 1379 DRM_ERROR("bad prim %x numverts %d\n",
1365 prim->prim, prim->numverts ); 1380 prim->prim, prim->numverts);
1366 return; 1381 return;
1367 } 1382 }
1368 1383
1369 do { 1384 do {
1370 /* Emit the next cliprect */ 1385 /* Emit the next cliprect */
1371 if ( i < nbox ) { 1386 if (i < nbox) {
1372 radeon_emit_clip_rect( dev_priv, 1387 radeon_emit_clip_rect(dev_priv, &sarea_priv->boxes[i]);
1373 &sarea_priv->boxes[i] );
1374 } 1388 }
1375 1389
1376 /* Emit the vertex buffer rendering commands */ 1390 /* Emit the vertex buffer rendering commands */
1377 BEGIN_RING( 5 ); 1391 BEGIN_RING(5);
1378 1392
1379 OUT_RING( CP_PACKET3( RADEON_3D_RNDR_GEN_INDX_PRIM, 3 ) ); 1393 OUT_RING(CP_PACKET3(RADEON_3D_RNDR_GEN_INDX_PRIM, 3));
1380 OUT_RING( offset ); 1394 OUT_RING(offset);
1381 OUT_RING( numverts ); 1395 OUT_RING(numverts);
1382 OUT_RING( prim->vc_format ); 1396 OUT_RING(prim->vc_format);
1383 OUT_RING( prim->prim | RADEON_PRIM_WALK_LIST | 1397 OUT_RING(prim->prim | RADEON_PRIM_WALK_LIST |
1384 RADEON_COLOR_ORDER_RGBA | 1398 RADEON_COLOR_ORDER_RGBA |
1385 RADEON_VTX_FMT_RADEON_MODE | 1399 RADEON_VTX_FMT_RADEON_MODE |
1386 (numverts << RADEON_NUM_VERTICES_SHIFT) ); 1400 (numverts << RADEON_NUM_VERTICES_SHIFT));
1387 1401
1388 ADVANCE_RING(); 1402 ADVANCE_RING();
1389 1403
1390 i++; 1404 i++;
1391 } while ( i < nbox ); 1405 } while (i < nbox);
1392} 1406}
1393 1407
1394 1408static void radeon_cp_discard_buffer(drm_device_t * dev, drm_buf_t * buf)
1395
1396static void radeon_cp_discard_buffer( drm_device_t *dev, drm_buf_t *buf )
1397{ 1409{
1398 drm_radeon_private_t *dev_priv = dev->dev_private; 1410 drm_radeon_private_t *dev_priv = dev->dev_private;
1399 drm_radeon_buf_priv_t *buf_priv = buf->dev_private; 1411 drm_radeon_buf_priv_t *buf_priv = buf->dev_private;
@@ -1402,24 +1414,22 @@ static void radeon_cp_discard_buffer( drm_device_t *dev, drm_buf_t *buf )
1402 buf_priv->age = ++dev_priv->sarea_priv->last_dispatch; 1414 buf_priv->age = ++dev_priv->sarea_priv->last_dispatch;
1403 1415
1404 /* Emit the vertex buffer age */ 1416 /* Emit the vertex buffer age */
1405 BEGIN_RING( 2 ); 1417 BEGIN_RING(2);
1406 RADEON_DISPATCH_AGE( buf_priv->age ); 1418 RADEON_DISPATCH_AGE(buf_priv->age);
1407 ADVANCE_RING(); 1419 ADVANCE_RING();
1408 1420
1409 buf->pending = 1; 1421 buf->pending = 1;
1410 buf->used = 0; 1422 buf->used = 0;
1411} 1423}
1412 1424
1413static void radeon_cp_dispatch_indirect( drm_device_t *dev, 1425static void radeon_cp_dispatch_indirect(drm_device_t * dev,
1414 drm_buf_t *buf, 1426 drm_buf_t * buf, int start, int end)
1415 int start, int end )
1416{ 1427{
1417 drm_radeon_private_t *dev_priv = dev->dev_private; 1428 drm_radeon_private_t *dev_priv = dev->dev_private;
1418 RING_LOCALS; 1429 RING_LOCALS;
1419 DRM_DEBUG( "indirect: buf=%d s=0x%x e=0x%x\n", 1430 DRM_DEBUG("indirect: buf=%d s=0x%x e=0x%x\n", buf->idx, start, end);
1420 buf->idx, start, end );
1421 1431
1422 if ( start != end ) { 1432 if (start != end) {
1423 int offset = (dev_priv->gart_buffers_offset 1433 int offset = (dev_priv->gart_buffers_offset
1424 + buf->offset + start); 1434 + buf->offset + start);
1425 int dwords = (end - start + 3) / sizeof(u32); 1435 int dwords = (end - start + 3) / sizeof(u32);
@@ -1428,28 +1438,27 @@ static void radeon_cp_dispatch_indirect( drm_device_t *dev,
1428 * dwords, so if we've been given an odd number we must 1438 * dwords, so if we've been given an odd number we must
1429 * pad the data with a Type-2 CP packet. 1439 * pad the data with a Type-2 CP packet.
1430 */ 1440 */
1431 if ( dwords & 1 ) { 1441 if (dwords & 1) {
1432 u32 *data = (u32 *) 1442 u32 *data = (u32 *)
1433 ((char *)dev->agp_buffer_map->handle 1443 ((char *)dev->agp_buffer_map->handle
1434 + buf->offset + start); 1444 + buf->offset + start);
1435 data[dwords++] = RADEON_CP_PACKET2; 1445 data[dwords++] = RADEON_CP_PACKET2;
1436 } 1446 }
1437 1447
1438 /* Fire off the indirect buffer */ 1448 /* Fire off the indirect buffer */
1439 BEGIN_RING( 3 ); 1449 BEGIN_RING(3);
1440 1450
1441 OUT_RING( CP_PACKET0( RADEON_CP_IB_BASE, 1 ) ); 1451 OUT_RING(CP_PACKET0(RADEON_CP_IB_BASE, 1));
1442 OUT_RING( offset ); 1452 OUT_RING(offset);
1443 OUT_RING( dwords ); 1453 OUT_RING(dwords);
1444 1454
1445 ADVANCE_RING(); 1455 ADVANCE_RING();
1446 } 1456 }
1447} 1457}
1448 1458
1449 1459static void radeon_cp_dispatch_indices(drm_device_t * dev,
1450static void radeon_cp_dispatch_indices( drm_device_t *dev, 1460 drm_buf_t * elt_buf,
1451 drm_buf_t *elt_buf, 1461 drm_radeon_tcl_prim_t * prim)
1452 drm_radeon_tcl_prim_t *prim )
1453{ 1462{
1454 drm_radeon_private_t *dev_priv = dev->dev_private; 1463 drm_radeon_private_t *dev_priv = dev->dev_private;
1455 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; 1464 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
@@ -1464,30 +1473,24 @@ static void radeon_cp_dispatch_indices( drm_device_t *dev,
1464 DRM_DEBUG("hwprim 0x%x vfmt 0x%x %d..%d offset: %x nr %d\n", 1473 DRM_DEBUG("hwprim 0x%x vfmt 0x%x %d..%d offset: %x nr %d\n",
1465 prim->prim, 1474 prim->prim,
1466 prim->vc_format, 1475 prim->vc_format,
1467 prim->start, 1476 prim->start, prim->finish, prim->offset, prim->numverts);
1468 prim->finish, 1477
1469 prim->offset, 1478 if (bad_prim_vertex_nr(prim->prim, count)) {
1470 prim->numverts); 1479 DRM_ERROR("bad prim %x count %d\n", prim->prim, count);
1471
1472 if (bad_prim_vertex_nr( prim->prim, count )) {
1473 DRM_ERROR( "bad prim %x count %d\n",
1474 prim->prim, count );
1475 return; 1480 return;
1476 } 1481 }
1477 1482
1478 1483 if (start >= prim->finish || (prim->start & 0x7)) {
1479 if ( start >= prim->finish || 1484 DRM_ERROR("buffer prim %d\n", prim->prim);
1480 (prim->start & 0x7) ) {
1481 DRM_ERROR( "buffer prim %d\n", prim->prim );
1482 return; 1485 return;
1483 } 1486 }
1484 1487
1485 dwords = (prim->finish - prim->start + 3) / sizeof(u32); 1488 dwords = (prim->finish - prim->start + 3) / sizeof(u32);
1486 1489
1487 data = (u32 *)((char *)dev->agp_buffer_map->handle + 1490 data = (u32 *) ((char *)dev->agp_buffer_map->handle +
1488 elt_buf->offset + prim->start); 1491 elt_buf->offset + prim->start);
1489 1492
1490 data[0] = CP_PACKET3( RADEON_3D_RNDR_GEN_INDX_PRIM, dwords-2 ); 1493 data[0] = CP_PACKET3(RADEON_3D_RNDR_GEN_INDX_PRIM, dwords - 2);
1491 data[1] = offset; 1494 data[1] = offset;
1492 data[2] = prim->numverts; 1495 data[2] = prim->numverts;
1493 data[3] = prim->vc_format; 1496 data[3] = prim->vc_format;
@@ -1495,28 +1498,26 @@ static void radeon_cp_dispatch_indices( drm_device_t *dev,
1495 RADEON_PRIM_WALK_IND | 1498 RADEON_PRIM_WALK_IND |
1496 RADEON_COLOR_ORDER_RGBA | 1499 RADEON_COLOR_ORDER_RGBA |
1497 RADEON_VTX_FMT_RADEON_MODE | 1500 RADEON_VTX_FMT_RADEON_MODE |
1498 (count << RADEON_NUM_VERTICES_SHIFT) ); 1501 (count << RADEON_NUM_VERTICES_SHIFT));
1499 1502
1500 do { 1503 do {
1501 if ( i < nbox ) 1504 if (i < nbox)
1502 radeon_emit_clip_rect( dev_priv, 1505 radeon_emit_clip_rect(dev_priv, &sarea_priv->boxes[i]);
1503 &sarea_priv->boxes[i] );
1504 1506
1505 radeon_cp_dispatch_indirect( dev, elt_buf, 1507 radeon_cp_dispatch_indirect(dev, elt_buf,
1506 prim->start, 1508 prim->start, prim->finish);
1507 prim->finish );
1508 1509
1509 i++; 1510 i++;
1510 } while ( i < nbox ); 1511 } while (i < nbox);
1511 1512
1512} 1513}
1513 1514
1514#define RADEON_MAX_TEXTURE_SIZE RADEON_BUFFER_SIZE 1515#define RADEON_MAX_TEXTURE_SIZE RADEON_BUFFER_SIZE
1515 1516
1516static int radeon_cp_dispatch_texture( DRMFILE filp, 1517static int radeon_cp_dispatch_texture(DRMFILE filp,
1517 drm_device_t *dev, 1518 drm_device_t * dev,
1518 drm_radeon_texture_t *tex, 1519 drm_radeon_texture_t * tex,
1519 drm_radeon_tex_image_t *image ) 1520 drm_radeon_tex_image_t * image)
1520{ 1521{
1521 drm_radeon_private_t *dev_priv = dev->dev_private; 1522 drm_radeon_private_t *dev_priv = dev->dev_private;
1522 drm_file_t *filp_priv; 1523 drm_file_t *filp_priv;
@@ -1531,11 +1532,11 @@ static int radeon_cp_dispatch_texture( DRMFILE filp,
1531 u32 offset; 1532 u32 offset;
1532 RING_LOCALS; 1533 RING_LOCALS;
1533 1534
1534 DRM_GET_PRIV_WITH_RETURN( filp_priv, filp ); 1535 DRM_GET_PRIV_WITH_RETURN(filp_priv, filp);
1535 1536
1536 if ( radeon_check_and_fixup_offset( dev_priv, filp_priv, &tex->offset ) ) { 1537 if (radeon_check_and_fixup_offset(dev_priv, filp_priv, &tex->offset)) {
1537 DRM_ERROR( "Invalid destination offset\n" ); 1538 DRM_ERROR("Invalid destination offset\n");
1538 return DRM_ERR( EINVAL ); 1539 return DRM_ERR(EINVAL);
1539 } 1540 }
1540 1541
1541 dev_priv->stats.boxes |= RADEON_BOX_TEXTURE_LOAD; 1542 dev_priv->stats.boxes |= RADEON_BOX_TEXTURE_LOAD;
@@ -1544,7 +1545,7 @@ static int radeon_cp_dispatch_texture( DRMFILE filp,
1544 * up with the texture data from the host data blit, otherwise 1545 * up with the texture data from the host data blit, otherwise
1545 * part of the texture image may be corrupted. 1546 * part of the texture image may be corrupted.
1546 */ 1547 */
1547 BEGIN_RING( 4 ); 1548 BEGIN_RING(4);
1548 RADEON_FLUSH_CACHE(); 1549 RADEON_FLUSH_CACHE();
1549 RADEON_WAIT_UNTIL_IDLE(); 1550 RADEON_WAIT_UNTIL_IDLE();
1550 ADVANCE_RING(); 1551 ADVANCE_RING();
@@ -1553,7 +1554,7 @@ static int radeon_cp_dispatch_texture( DRMFILE filp,
1553 * even if the only legal values are powers of two. Thus, we'll 1554 * even if the only legal values are powers of two. Thus, we'll
1554 * use a shift instead. 1555 * use a shift instead.
1555 */ 1556 */
1556 switch ( tex->format ) { 1557 switch (tex->format) {
1557 case RADEON_TXFORMAT_ARGB8888: 1558 case RADEON_TXFORMAT_ARGB8888:
1558 case RADEON_TXFORMAT_RGBA8888: 1559 case RADEON_TXFORMAT_RGBA8888:
1559 format = RADEON_COLOR_FORMAT_ARGB8888; 1560 format = RADEON_COLOR_FORMAT_ARGB8888;
@@ -1577,7 +1578,7 @@ static int radeon_cp_dispatch_texture( DRMFILE filp,
1577 blit_width = image->width * 1; 1578 blit_width = image->width * 1;
1578 break; 1579 break;
1579 default: 1580 default:
1580 DRM_ERROR( "invalid texture format %d\n", tex->format ); 1581 DRM_ERROR("invalid texture format %d\n", tex->format);
1581 return DRM_ERR(EINVAL); 1582 return DRM_ERR(EINVAL);
1582 } 1583 }
1583 spitch = blit_width >> 6; 1584 spitch = blit_width >> 6;
@@ -1592,49 +1593,49 @@ static int radeon_cp_dispatch_texture( DRMFILE filp,
1592 /* we got tiled coordinates, untile them */ 1593 /* we got tiled coordinates, untile them */
1593 image->x *= 2; 1594 image->x *= 2;
1594 } 1595 }
1595 } 1596 } else
1596 else microtile = 0; 1597 microtile = 0;
1597 1598
1598 DRM_DEBUG("tex=%dx%d blit=%d\n", tex_width, tex->height, blit_width ); 1599 DRM_DEBUG("tex=%dx%d blit=%d\n", tex_width, tex->height, blit_width);
1599 1600
1600 do { 1601 do {
1601 DRM_DEBUG( "tex: ofs=0x%x p=%d f=%d x=%hd y=%hd w=%hd h=%hd\n", 1602 DRM_DEBUG("tex: ofs=0x%x p=%d f=%d x=%hd y=%hd w=%hd h=%hd\n",
1602 tex->offset >> 10, tex->pitch, tex->format, 1603 tex->offset >> 10, tex->pitch, tex->format,
1603 image->x, image->y, image->width, image->height ); 1604 image->x, image->y, image->width, image->height);
1604 1605
1605 /* Make a copy of some parameters in case we have to 1606 /* Make a copy of some parameters in case we have to
1606 * update them for a multi-pass texture blit. 1607 * update them for a multi-pass texture blit.
1607 */ 1608 */
1608 height = image->height; 1609 height = image->height;
1609 data = (const u8 __user *)image->data; 1610 data = (const u8 __user *)image->data;
1610 1611
1611 size = height * blit_width; 1612 size = height * blit_width;
1612 1613
1613 if ( size > RADEON_MAX_TEXTURE_SIZE ) { 1614 if (size > RADEON_MAX_TEXTURE_SIZE) {
1614 height = RADEON_MAX_TEXTURE_SIZE / blit_width; 1615 height = RADEON_MAX_TEXTURE_SIZE / blit_width;
1615 size = height * blit_width; 1616 size = height * blit_width;
1616 } else if ( size < 4 && size > 0 ) { 1617 } else if (size < 4 && size > 0) {
1617 size = 4; 1618 size = 4;
1618 } else if ( size == 0 ) { 1619 } else if (size == 0) {
1619 return 0; 1620 return 0;
1620 } 1621 }
1621 1622
1622 buf = radeon_freelist_get( dev ); 1623 buf = radeon_freelist_get(dev);
1623 if ( 0 && !buf ) { 1624 if (0 && !buf) {
1624 radeon_do_cp_idle( dev_priv ); 1625 radeon_do_cp_idle(dev_priv);
1625 buf = radeon_freelist_get( dev ); 1626 buf = radeon_freelist_get(dev);
1626 } 1627 }
1627 if ( !buf ) { 1628 if (!buf) {
1628 DRM_DEBUG("radeon_cp_dispatch_texture: EAGAIN\n"); 1629 DRM_DEBUG("radeon_cp_dispatch_texture: EAGAIN\n");
1629 if (DRM_COPY_TO_USER( tex->image, image, sizeof(*image) )) 1630 if (DRM_COPY_TO_USER(tex->image, image, sizeof(*image)))
1630 return DRM_ERR(EFAULT); 1631 return DRM_ERR(EFAULT);
1631 return DRM_ERR(EAGAIN); 1632 return DRM_ERR(EAGAIN);
1632 } 1633 }
1633 1634
1634
1635 /* Dispatch the indirect buffer. 1635 /* Dispatch the indirect buffer.
1636 */ 1636 */
1637 buffer = (u32*)((char*)dev->agp_buffer_map->handle + buf->offset); 1637 buffer =
1638 (u32 *) ((char *)dev->agp_buffer_map->handle + buf->offset);
1638 dwords = size / 4; 1639 dwords = size / 4;
1639 1640
1640 if (microtile) { 1641 if (microtile) {
@@ -1649,20 +1650,26 @@ static int radeon_cp_dispatch_texture( DRMFILE filp,
1649 if (tex->height == 1) { 1650 if (tex->height == 1) {
1650 if (tex_width >= 64 || tex_width <= 16) { 1651 if (tex_width >= 64 || tex_width <= 16) {
1651 if (DRM_COPY_FROM_USER(buffer, data, 1652 if (DRM_COPY_FROM_USER(buffer, data,
1652 tex_width * sizeof(u32))) { 1653 tex_width *
1653 DRM_ERROR("EFAULT on pad, %d bytes\n", 1654 sizeof(u32))) {
1654 tex_width); 1655 DRM_ERROR
1656 ("EFAULT on pad, %d bytes\n",
1657 tex_width);
1655 return DRM_ERR(EFAULT); 1658 return DRM_ERR(EFAULT);
1656 } 1659 }
1657 } else if (tex_width == 32) { 1660 } else if (tex_width == 32) {
1658 if (DRM_COPY_FROM_USER(buffer, data, 16)) { 1661 if (DRM_COPY_FROM_USER
1659 DRM_ERROR("EFAULT on pad, %d bytes\n", 1662 (buffer, data, 16)) {
1660 tex_width); 1663 DRM_ERROR
1664 ("EFAULT on pad, %d bytes\n",
1665 tex_width);
1661 return DRM_ERR(EFAULT); 1666 return DRM_ERR(EFAULT);
1662 } 1667 }
1663 if (DRM_COPY_FROM_USER(buffer + 8, data + 16, 16)) { 1668 if (DRM_COPY_FROM_USER
1664 DRM_ERROR("EFAULT on pad, %d bytes\n", 1669 (buffer + 8, data + 16, 16)) {
1665 tex_width); 1670 DRM_ERROR
1671 ("EFAULT on pad, %d bytes\n",
1672 tex_width);
1666 return DRM_ERR(EFAULT); 1673 return DRM_ERR(EFAULT);
1667 } 1674 }
1668 } 1675 }
@@ -1675,9 +1682,11 @@ static int radeon_cp_dispatch_texture( DRMFILE filp,
1675 } 1682 }
1676 } else if (tex_width < 16) { 1683 } else if (tex_width < 16) {
1677 for (i = 0; i < tex->height; i++) { 1684 for (i = 0; i < tex->height; i++) {
1678 if (DRM_COPY_FROM_USER(buffer, data, tex_width)) { 1685 if (DRM_COPY_FROM_USER
1679 DRM_ERROR("EFAULT on pad, %d bytes\n", 1686 (buffer, data, tex_width)) {
1680 tex_width); 1687 DRM_ERROR
1688 ("EFAULT on pad, %d bytes\n",
1689 tex_width);
1681 return DRM_ERR(EFAULT); 1690 return DRM_ERR(EFAULT);
1682 } 1691 }
1683 buffer += 4; 1692 buffer += 4;
@@ -1687,35 +1696,42 @@ static int radeon_cp_dispatch_texture( DRMFILE filp,
1687 /* TODO: make sure this works when not fitting in one buffer 1696 /* TODO: make sure this works when not fitting in one buffer
1688 (i.e. 32bytes x 2048...) */ 1697 (i.e. 32bytes x 2048...) */
1689 for (i = 0; i < tex->height; i += 2) { 1698 for (i = 0; i < tex->height; i += 2) {
1690 if (DRM_COPY_FROM_USER(buffer, data, 16)) { 1699 if (DRM_COPY_FROM_USER
1691 DRM_ERROR("EFAULT on pad, %d bytes\n", 1700 (buffer, data, 16)) {
1692 tex_width); 1701 DRM_ERROR
1702 ("EFAULT on pad, %d bytes\n",
1703 tex_width);
1693 return DRM_ERR(EFAULT); 1704 return DRM_ERR(EFAULT);
1694 } 1705 }
1695 data += 16; 1706 data += 16;
1696 if (DRM_COPY_FROM_USER(buffer + 8, data, 16)) { 1707 if (DRM_COPY_FROM_USER
1697 DRM_ERROR("EFAULT on pad, %d bytes\n", 1708 (buffer + 8, data, 16)) {
1698 tex_width); 1709 DRM_ERROR
1710 ("EFAULT on pad, %d bytes\n",
1711 tex_width);
1699 return DRM_ERR(EFAULT); 1712 return DRM_ERR(EFAULT);
1700 } 1713 }
1701 data += 16; 1714 data += 16;
1702 if (DRM_COPY_FROM_USER(buffer + 4, data, 16)) { 1715 if (DRM_COPY_FROM_USER
1703 DRM_ERROR("EFAULT on pad, %d bytes\n", 1716 (buffer + 4, data, 16)) {
1704 tex_width); 1717 DRM_ERROR
1718 ("EFAULT on pad, %d bytes\n",
1719 tex_width);
1705 return DRM_ERR(EFAULT); 1720 return DRM_ERR(EFAULT);
1706 } 1721 }
1707 data += 16; 1722 data += 16;
1708 if (DRM_COPY_FROM_USER(buffer + 12, data, 16)) { 1723 if (DRM_COPY_FROM_USER
1709 DRM_ERROR("EFAULT on pad, %d bytes\n", 1724 (buffer + 12, data, 16)) {
1710 tex_width); 1725 DRM_ERROR
1726 ("EFAULT on pad, %d bytes\n",
1727 tex_width);
1711 return DRM_ERR(EFAULT); 1728 return DRM_ERR(EFAULT);
1712 } 1729 }
1713 data += 16; 1730 data += 16;
1714 buffer += 16; 1731 buffer += 16;
1715 } 1732 }
1716 } 1733 }
1717 } 1734 } else {
1718 else {
1719 if (tex_width >= 32) { 1735 if (tex_width >= 32) {
1720 /* Texture image width is larger than the minimum, so we 1736 /* Texture image width is larger than the minimum, so we
1721 * can upload it directly. 1737 * can upload it directly.
@@ -1731,9 +1747,12 @@ static int radeon_cp_dispatch_texture( DRMFILE filp,
1731 * need to pad out each image scanline to the minimum 1747 * need to pad out each image scanline to the minimum
1732 * width. 1748 * width.
1733 */ 1749 */
1734 for (i = 0 ; i < tex->height ; i++) { 1750 for (i = 0; i < tex->height; i++) {
1735 if (DRM_COPY_FROM_USER(buffer, data, tex_width )) { 1751 if (DRM_COPY_FROM_USER
1736 DRM_ERROR("EFAULT on pad, %d bytes\n", tex_width); 1752 (buffer, data, tex_width)) {
1753 DRM_ERROR
1754 ("EFAULT on pad, %d bytes\n",
1755 tex_width);
1737 return DRM_ERR(EFAULT); 1756 return DRM_ERR(EFAULT);
1738 } 1757 }
1739 buffer += 8; 1758 buffer += 8;
@@ -1754,8 +1773,7 @@ static int radeon_cp_dispatch_texture( DRMFILE filp,
1754 RADEON_GMC_SRC_DATATYPE_COLOR | 1773 RADEON_GMC_SRC_DATATYPE_COLOR |
1755 RADEON_ROP3_S | 1774 RADEON_ROP3_S |
1756 RADEON_DP_SRC_SOURCE_MEMORY | 1775 RADEON_DP_SRC_SOURCE_MEMORY |
1757 RADEON_GMC_CLR_CMP_CNTL_DIS | 1776 RADEON_GMC_CLR_CMP_CNTL_DIS | RADEON_GMC_WR_MSK_DIS);
1758 RADEON_GMC_WR_MSK_DIS );
1759 OUT_RING((spitch << 22) | (offset >> 10)); 1777 OUT_RING((spitch << 22) | (offset >> 10));
1760 OUT_RING((texpitch << 22) | (tex->offset >> 10)); 1778 OUT_RING((texpitch << 22) | (tex->offset >> 10));
1761 OUT_RING(0); 1779 OUT_RING(0);
@@ -1776,62 +1794,62 @@ static int radeon_cp_dispatch_texture( DRMFILE filp,
1776 * the texture data is written out to memory before rendering 1794 * the texture data is written out to memory before rendering
1777 * continues. 1795 * continues.
1778 */ 1796 */
1779 BEGIN_RING( 4 ); 1797 BEGIN_RING(4);
1780 RADEON_FLUSH_CACHE(); 1798 RADEON_FLUSH_CACHE();
1781 RADEON_WAIT_UNTIL_2D_IDLE(); 1799 RADEON_WAIT_UNTIL_2D_IDLE();
1782 ADVANCE_RING(); 1800 ADVANCE_RING();
1783 return 0; 1801 return 0;
1784} 1802}
1785 1803
1786 1804static void radeon_cp_dispatch_stipple(drm_device_t * dev, u32 * stipple)
1787static void radeon_cp_dispatch_stipple( drm_device_t *dev, u32 *stipple )
1788{ 1805{
1789 drm_radeon_private_t *dev_priv = dev->dev_private; 1806 drm_radeon_private_t *dev_priv = dev->dev_private;
1790 int i; 1807 int i;
1791 RING_LOCALS; 1808 RING_LOCALS;
1792 DRM_DEBUG( "\n" ); 1809 DRM_DEBUG("\n");
1793 1810
1794 BEGIN_RING( 35 ); 1811 BEGIN_RING(35);
1795 1812
1796 OUT_RING( CP_PACKET0( RADEON_RE_STIPPLE_ADDR, 0 ) ); 1813 OUT_RING(CP_PACKET0(RADEON_RE_STIPPLE_ADDR, 0));
1797 OUT_RING( 0x00000000 ); 1814 OUT_RING(0x00000000);
1798 1815
1799 OUT_RING( CP_PACKET0_TABLE( RADEON_RE_STIPPLE_DATA, 31 ) ); 1816 OUT_RING(CP_PACKET0_TABLE(RADEON_RE_STIPPLE_DATA, 31));
1800 for ( i = 0 ; i < 32 ; i++ ) { 1817 for (i = 0; i < 32; i++) {
1801 OUT_RING( stipple[i] ); 1818 OUT_RING(stipple[i]);
1802 } 1819 }
1803 1820
1804 ADVANCE_RING(); 1821 ADVANCE_RING();
1805} 1822}
1806 1823
1807static void radeon_apply_surface_regs(int surf_index, drm_radeon_private_t *dev_priv) 1824static void radeon_apply_surface_regs(int surf_index,
1825 drm_radeon_private_t * dev_priv)
1808{ 1826{
1809 if (!dev_priv->mmio) 1827 if (!dev_priv->mmio)
1810 return; 1828 return;
1811 1829
1812 radeon_do_cp_idle(dev_priv); 1830 radeon_do_cp_idle(dev_priv);
1813 1831
1814 RADEON_WRITE(RADEON_SURFACE0_INFO + 16*surf_index, 1832 RADEON_WRITE(RADEON_SURFACE0_INFO + 16 * surf_index,
1815 dev_priv->surfaces[surf_index].flags); 1833 dev_priv->surfaces[surf_index].flags);
1816 RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND + 16*surf_index, 1834 RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND + 16 * surf_index,
1817 dev_priv->surfaces[surf_index].lower); 1835 dev_priv->surfaces[surf_index].lower);
1818 RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND + 16*surf_index, 1836 RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND + 16 * surf_index,
1819 dev_priv->surfaces[surf_index].upper); 1837 dev_priv->surfaces[surf_index].upper);
1820} 1838}
1821 1839
1822
1823/* Allocates a virtual surface 1840/* Allocates a virtual surface
1824 * doesn't always allocate a real surface, will stretch an existing 1841 * doesn't always allocate a real surface, will stretch an existing
1825 * surface when possible. 1842 * surface when possible.
1826 * 1843 *
1827 * Note that refcount can be at most 2, since during a free refcount=3 1844 * Note that refcount can be at most 2, since during a free refcount=3
1828 * might mean we have to allocate a new surface which might not always 1845 * might mean we have to allocate a new surface which might not always
1829 * be available. 1846 * be available.
1830 * For example : we allocate three contigous surfaces ABC. If B is 1847 * For example : we allocate three contigous surfaces ABC. If B is
1831 * freed, we suddenly need two surfaces to store A and C, which might 1848 * freed, we suddenly need two surfaces to store A and C, which might
1832 * not always be available. 1849 * not always be available.
1833 */ 1850 */
1834static int alloc_surface(drm_radeon_surface_alloc_t* new, drm_radeon_private_t *dev_priv, DRMFILE filp) 1851static int alloc_surface(drm_radeon_surface_alloc_t * new,
1852 drm_radeon_private_t * dev_priv, DRMFILE filp)
1835{ 1853{
1836 struct radeon_virt_surface *s; 1854 struct radeon_virt_surface *s;
1837 int i; 1855 int i;
@@ -1843,34 +1861,37 @@ static int alloc_surface(drm_radeon_surface_alloc_t* new, drm_radeon_private_t *
1843 1861
1844 /* sanity check */ 1862 /* sanity check */
1845 if ((new_lower >= new_upper) || (new->flags == 0) || (new->size == 0) || 1863 if ((new_lower >= new_upper) || (new->flags == 0) || (new->size == 0) ||
1846 ((new_upper & RADEON_SURF_ADDRESS_FIXED_MASK) != RADEON_SURF_ADDRESS_FIXED_MASK) || 1864 ((new_upper & RADEON_SURF_ADDRESS_FIXED_MASK) !=
1847 ((new_lower & RADEON_SURF_ADDRESS_FIXED_MASK) != 0)) 1865 RADEON_SURF_ADDRESS_FIXED_MASK)
1866 || ((new_lower & RADEON_SURF_ADDRESS_FIXED_MASK) != 0))
1848 return -1; 1867 return -1;
1849 1868
1850 /* make sure there is no overlap with existing surfaces */ 1869 /* make sure there is no overlap with existing surfaces */
1851 for (i = 0; i < RADEON_MAX_SURFACES; i++) { 1870 for (i = 0; i < RADEON_MAX_SURFACES; i++) {
1852 if ((dev_priv->surfaces[i].refcount != 0) && 1871 if ((dev_priv->surfaces[i].refcount != 0) &&
1853 (( (new_lower >= dev_priv->surfaces[i].lower) && 1872 (((new_lower >= dev_priv->surfaces[i].lower) &&
1854 (new_lower < dev_priv->surfaces[i].upper) ) || 1873 (new_lower < dev_priv->surfaces[i].upper)) ||
1855 ( (new_lower < dev_priv->surfaces[i].lower) && 1874 ((new_lower < dev_priv->surfaces[i].lower) &&
1856 (new_upper > dev_priv->surfaces[i].lower) )) ){ 1875 (new_upper > dev_priv->surfaces[i].lower)))) {
1857 return -1;} 1876 return -1;
1877 }
1858 } 1878 }
1859 1879
1860 /* find a virtual surface */ 1880 /* find a virtual surface */
1861 for (i = 0; i < 2*RADEON_MAX_SURFACES; i++) 1881 for (i = 0; i < 2 * RADEON_MAX_SURFACES; i++)
1862 if (dev_priv->virt_surfaces[i].filp == 0) 1882 if (dev_priv->virt_surfaces[i].filp == 0)
1863 break; 1883 break;
1864 if (i == 2*RADEON_MAX_SURFACES) { 1884 if (i == 2 * RADEON_MAX_SURFACES) {
1865 return -1;} 1885 return -1;
1886 }
1866 virt_surface_index = i; 1887 virt_surface_index = i;
1867 1888
1868 /* try to reuse an existing surface */ 1889 /* try to reuse an existing surface */
1869 for (i = 0; i < RADEON_MAX_SURFACES; i++) { 1890 for (i = 0; i < RADEON_MAX_SURFACES; i++) {
1870 /* extend before */ 1891 /* extend before */
1871 if ((dev_priv->surfaces[i].refcount == 1) && 1892 if ((dev_priv->surfaces[i].refcount == 1) &&
1872 (new->flags == dev_priv->surfaces[i].flags) && 1893 (new->flags == dev_priv->surfaces[i].flags) &&
1873 (new_upper + 1 == dev_priv->surfaces[i].lower)) { 1894 (new_upper + 1 == dev_priv->surfaces[i].lower)) {
1874 s = &(dev_priv->virt_surfaces[virt_surface_index]); 1895 s = &(dev_priv->virt_surfaces[virt_surface_index]);
1875 s->surface_index = i; 1896 s->surface_index = i;
1876 s->lower = new_lower; 1897 s->lower = new_lower;
@@ -1885,8 +1906,8 @@ static int alloc_surface(drm_radeon_surface_alloc_t* new, drm_radeon_private_t *
1885 1906
1886 /* extend after */ 1907 /* extend after */
1887 if ((dev_priv->surfaces[i].refcount == 1) && 1908 if ((dev_priv->surfaces[i].refcount == 1) &&
1888 (new->flags == dev_priv->surfaces[i].flags) && 1909 (new->flags == dev_priv->surfaces[i].flags) &&
1889 (new_lower == dev_priv->surfaces[i].upper + 1)) { 1910 (new_lower == dev_priv->surfaces[i].upper + 1)) {
1890 s = &(dev_priv->virt_surfaces[virt_surface_index]); 1911 s = &(dev_priv->virt_surfaces[virt_surface_index]);
1891 s->surface_index = i; 1912 s->surface_index = i;
1892 s->lower = new_lower; 1913 s->lower = new_lower;
@@ -1922,26 +1943,34 @@ static int alloc_surface(drm_radeon_surface_alloc_t* new, drm_radeon_private_t *
1922 return -1; 1943 return -1;
1923} 1944}
1924 1945
1925static int free_surface(DRMFILE filp, drm_radeon_private_t *dev_priv, int lower) 1946static int free_surface(DRMFILE filp, drm_radeon_private_t * dev_priv,
1947 int lower)
1926{ 1948{
1927 struct radeon_virt_surface *s; 1949 struct radeon_virt_surface *s;
1928 int i; 1950 int i;
1929 /* find the virtual surface */ 1951 /* find the virtual surface */
1930 for(i = 0; i < 2*RADEON_MAX_SURFACES; i++) { 1952 for (i = 0; i < 2 * RADEON_MAX_SURFACES; i++) {
1931 s = &(dev_priv->virt_surfaces[i]); 1953 s = &(dev_priv->virt_surfaces[i]);
1932 if (s->filp) { 1954 if (s->filp) {
1933 if ((lower == s->lower) && (filp == s->filp)) { 1955 if ((lower == s->lower) && (filp == s->filp)) {
1934 if (dev_priv->surfaces[s->surface_index].lower == s->lower) 1956 if (dev_priv->surfaces[s->surface_index].
1935 dev_priv->surfaces[s->surface_index].lower = s->upper; 1957 lower == s->lower)
1958 dev_priv->surfaces[s->surface_index].
1959 lower = s->upper;
1936 1960
1937 if (dev_priv->surfaces[s->surface_index].upper == s->upper) 1961 if (dev_priv->surfaces[s->surface_index].
1938 dev_priv->surfaces[s->surface_index].upper = s->lower; 1962 upper == s->upper)
1963 dev_priv->surfaces[s->surface_index].
1964 upper = s->lower;
1939 1965
1940 dev_priv->surfaces[s->surface_index].refcount--; 1966 dev_priv->surfaces[s->surface_index].refcount--;
1941 if (dev_priv->surfaces[s->surface_index].refcount == 0) 1967 if (dev_priv->surfaces[s->surface_index].
1942 dev_priv->surfaces[s->surface_index].flags = 0; 1968 refcount == 0)
1969 dev_priv->surfaces[s->surface_index].
1970 flags = 0;
1943 s->filp = NULL; 1971 s->filp = NULL;
1944 radeon_apply_surface_regs(s->surface_index, dev_priv); 1972 radeon_apply_surface_regs(s->surface_index,
1973 dev_priv);
1945 return 0; 1974 return 0;
1946 } 1975 }
1947 } 1976 }
@@ -1949,13 +1978,14 @@ static int free_surface(DRMFILE filp, drm_radeon_private_t *dev_priv, int lower)
1949 return 1; 1978 return 1;
1950} 1979}
1951 1980
1952static void radeon_surfaces_release(DRMFILE filp, drm_radeon_private_t *dev_priv) 1981static void radeon_surfaces_release(DRMFILE filp,
1982 drm_radeon_private_t * dev_priv)
1953{ 1983{
1954 int i; 1984 int i;
1955 for( i = 0; i < 2*RADEON_MAX_SURFACES; i++) 1985 for (i = 0; i < 2 * RADEON_MAX_SURFACES; i++) {
1956 {
1957 if (dev_priv->virt_surfaces[i].filp == filp) 1986 if (dev_priv->virt_surfaces[i].filp == filp)
1958 free_surface(filp, dev_priv, dev_priv->virt_surfaces[i].lower); 1987 free_surface(filp, dev_priv,
1988 dev_priv->virt_surfaces[i].lower);
1959 } 1989 }
1960} 1990}
1961 1991
@@ -1969,12 +1999,13 @@ static int radeon_surface_alloc(DRM_IOCTL_ARGS)
1969 drm_radeon_surface_alloc_t alloc; 1999 drm_radeon_surface_alloc_t alloc;
1970 2000
1971 if (!dev_priv) { 2001 if (!dev_priv) {
1972 DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ); 2002 DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
1973 return DRM_ERR(EINVAL); 2003 return DRM_ERR(EINVAL);
1974 } 2004 }
1975 2005
1976 DRM_COPY_FROM_USER_IOCTL(alloc, (drm_radeon_surface_alloc_t __user *)data, 2006 DRM_COPY_FROM_USER_IOCTL(alloc,
1977 sizeof(alloc)); 2007 (drm_radeon_surface_alloc_t __user *) data,
2008 sizeof(alloc));
1978 2009
1979 if (alloc_surface(&alloc, dev_priv, filp) == -1) 2010 if (alloc_surface(&alloc, dev_priv, filp) == -1)
1980 return DRM_ERR(EINVAL); 2011 return DRM_ERR(EINVAL);
@@ -1989,12 +2020,12 @@ static int radeon_surface_free(DRM_IOCTL_ARGS)
1989 drm_radeon_surface_free_t memfree; 2020 drm_radeon_surface_free_t memfree;
1990 2021
1991 if (!dev_priv) { 2022 if (!dev_priv) {
1992 DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ); 2023 DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
1993 return DRM_ERR(EINVAL); 2024 return DRM_ERR(EINVAL);
1994 } 2025 }
1995 2026
1996 DRM_COPY_FROM_USER_IOCTL(memfree, (drm_radeon_mem_free_t __user *)data, 2027 DRM_COPY_FROM_USER_IOCTL(memfree, (drm_radeon_mem_free_t __user *) data,
1997 sizeof(memfree) ); 2028 sizeof(memfree));
1998 2029
1999 if (free_surface(filp, dev_priv, memfree.address)) 2030 if (free_surface(filp, dev_priv, memfree.address))
2000 return DRM_ERR(EINVAL); 2031 return DRM_ERR(EINVAL);
@@ -2002,51 +2033,52 @@ static int radeon_surface_free(DRM_IOCTL_ARGS)
2002 return 0; 2033 return 0;
2003} 2034}
2004 2035
2005static int radeon_cp_clear( DRM_IOCTL_ARGS ) 2036static int radeon_cp_clear(DRM_IOCTL_ARGS)
2006{ 2037{
2007 DRM_DEVICE; 2038 DRM_DEVICE;
2008 drm_radeon_private_t *dev_priv = dev->dev_private; 2039 drm_radeon_private_t *dev_priv = dev->dev_private;
2009 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; 2040 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
2010 drm_radeon_clear_t clear; 2041 drm_radeon_clear_t clear;
2011 drm_radeon_clear_rect_t depth_boxes[RADEON_NR_SAREA_CLIPRECTS]; 2042 drm_radeon_clear_rect_t depth_boxes[RADEON_NR_SAREA_CLIPRECTS];
2012 DRM_DEBUG( "\n" ); 2043 DRM_DEBUG("\n");
2013 2044
2014 LOCK_TEST_WITH_RETURN( dev, filp ); 2045 LOCK_TEST_WITH_RETURN(dev, filp);
2015 2046
2016 DRM_COPY_FROM_USER_IOCTL( clear, (drm_radeon_clear_t __user *)data, 2047 DRM_COPY_FROM_USER_IOCTL(clear, (drm_radeon_clear_t __user *) data,
2017 sizeof(clear) ); 2048 sizeof(clear));
2018 2049
2019 RING_SPACE_TEST_WITH_RETURN( dev_priv ); 2050 RING_SPACE_TEST_WITH_RETURN(dev_priv);
2020 2051
2021 if ( sarea_priv->nbox > RADEON_NR_SAREA_CLIPRECTS ) 2052 if (sarea_priv->nbox > RADEON_NR_SAREA_CLIPRECTS)
2022 sarea_priv->nbox = RADEON_NR_SAREA_CLIPRECTS; 2053 sarea_priv->nbox = RADEON_NR_SAREA_CLIPRECTS;
2023 2054
2024 if ( DRM_COPY_FROM_USER( &depth_boxes, clear.depth_boxes, 2055 if (DRM_COPY_FROM_USER(&depth_boxes, clear.depth_boxes,
2025 sarea_priv->nbox * sizeof(depth_boxes[0]) ) ) 2056 sarea_priv->nbox * sizeof(depth_boxes[0])))
2026 return DRM_ERR(EFAULT); 2057 return DRM_ERR(EFAULT);
2027 2058
2028 radeon_cp_dispatch_clear( dev, &clear, depth_boxes ); 2059 radeon_cp_dispatch_clear(dev, &clear, depth_boxes);
2029 2060
2030 COMMIT_RING(); 2061 COMMIT_RING();
2031 return 0; 2062 return 0;
2032} 2063}
2033 2064
2034
2035/* Not sure why this isn't set all the time: 2065/* Not sure why this isn't set all the time:
2036 */ 2066 */
2037static int radeon_do_init_pageflip( drm_device_t *dev ) 2067static int radeon_do_init_pageflip(drm_device_t * dev)
2038{ 2068{
2039 drm_radeon_private_t *dev_priv = dev->dev_private; 2069 drm_radeon_private_t *dev_priv = dev->dev_private;
2040 RING_LOCALS; 2070 RING_LOCALS;
2041 2071
2042 DRM_DEBUG( "\n" ); 2072 DRM_DEBUG("\n");
2043 2073
2044 BEGIN_RING( 6 ); 2074 BEGIN_RING(6);
2045 RADEON_WAIT_UNTIL_3D_IDLE(); 2075 RADEON_WAIT_UNTIL_3D_IDLE();
2046 OUT_RING( CP_PACKET0( RADEON_CRTC_OFFSET_CNTL, 0 ) ); 2076 OUT_RING(CP_PACKET0(RADEON_CRTC_OFFSET_CNTL, 0));
2047 OUT_RING( RADEON_READ( RADEON_CRTC_OFFSET_CNTL ) | RADEON_CRTC_OFFSET_FLIP_CNTL ); 2077 OUT_RING(RADEON_READ(RADEON_CRTC_OFFSET_CNTL) |
2048 OUT_RING( CP_PACKET0( RADEON_CRTC2_OFFSET_CNTL, 0 ) ); 2078 RADEON_CRTC_OFFSET_FLIP_CNTL);
2049 OUT_RING( RADEON_READ( RADEON_CRTC2_OFFSET_CNTL ) | RADEON_CRTC_OFFSET_FLIP_CNTL ); 2079 OUT_RING(CP_PACKET0(RADEON_CRTC2_OFFSET_CNTL, 0));
2080 OUT_RING(RADEON_READ(RADEON_CRTC2_OFFSET_CNTL) |
2081 RADEON_CRTC_OFFSET_FLIP_CNTL);
2050 ADVANCE_RING(); 2082 ADVANCE_RING();
2051 2083
2052 dev_priv->page_flipping = 1; 2084 dev_priv->page_flipping = 1;
@@ -2059,62 +2091,62 @@ static int radeon_do_init_pageflip( drm_device_t *dev )
2059/* Called whenever a client dies, from drm_release. 2091/* Called whenever a client dies, from drm_release.
2060 * NOTE: Lock isn't necessarily held when this is called! 2092 * NOTE: Lock isn't necessarily held when this is called!
2061 */ 2093 */
2062static int radeon_do_cleanup_pageflip( drm_device_t *dev ) 2094static int radeon_do_cleanup_pageflip(drm_device_t * dev)
2063{ 2095{
2064 drm_radeon_private_t *dev_priv = dev->dev_private; 2096 drm_radeon_private_t *dev_priv = dev->dev_private;
2065 DRM_DEBUG( "\n" ); 2097 DRM_DEBUG("\n");
2066 2098
2067 if (dev_priv->current_page != 0) 2099 if (dev_priv->current_page != 0)
2068 radeon_cp_dispatch_flip( dev ); 2100 radeon_cp_dispatch_flip(dev);
2069 2101
2070 dev_priv->page_flipping = 0; 2102 dev_priv->page_flipping = 0;
2071 return 0; 2103 return 0;
2072} 2104}
2073 2105
2074/* Swapping and flipping are different operations, need different ioctls. 2106/* Swapping and flipping are different operations, need different ioctls.
2075 * They can & should be intermixed to support multiple 3d windows. 2107 * They can & should be intermixed to support multiple 3d windows.
2076 */ 2108 */
2077static int radeon_cp_flip( DRM_IOCTL_ARGS ) 2109static int radeon_cp_flip(DRM_IOCTL_ARGS)
2078{ 2110{
2079 DRM_DEVICE; 2111 DRM_DEVICE;
2080 drm_radeon_private_t *dev_priv = dev->dev_private; 2112 drm_radeon_private_t *dev_priv = dev->dev_private;
2081 DRM_DEBUG( "\n" ); 2113 DRM_DEBUG("\n");
2114
2115 LOCK_TEST_WITH_RETURN(dev, filp);
2082 2116
2083 LOCK_TEST_WITH_RETURN( dev, filp ); 2117 RING_SPACE_TEST_WITH_RETURN(dev_priv);
2084 2118
2085 RING_SPACE_TEST_WITH_RETURN( dev_priv ); 2119 if (!dev_priv->page_flipping)
2120 radeon_do_init_pageflip(dev);
2086 2121
2087 if (!dev_priv->page_flipping) 2122 radeon_cp_dispatch_flip(dev);
2088 radeon_do_init_pageflip( dev );
2089
2090 radeon_cp_dispatch_flip( dev );
2091 2123
2092 COMMIT_RING(); 2124 COMMIT_RING();
2093 return 0; 2125 return 0;
2094} 2126}
2095 2127
2096static int radeon_cp_swap( DRM_IOCTL_ARGS ) 2128static int radeon_cp_swap(DRM_IOCTL_ARGS)
2097{ 2129{
2098 DRM_DEVICE; 2130 DRM_DEVICE;
2099 drm_radeon_private_t *dev_priv = dev->dev_private; 2131 drm_radeon_private_t *dev_priv = dev->dev_private;
2100 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; 2132 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
2101 DRM_DEBUG( "\n" ); 2133 DRM_DEBUG("\n");
2102 2134
2103 LOCK_TEST_WITH_RETURN( dev, filp ); 2135 LOCK_TEST_WITH_RETURN(dev, filp);
2104 2136
2105 RING_SPACE_TEST_WITH_RETURN( dev_priv ); 2137 RING_SPACE_TEST_WITH_RETURN(dev_priv);
2106 2138
2107 if ( sarea_priv->nbox > RADEON_NR_SAREA_CLIPRECTS ) 2139 if (sarea_priv->nbox > RADEON_NR_SAREA_CLIPRECTS)
2108 sarea_priv->nbox = RADEON_NR_SAREA_CLIPRECTS; 2140 sarea_priv->nbox = RADEON_NR_SAREA_CLIPRECTS;
2109 2141
2110 radeon_cp_dispatch_swap( dev ); 2142 radeon_cp_dispatch_swap(dev);
2111 dev_priv->sarea_priv->ctx_owner = 0; 2143 dev_priv->sarea_priv->ctx_owner = 0;
2112 2144
2113 COMMIT_RING(); 2145 COMMIT_RING();
2114 return 0; 2146 return 0;
2115} 2147}
2116 2148
2117static int radeon_cp_vertex( DRM_IOCTL_ARGS ) 2149static int radeon_cp_vertex(DRM_IOCTL_ARGS)
2118{ 2150{
2119 DRM_DEVICE; 2151 DRM_DEVICE;
2120 drm_radeon_private_t *dev_priv = dev->dev_private; 2152 drm_radeon_private_t *dev_priv = dev->dev_private;
@@ -2125,55 +2157,53 @@ static int radeon_cp_vertex( DRM_IOCTL_ARGS )
2125 drm_radeon_vertex_t vertex; 2157 drm_radeon_vertex_t vertex;
2126 drm_radeon_tcl_prim_t prim; 2158 drm_radeon_tcl_prim_t prim;
2127 2159
2128 LOCK_TEST_WITH_RETURN( dev, filp ); 2160 LOCK_TEST_WITH_RETURN(dev, filp);
2129 2161
2130 DRM_GET_PRIV_WITH_RETURN( filp_priv, filp ); 2162 DRM_GET_PRIV_WITH_RETURN(filp_priv, filp);
2131 2163
2132 DRM_COPY_FROM_USER_IOCTL( vertex, (drm_radeon_vertex_t __user *)data, 2164 DRM_COPY_FROM_USER_IOCTL(vertex, (drm_radeon_vertex_t __user *) data,
2133 sizeof(vertex) ); 2165 sizeof(vertex));
2134 2166
2135 DRM_DEBUG( "pid=%d index=%d count=%d discard=%d\n", 2167 DRM_DEBUG("pid=%d index=%d count=%d discard=%d\n",
2136 DRM_CURRENTPID, 2168 DRM_CURRENTPID, vertex.idx, vertex.count, vertex.discard);
2137 vertex.idx, vertex.count, vertex.discard );
2138 2169
2139 if ( vertex.idx < 0 || vertex.idx >= dma->buf_count ) { 2170 if (vertex.idx < 0 || vertex.idx >= dma->buf_count) {
2140 DRM_ERROR( "buffer index %d (of %d max)\n", 2171 DRM_ERROR("buffer index %d (of %d max)\n",
2141 vertex.idx, dma->buf_count - 1 ); 2172 vertex.idx, dma->buf_count - 1);
2142 return DRM_ERR(EINVAL); 2173 return DRM_ERR(EINVAL);
2143 } 2174 }
2144 if ( vertex.prim < 0 || 2175 if (vertex.prim < 0 || vertex.prim > RADEON_PRIM_TYPE_3VRT_LINE_LIST) {
2145 vertex.prim > RADEON_PRIM_TYPE_3VRT_LINE_LIST ) { 2176 DRM_ERROR("buffer prim %d\n", vertex.prim);
2146 DRM_ERROR( "buffer prim %d\n", vertex.prim );
2147 return DRM_ERR(EINVAL); 2177 return DRM_ERR(EINVAL);
2148 } 2178 }
2149 2179
2150 RING_SPACE_TEST_WITH_RETURN( dev_priv ); 2180 RING_SPACE_TEST_WITH_RETURN(dev_priv);
2151 VB_AGE_TEST_WITH_RETURN( dev_priv ); 2181 VB_AGE_TEST_WITH_RETURN(dev_priv);
2152 2182
2153 buf = dma->buflist[vertex.idx]; 2183 buf = dma->buflist[vertex.idx];
2154 2184
2155 if ( buf->filp != filp ) { 2185 if (buf->filp != filp) {
2156 DRM_ERROR( "process %d using buffer owned by %p\n", 2186 DRM_ERROR("process %d using buffer owned by %p\n",
2157 DRM_CURRENTPID, buf->filp ); 2187 DRM_CURRENTPID, buf->filp);
2158 return DRM_ERR(EINVAL); 2188 return DRM_ERR(EINVAL);
2159 } 2189 }
2160 if ( buf->pending ) { 2190 if (buf->pending) {
2161 DRM_ERROR( "sending pending buffer %d\n", vertex.idx ); 2191 DRM_ERROR("sending pending buffer %d\n", vertex.idx);
2162 return DRM_ERR(EINVAL); 2192 return DRM_ERR(EINVAL);
2163 } 2193 }
2164 2194
2165 /* Build up a prim_t record: 2195 /* Build up a prim_t record:
2166 */ 2196 */
2167 if (vertex.count) { 2197 if (vertex.count) {
2168 buf->used = vertex.count; /* not used? */ 2198 buf->used = vertex.count; /* not used? */
2169 2199
2170 if ( sarea_priv->dirty & ~RADEON_UPLOAD_CLIPRECTS ) { 2200 if (sarea_priv->dirty & ~RADEON_UPLOAD_CLIPRECTS) {
2171 if ( radeon_emit_state( dev_priv, filp_priv, 2201 if (radeon_emit_state(dev_priv, filp_priv,
2172 &sarea_priv->context_state, 2202 &sarea_priv->context_state,
2173 sarea_priv->tex_state, 2203 sarea_priv->tex_state,
2174 sarea_priv->dirty ) ) { 2204 sarea_priv->dirty)) {
2175 DRM_ERROR( "radeon_emit_state failed\n" ); 2205 DRM_ERROR("radeon_emit_state failed\n");
2176 return DRM_ERR( EINVAL ); 2206 return DRM_ERR(EINVAL);
2177 } 2207 }
2178 2208
2179 sarea_priv->dirty &= ~(RADEON_UPLOAD_TEX0IMAGES | 2209 sarea_priv->dirty &= ~(RADEON_UPLOAD_TEX0IMAGES |
@@ -2183,23 +2213,23 @@ static int radeon_cp_vertex( DRM_IOCTL_ARGS )
2183 } 2213 }
2184 2214
2185 prim.start = 0; 2215 prim.start = 0;
2186 prim.finish = vertex.count; /* unused */ 2216 prim.finish = vertex.count; /* unused */
2187 prim.prim = vertex.prim; 2217 prim.prim = vertex.prim;
2188 prim.numverts = vertex.count; 2218 prim.numverts = vertex.count;
2189 prim.vc_format = dev_priv->sarea_priv->vc_format; 2219 prim.vc_format = dev_priv->sarea_priv->vc_format;
2190 2220
2191 radeon_cp_dispatch_vertex( dev, buf, &prim ); 2221 radeon_cp_dispatch_vertex(dev, buf, &prim);
2192 } 2222 }
2193 2223
2194 if (vertex.discard) { 2224 if (vertex.discard) {
2195 radeon_cp_discard_buffer( dev, buf ); 2225 radeon_cp_discard_buffer(dev, buf);
2196 } 2226 }
2197 2227
2198 COMMIT_RING(); 2228 COMMIT_RING();
2199 return 0; 2229 return 0;
2200} 2230}
2201 2231
2202static int radeon_cp_indices( DRM_IOCTL_ARGS ) 2232static int radeon_cp_indices(DRM_IOCTL_ARGS)
2203{ 2233{
2204 DRM_DEVICE; 2234 DRM_DEVICE;
2205 drm_radeon_private_t *dev_priv = dev->dev_private; 2235 drm_radeon_private_t *dev_priv = dev->dev_private;
@@ -2211,69 +2241,67 @@ static int radeon_cp_indices( DRM_IOCTL_ARGS )
2211 drm_radeon_tcl_prim_t prim; 2241 drm_radeon_tcl_prim_t prim;
2212 int count; 2242 int count;
2213 2243
2214 LOCK_TEST_WITH_RETURN( dev, filp ); 2244 LOCK_TEST_WITH_RETURN(dev, filp);
2215 2245
2216 if ( !dev_priv ) { 2246 if (!dev_priv) {
2217 DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ); 2247 DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
2218 return DRM_ERR(EINVAL); 2248 return DRM_ERR(EINVAL);
2219 } 2249 }
2220 2250
2221 DRM_GET_PRIV_WITH_RETURN( filp_priv, filp ); 2251 DRM_GET_PRIV_WITH_RETURN(filp_priv, filp);
2222 2252
2223 DRM_COPY_FROM_USER_IOCTL( elts, (drm_radeon_indices_t __user *)data, 2253 DRM_COPY_FROM_USER_IOCTL(elts, (drm_radeon_indices_t __user *) data,
2224 sizeof(elts) ); 2254 sizeof(elts));
2225 2255
2226 DRM_DEBUG( "pid=%d index=%d start=%d end=%d discard=%d\n", 2256 DRM_DEBUG("pid=%d index=%d start=%d end=%d discard=%d\n",
2227 DRM_CURRENTPID, 2257 DRM_CURRENTPID, elts.idx, elts.start, elts.end, elts.discard);
2228 elts.idx, elts.start, elts.end, elts.discard );
2229 2258
2230 if ( elts.idx < 0 || elts.idx >= dma->buf_count ) { 2259 if (elts.idx < 0 || elts.idx >= dma->buf_count) {
2231 DRM_ERROR( "buffer index %d (of %d max)\n", 2260 DRM_ERROR("buffer index %d (of %d max)\n",
2232 elts.idx, dma->buf_count - 1 ); 2261 elts.idx, dma->buf_count - 1);
2233 return DRM_ERR(EINVAL); 2262 return DRM_ERR(EINVAL);
2234 } 2263 }
2235 if ( elts.prim < 0 || 2264 if (elts.prim < 0 || elts.prim > RADEON_PRIM_TYPE_3VRT_LINE_LIST) {
2236 elts.prim > RADEON_PRIM_TYPE_3VRT_LINE_LIST ) { 2265 DRM_ERROR("buffer prim %d\n", elts.prim);
2237 DRM_ERROR( "buffer prim %d\n", elts.prim );
2238 return DRM_ERR(EINVAL); 2266 return DRM_ERR(EINVAL);
2239 } 2267 }
2240 2268
2241 RING_SPACE_TEST_WITH_RETURN( dev_priv ); 2269 RING_SPACE_TEST_WITH_RETURN(dev_priv);
2242 VB_AGE_TEST_WITH_RETURN( dev_priv ); 2270 VB_AGE_TEST_WITH_RETURN(dev_priv);
2243 2271
2244 buf = dma->buflist[elts.idx]; 2272 buf = dma->buflist[elts.idx];
2245 2273
2246 if ( buf->filp != filp ) { 2274 if (buf->filp != filp) {
2247 DRM_ERROR( "process %d using buffer owned by %p\n", 2275 DRM_ERROR("process %d using buffer owned by %p\n",
2248 DRM_CURRENTPID, buf->filp ); 2276 DRM_CURRENTPID, buf->filp);
2249 return DRM_ERR(EINVAL); 2277 return DRM_ERR(EINVAL);
2250 } 2278 }
2251 if ( buf->pending ) { 2279 if (buf->pending) {
2252 DRM_ERROR( "sending pending buffer %d\n", elts.idx ); 2280 DRM_ERROR("sending pending buffer %d\n", elts.idx);
2253 return DRM_ERR(EINVAL); 2281 return DRM_ERR(EINVAL);
2254 } 2282 }
2255 2283
2256 count = (elts.end - elts.start) / sizeof(u16); 2284 count = (elts.end - elts.start) / sizeof(u16);
2257 elts.start -= RADEON_INDEX_PRIM_OFFSET; 2285 elts.start -= RADEON_INDEX_PRIM_OFFSET;
2258 2286
2259 if ( elts.start & 0x7 ) { 2287 if (elts.start & 0x7) {
2260 DRM_ERROR( "misaligned buffer 0x%x\n", elts.start ); 2288 DRM_ERROR("misaligned buffer 0x%x\n", elts.start);
2261 return DRM_ERR(EINVAL); 2289 return DRM_ERR(EINVAL);
2262 } 2290 }
2263 if ( elts.start < buf->used ) { 2291 if (elts.start < buf->used) {
2264 DRM_ERROR( "no header 0x%x - 0x%x\n", elts.start, buf->used ); 2292 DRM_ERROR("no header 0x%x - 0x%x\n", elts.start, buf->used);
2265 return DRM_ERR(EINVAL); 2293 return DRM_ERR(EINVAL);
2266 } 2294 }
2267 2295
2268 buf->used = elts.end; 2296 buf->used = elts.end;
2269 2297
2270 if ( sarea_priv->dirty & ~RADEON_UPLOAD_CLIPRECTS ) { 2298 if (sarea_priv->dirty & ~RADEON_UPLOAD_CLIPRECTS) {
2271 if ( radeon_emit_state( dev_priv, filp_priv, 2299 if (radeon_emit_state(dev_priv, filp_priv,
2272 &sarea_priv->context_state, 2300 &sarea_priv->context_state,
2273 sarea_priv->tex_state, 2301 sarea_priv->tex_state,
2274 sarea_priv->dirty ) ) { 2302 sarea_priv->dirty)) {
2275 DRM_ERROR( "radeon_emit_state failed\n" ); 2303 DRM_ERROR("radeon_emit_state failed\n");
2276 return DRM_ERR( EINVAL ); 2304 return DRM_ERR(EINVAL);
2277 } 2305 }
2278 2306
2279 sarea_priv->dirty &= ~(RADEON_UPLOAD_TEX0IMAGES | 2307 sarea_priv->dirty &= ~(RADEON_UPLOAD_TEX0IMAGES |
@@ -2282,26 +2310,25 @@ static int radeon_cp_indices( DRM_IOCTL_ARGS )
2282 RADEON_REQUIRE_QUIESCENCE); 2310 RADEON_REQUIRE_QUIESCENCE);
2283 } 2311 }
2284 2312
2285
2286 /* Build up a prim_t record: 2313 /* Build up a prim_t record:
2287 */ 2314 */
2288 prim.start = elts.start; 2315 prim.start = elts.start;
2289 prim.finish = elts.end; 2316 prim.finish = elts.end;
2290 prim.prim = elts.prim; 2317 prim.prim = elts.prim;
2291 prim.offset = 0; /* offset from start of dma buffers */ 2318 prim.offset = 0; /* offset from start of dma buffers */
2292 prim.numverts = RADEON_MAX_VB_VERTS; /* duh */ 2319 prim.numverts = RADEON_MAX_VB_VERTS; /* duh */
2293 prim.vc_format = dev_priv->sarea_priv->vc_format; 2320 prim.vc_format = dev_priv->sarea_priv->vc_format;
2294 2321
2295 radeon_cp_dispatch_indices( dev, buf, &prim ); 2322 radeon_cp_dispatch_indices(dev, buf, &prim);
2296 if (elts.discard) { 2323 if (elts.discard) {
2297 radeon_cp_discard_buffer( dev, buf ); 2324 radeon_cp_discard_buffer(dev, buf);
2298 } 2325 }
2299 2326
2300 COMMIT_RING(); 2327 COMMIT_RING();
2301 return 0; 2328 return 0;
2302} 2329}
2303 2330
2304static int radeon_cp_texture( DRM_IOCTL_ARGS ) 2331static int radeon_cp_texture(DRM_IOCTL_ARGS)
2305{ 2332{
2306 DRM_DEVICE; 2333 DRM_DEVICE;
2307 drm_radeon_private_t *dev_priv = dev->dev_private; 2334 drm_radeon_private_t *dev_priv = dev->dev_private;
@@ -2309,53 +2336,54 @@ static int radeon_cp_texture( DRM_IOCTL_ARGS )
2309 drm_radeon_tex_image_t image; 2336 drm_radeon_tex_image_t image;
2310 int ret; 2337 int ret;
2311 2338
2312 LOCK_TEST_WITH_RETURN( dev, filp ); 2339 LOCK_TEST_WITH_RETURN(dev, filp);
2313 2340
2314 DRM_COPY_FROM_USER_IOCTL( tex, (drm_radeon_texture_t __user *)data, sizeof(tex) ); 2341 DRM_COPY_FROM_USER_IOCTL(tex, (drm_radeon_texture_t __user *) data,
2342 sizeof(tex));
2315 2343
2316 if ( tex.image == NULL ) { 2344 if (tex.image == NULL) {
2317 DRM_ERROR( "null texture image!\n" ); 2345 DRM_ERROR("null texture image!\n");
2318 return DRM_ERR(EINVAL); 2346 return DRM_ERR(EINVAL);
2319 } 2347 }
2320 2348
2321 if ( DRM_COPY_FROM_USER( &image, 2349 if (DRM_COPY_FROM_USER(&image,
2322 (drm_radeon_tex_image_t __user *)tex.image, 2350 (drm_radeon_tex_image_t __user *) tex.image,
2323 sizeof(image) ) ) 2351 sizeof(image)))
2324 return DRM_ERR(EFAULT); 2352 return DRM_ERR(EFAULT);
2325 2353
2326 RING_SPACE_TEST_WITH_RETURN( dev_priv ); 2354 RING_SPACE_TEST_WITH_RETURN(dev_priv);
2327 VB_AGE_TEST_WITH_RETURN( dev_priv ); 2355 VB_AGE_TEST_WITH_RETURN(dev_priv);
2328 2356
2329 ret = radeon_cp_dispatch_texture( filp, dev, &tex, &image ); 2357 ret = radeon_cp_dispatch_texture(filp, dev, &tex, &image);
2330 2358
2331 COMMIT_RING(); 2359 COMMIT_RING();
2332 return ret; 2360 return ret;
2333} 2361}
2334 2362
2335static int radeon_cp_stipple( DRM_IOCTL_ARGS ) 2363static int radeon_cp_stipple(DRM_IOCTL_ARGS)
2336{ 2364{
2337 DRM_DEVICE; 2365 DRM_DEVICE;
2338 drm_radeon_private_t *dev_priv = dev->dev_private; 2366 drm_radeon_private_t *dev_priv = dev->dev_private;
2339 drm_radeon_stipple_t stipple; 2367 drm_radeon_stipple_t stipple;
2340 u32 mask[32]; 2368 u32 mask[32];
2341 2369
2342 LOCK_TEST_WITH_RETURN( dev, filp ); 2370 LOCK_TEST_WITH_RETURN(dev, filp);
2343 2371
2344 DRM_COPY_FROM_USER_IOCTL( stipple, (drm_radeon_stipple_t __user *)data, 2372 DRM_COPY_FROM_USER_IOCTL(stipple, (drm_radeon_stipple_t __user *) data,
2345 sizeof(stipple) ); 2373 sizeof(stipple));
2346 2374
2347 if ( DRM_COPY_FROM_USER( &mask, stipple.mask, 32 * sizeof(u32) ) ) 2375 if (DRM_COPY_FROM_USER(&mask, stipple.mask, 32 * sizeof(u32)))
2348 return DRM_ERR(EFAULT); 2376 return DRM_ERR(EFAULT);
2349 2377
2350 RING_SPACE_TEST_WITH_RETURN( dev_priv ); 2378 RING_SPACE_TEST_WITH_RETURN(dev_priv);
2351 2379
2352 radeon_cp_dispatch_stipple( dev, mask ); 2380 radeon_cp_dispatch_stipple(dev, mask);
2353 2381
2354 COMMIT_RING(); 2382 COMMIT_RING();
2355 return 0; 2383 return 0;
2356} 2384}
2357 2385
2358static int radeon_cp_indirect( DRM_IOCTL_ARGS ) 2386static int radeon_cp_indirect(DRM_IOCTL_ARGS)
2359{ 2387{
2360 DRM_DEVICE; 2388 DRM_DEVICE;
2361 drm_radeon_private_t *dev_priv = dev->dev_private; 2389 drm_radeon_private_t *dev_priv = dev->dev_private;
@@ -2364,53 +2392,53 @@ static int radeon_cp_indirect( DRM_IOCTL_ARGS )
2364 drm_radeon_indirect_t indirect; 2392 drm_radeon_indirect_t indirect;
2365 RING_LOCALS; 2393 RING_LOCALS;
2366 2394
2367 LOCK_TEST_WITH_RETURN( dev, filp ); 2395 LOCK_TEST_WITH_RETURN(dev, filp);
2368 2396
2369 if ( !dev_priv ) { 2397 if (!dev_priv) {
2370 DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ); 2398 DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
2371 return DRM_ERR(EINVAL); 2399 return DRM_ERR(EINVAL);
2372 } 2400 }
2373 2401
2374 DRM_COPY_FROM_USER_IOCTL( indirect, (drm_radeon_indirect_t __user *)data, 2402 DRM_COPY_FROM_USER_IOCTL(indirect,
2375 sizeof(indirect) ); 2403 (drm_radeon_indirect_t __user *) data,
2404 sizeof(indirect));
2376 2405
2377 DRM_DEBUG( "indirect: idx=%d s=%d e=%d d=%d\n", 2406 DRM_DEBUG("indirect: idx=%d s=%d e=%d d=%d\n",
2378 indirect.idx, indirect.start, 2407 indirect.idx, indirect.start, indirect.end, indirect.discard);
2379 indirect.end, indirect.discard );
2380 2408
2381 if ( indirect.idx < 0 || indirect.idx >= dma->buf_count ) { 2409 if (indirect.idx < 0 || indirect.idx >= dma->buf_count) {
2382 DRM_ERROR( "buffer index %d (of %d max)\n", 2410 DRM_ERROR("buffer index %d (of %d max)\n",
2383 indirect.idx, dma->buf_count - 1 ); 2411 indirect.idx, dma->buf_count - 1);
2384 return DRM_ERR(EINVAL); 2412 return DRM_ERR(EINVAL);
2385 } 2413 }
2386 2414
2387 buf = dma->buflist[indirect.idx]; 2415 buf = dma->buflist[indirect.idx];
2388 2416
2389 if ( buf->filp != filp ) { 2417 if (buf->filp != filp) {
2390 DRM_ERROR( "process %d using buffer owned by %p\n", 2418 DRM_ERROR("process %d using buffer owned by %p\n",
2391 DRM_CURRENTPID, buf->filp ); 2419 DRM_CURRENTPID, buf->filp);
2392 return DRM_ERR(EINVAL); 2420 return DRM_ERR(EINVAL);
2393 } 2421 }
2394 if ( buf->pending ) { 2422 if (buf->pending) {
2395 DRM_ERROR( "sending pending buffer %d\n", indirect.idx ); 2423 DRM_ERROR("sending pending buffer %d\n", indirect.idx);
2396 return DRM_ERR(EINVAL); 2424 return DRM_ERR(EINVAL);
2397 } 2425 }
2398 2426
2399 if ( indirect.start < buf->used ) { 2427 if (indirect.start < buf->used) {
2400 DRM_ERROR( "reusing indirect: start=0x%x actual=0x%x\n", 2428 DRM_ERROR("reusing indirect: start=0x%x actual=0x%x\n",
2401 indirect.start, buf->used ); 2429 indirect.start, buf->used);
2402 return DRM_ERR(EINVAL); 2430 return DRM_ERR(EINVAL);
2403 } 2431 }
2404 2432
2405 RING_SPACE_TEST_WITH_RETURN( dev_priv ); 2433 RING_SPACE_TEST_WITH_RETURN(dev_priv);
2406 VB_AGE_TEST_WITH_RETURN( dev_priv ); 2434 VB_AGE_TEST_WITH_RETURN(dev_priv);
2407 2435
2408 buf->used = indirect.end; 2436 buf->used = indirect.end;
2409 2437
2410 /* Wait for the 3D stream to idle before the indirect buffer 2438 /* Wait for the 3D stream to idle before the indirect buffer
2411 * containing 2D acceleration commands is processed. 2439 * containing 2D acceleration commands is processed.
2412 */ 2440 */
2413 BEGIN_RING( 2 ); 2441 BEGIN_RING(2);
2414 2442
2415 RADEON_WAIT_UNTIL_3D_IDLE(); 2443 RADEON_WAIT_UNTIL_3D_IDLE();
2416 2444
@@ -2420,17 +2448,16 @@ static int radeon_cp_indirect( DRM_IOCTL_ARGS )
2420 * X server. This is insecure and is thus only available to 2448 * X server. This is insecure and is thus only available to
2421 * privileged clients. 2449 * privileged clients.
2422 */ 2450 */
2423 radeon_cp_dispatch_indirect( dev, buf, indirect.start, indirect.end ); 2451 radeon_cp_dispatch_indirect(dev, buf, indirect.start, indirect.end);
2424 if (indirect.discard) { 2452 if (indirect.discard) {
2425 radeon_cp_discard_buffer( dev, buf ); 2453 radeon_cp_discard_buffer(dev, buf);
2426 } 2454 }
2427 2455
2428
2429 COMMIT_RING(); 2456 COMMIT_RING();
2430 return 0; 2457 return 0;
2431} 2458}
2432 2459
2433static int radeon_cp_vertex2( DRM_IOCTL_ARGS ) 2460static int radeon_cp_vertex2(DRM_IOCTL_ARGS)
2434{ 2461{
2435 DRM_DEVICE; 2462 DRM_DEVICE;
2436 drm_radeon_private_t *dev_priv = dev->dev_private; 2463 drm_radeon_private_t *dev_priv = dev->dev_private;
@@ -2442,65 +2469,64 @@ static int radeon_cp_vertex2( DRM_IOCTL_ARGS )
2442 int i; 2469 int i;
2443 unsigned char laststate; 2470 unsigned char laststate;
2444 2471
2445 LOCK_TEST_WITH_RETURN( dev, filp ); 2472 LOCK_TEST_WITH_RETURN(dev, filp);
2446 2473
2447 if ( !dev_priv ) { 2474 if (!dev_priv) {
2448 DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ); 2475 DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
2449 return DRM_ERR(EINVAL); 2476 return DRM_ERR(EINVAL);
2450 } 2477 }
2451 2478
2452 DRM_GET_PRIV_WITH_RETURN( filp_priv, filp ); 2479 DRM_GET_PRIV_WITH_RETURN(filp_priv, filp);
2453 2480
2454 DRM_COPY_FROM_USER_IOCTL( vertex, (drm_radeon_vertex2_t __user *)data, 2481 DRM_COPY_FROM_USER_IOCTL(vertex, (drm_radeon_vertex2_t __user *) data,
2455 sizeof(vertex) ); 2482 sizeof(vertex));
2456 2483
2457 DRM_DEBUG( "pid=%d index=%d discard=%d\n", 2484 DRM_DEBUG("pid=%d index=%d discard=%d\n",
2458 DRM_CURRENTPID, 2485 DRM_CURRENTPID, vertex.idx, vertex.discard);
2459 vertex.idx, vertex.discard );
2460 2486
2461 if ( vertex.idx < 0 || vertex.idx >= dma->buf_count ) { 2487 if (vertex.idx < 0 || vertex.idx >= dma->buf_count) {
2462 DRM_ERROR( "buffer index %d (of %d max)\n", 2488 DRM_ERROR("buffer index %d (of %d max)\n",
2463 vertex.idx, dma->buf_count - 1 ); 2489 vertex.idx, dma->buf_count - 1);
2464 return DRM_ERR(EINVAL); 2490 return DRM_ERR(EINVAL);
2465 } 2491 }
2466 2492
2467 RING_SPACE_TEST_WITH_RETURN( dev_priv ); 2493 RING_SPACE_TEST_WITH_RETURN(dev_priv);
2468 VB_AGE_TEST_WITH_RETURN( dev_priv ); 2494 VB_AGE_TEST_WITH_RETURN(dev_priv);
2469 2495
2470 buf = dma->buflist[vertex.idx]; 2496 buf = dma->buflist[vertex.idx];
2471 2497
2472 if ( buf->filp != filp ) { 2498 if (buf->filp != filp) {
2473 DRM_ERROR( "process %d using buffer owned by %p\n", 2499 DRM_ERROR("process %d using buffer owned by %p\n",
2474 DRM_CURRENTPID, buf->filp ); 2500 DRM_CURRENTPID, buf->filp);
2475 return DRM_ERR(EINVAL); 2501 return DRM_ERR(EINVAL);
2476 } 2502 }
2477 2503
2478 if ( buf->pending ) { 2504 if (buf->pending) {
2479 DRM_ERROR( "sending pending buffer %d\n", vertex.idx ); 2505 DRM_ERROR("sending pending buffer %d\n", vertex.idx);
2480 return DRM_ERR(EINVAL); 2506 return DRM_ERR(EINVAL);
2481 } 2507 }
2482 2508
2483 if (sarea_priv->nbox > RADEON_NR_SAREA_CLIPRECTS) 2509 if (sarea_priv->nbox > RADEON_NR_SAREA_CLIPRECTS)
2484 return DRM_ERR(EINVAL); 2510 return DRM_ERR(EINVAL);
2485 2511
2486 for (laststate = 0xff, i = 0 ; i < vertex.nr_prims ; i++) { 2512 for (laststate = 0xff, i = 0; i < vertex.nr_prims; i++) {
2487 drm_radeon_prim_t prim; 2513 drm_radeon_prim_t prim;
2488 drm_radeon_tcl_prim_t tclprim; 2514 drm_radeon_tcl_prim_t tclprim;
2489 2515
2490 if ( DRM_COPY_FROM_USER( &prim, &vertex.prim[i], sizeof(prim) ) ) 2516 if (DRM_COPY_FROM_USER(&prim, &vertex.prim[i], sizeof(prim)))
2491 return DRM_ERR(EFAULT); 2517 return DRM_ERR(EFAULT);
2492 2518
2493 if ( prim.stateidx != laststate ) { 2519 if (prim.stateidx != laststate) {
2494 drm_radeon_state_t state; 2520 drm_radeon_state_t state;
2495 2521
2496 if ( DRM_COPY_FROM_USER( &state, 2522 if (DRM_COPY_FROM_USER(&state,
2497 &vertex.state[prim.stateidx], 2523 &vertex.state[prim.stateidx],
2498 sizeof(state) ) ) 2524 sizeof(state)))
2499 return DRM_ERR(EFAULT); 2525 return DRM_ERR(EFAULT);
2500 2526
2501 if ( radeon_emit_state2( dev_priv, filp_priv, &state ) ) { 2527 if (radeon_emit_state2(dev_priv, filp_priv, &state)) {
2502 DRM_ERROR( "radeon_emit_state2 failed\n" ); 2528 DRM_ERROR("radeon_emit_state2 failed\n");
2503 return DRM_ERR( EINVAL ); 2529 return DRM_ERR(EINVAL);
2504 } 2530 }
2505 2531
2506 laststate = prim.stateidx; 2532 laststate = prim.stateidx;
@@ -2511,42 +2537,40 @@ static int radeon_cp_vertex2( DRM_IOCTL_ARGS )
2511 tclprim.prim = prim.prim; 2537 tclprim.prim = prim.prim;
2512 tclprim.vc_format = prim.vc_format; 2538 tclprim.vc_format = prim.vc_format;
2513 2539
2514 if ( prim.prim & RADEON_PRIM_WALK_IND ) { 2540 if (prim.prim & RADEON_PRIM_WALK_IND) {
2515 tclprim.offset = prim.numverts * 64; 2541 tclprim.offset = prim.numverts * 64;
2516 tclprim.numverts = RADEON_MAX_VB_VERTS; /* duh */ 2542 tclprim.numverts = RADEON_MAX_VB_VERTS; /* duh */
2517 2543
2518 radeon_cp_dispatch_indices( dev, buf, &tclprim ); 2544 radeon_cp_dispatch_indices(dev, buf, &tclprim);
2519 } else { 2545 } else {
2520 tclprim.numverts = prim.numverts; 2546 tclprim.numverts = prim.numverts;
2521 tclprim.offset = 0; /* not used */ 2547 tclprim.offset = 0; /* not used */
2522 2548
2523 radeon_cp_dispatch_vertex( dev, buf, &tclprim ); 2549 radeon_cp_dispatch_vertex(dev, buf, &tclprim);
2524 } 2550 }
2525 2551
2526 if (sarea_priv->nbox == 1) 2552 if (sarea_priv->nbox == 1)
2527 sarea_priv->nbox = 0; 2553 sarea_priv->nbox = 0;
2528 } 2554 }
2529 2555
2530 if ( vertex.discard ) { 2556 if (vertex.discard) {
2531 radeon_cp_discard_buffer( dev, buf ); 2557 radeon_cp_discard_buffer(dev, buf);
2532 } 2558 }
2533 2559
2534 COMMIT_RING(); 2560 COMMIT_RING();
2535 return 0; 2561 return 0;
2536} 2562}
2537 2563
2538 2564static int radeon_emit_packets(drm_radeon_private_t * dev_priv,
2539static int radeon_emit_packets( 2565 drm_file_t * filp_priv,
2540 drm_radeon_private_t *dev_priv, 2566 drm_radeon_cmd_header_t header,
2541 drm_file_t *filp_priv, 2567 drm_radeon_cmd_buffer_t * cmdbuf)
2542 drm_radeon_cmd_header_t header,
2543 drm_radeon_cmd_buffer_t *cmdbuf )
2544{ 2568{
2545 int id = (int)header.packet.packet_id; 2569 int id = (int)header.packet.packet_id;
2546 int sz, reg; 2570 int sz, reg;
2547 int *data = (int *)cmdbuf->buf; 2571 int *data = (int *)cmdbuf->buf;
2548 RING_LOCALS; 2572 RING_LOCALS;
2549 2573
2550 if (id >= RADEON_MAX_STATE_PACKETS) 2574 if (id >= RADEON_MAX_STATE_PACKETS)
2551 return DRM_ERR(EINVAL); 2575 return DRM_ERR(EINVAL);
2552 2576
@@ -2554,18 +2578,18 @@ static int radeon_emit_packets(
2554 reg = packet[id].start; 2578 reg = packet[id].start;
2555 2579
2556 if (sz * sizeof(int) > cmdbuf->bufsz) { 2580 if (sz * sizeof(int) > cmdbuf->bufsz) {
2557 DRM_ERROR( "Packet size provided larger than data provided\n" ); 2581 DRM_ERROR("Packet size provided larger than data provided\n");
2558 return DRM_ERR(EINVAL); 2582 return DRM_ERR(EINVAL);
2559 } 2583 }
2560 2584
2561 if ( radeon_check_and_fixup_packets( dev_priv, filp_priv, id, data ) ) { 2585 if (radeon_check_and_fixup_packets(dev_priv, filp_priv, id, data)) {
2562 DRM_ERROR( "Packet verification failed\n" ); 2586 DRM_ERROR("Packet verification failed\n");
2563 return DRM_ERR( EINVAL ); 2587 return DRM_ERR(EINVAL);
2564 } 2588 }
2565 2589
2566 BEGIN_RING(sz+1); 2590 BEGIN_RING(sz + 1);
2567 OUT_RING( CP_PACKET0( reg, (sz-1) ) ); 2591 OUT_RING(CP_PACKET0(reg, (sz - 1)));
2568 OUT_RING_TABLE( data, sz ); 2592 OUT_RING_TABLE(data, sz);
2569 ADVANCE_RING(); 2593 ADVANCE_RING();
2570 2594
2571 cmdbuf->buf += sz * sizeof(int); 2595 cmdbuf->buf += sz * sizeof(int);
@@ -2573,21 +2597,20 @@ static int radeon_emit_packets(
2573 return 0; 2597 return 0;
2574} 2598}
2575 2599
2576static __inline__ int radeon_emit_scalars( 2600static __inline__ int radeon_emit_scalars(drm_radeon_private_t * dev_priv,
2577 drm_radeon_private_t *dev_priv, 2601 drm_radeon_cmd_header_t header,
2578 drm_radeon_cmd_header_t header, 2602 drm_radeon_cmd_buffer_t * cmdbuf)
2579 drm_radeon_cmd_buffer_t *cmdbuf )
2580{ 2603{
2581 int sz = header.scalars.count; 2604 int sz = header.scalars.count;
2582 int start = header.scalars.offset; 2605 int start = header.scalars.offset;
2583 int stride = header.scalars.stride; 2606 int stride = header.scalars.stride;
2584 RING_LOCALS; 2607 RING_LOCALS;
2585 2608
2586 BEGIN_RING( 3+sz ); 2609 BEGIN_RING(3 + sz);
2587 OUT_RING( CP_PACKET0( RADEON_SE_TCL_SCALAR_INDX_REG, 0 ) ); 2610 OUT_RING(CP_PACKET0(RADEON_SE_TCL_SCALAR_INDX_REG, 0));
2588 OUT_RING( start | (stride << RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT)); 2611 OUT_RING(start | (stride << RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT));
2589 OUT_RING( CP_PACKET0_TABLE( RADEON_SE_TCL_SCALAR_DATA_REG, sz-1 ) ); 2612 OUT_RING(CP_PACKET0_TABLE(RADEON_SE_TCL_SCALAR_DATA_REG, sz - 1));
2590 OUT_RING_TABLE( cmdbuf->buf, sz ); 2613 OUT_RING_TABLE(cmdbuf->buf, sz);
2591 ADVANCE_RING(); 2614 ADVANCE_RING();
2592 cmdbuf->buf += sz * sizeof(int); 2615 cmdbuf->buf += sz * sizeof(int);
2593 cmdbuf->bufsz -= sz * sizeof(int); 2616 cmdbuf->bufsz -= sz * sizeof(int);
@@ -2596,42 +2619,40 @@ static __inline__ int radeon_emit_scalars(
2596 2619
2597/* God this is ugly 2620/* God this is ugly
2598 */ 2621 */
2599static __inline__ int radeon_emit_scalars2( 2622static __inline__ int radeon_emit_scalars2(drm_radeon_private_t * dev_priv,
2600 drm_radeon_private_t *dev_priv, 2623 drm_radeon_cmd_header_t header,
2601 drm_radeon_cmd_header_t header, 2624 drm_radeon_cmd_buffer_t * cmdbuf)
2602 drm_radeon_cmd_buffer_t *cmdbuf )
2603{ 2625{
2604 int sz = header.scalars.count; 2626 int sz = header.scalars.count;
2605 int start = ((unsigned int)header.scalars.offset) + 0x100; 2627 int start = ((unsigned int)header.scalars.offset) + 0x100;
2606 int stride = header.scalars.stride; 2628 int stride = header.scalars.stride;
2607 RING_LOCALS; 2629 RING_LOCALS;
2608 2630
2609 BEGIN_RING( 3+sz ); 2631 BEGIN_RING(3 + sz);
2610 OUT_RING( CP_PACKET0( RADEON_SE_TCL_SCALAR_INDX_REG, 0 ) ); 2632 OUT_RING(CP_PACKET0(RADEON_SE_TCL_SCALAR_INDX_REG, 0));
2611 OUT_RING( start | (stride << RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT)); 2633 OUT_RING(start | (stride << RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT));
2612 OUT_RING( CP_PACKET0_TABLE( RADEON_SE_TCL_SCALAR_DATA_REG, sz-1 ) ); 2634 OUT_RING(CP_PACKET0_TABLE(RADEON_SE_TCL_SCALAR_DATA_REG, sz - 1));
2613 OUT_RING_TABLE( cmdbuf->buf, sz ); 2635 OUT_RING_TABLE(cmdbuf->buf, sz);
2614 ADVANCE_RING(); 2636 ADVANCE_RING();
2615 cmdbuf->buf += sz * sizeof(int); 2637 cmdbuf->buf += sz * sizeof(int);
2616 cmdbuf->bufsz -= sz * sizeof(int); 2638 cmdbuf->bufsz -= sz * sizeof(int);
2617 return 0; 2639 return 0;
2618} 2640}
2619 2641
2620static __inline__ int radeon_emit_vectors( 2642static __inline__ int radeon_emit_vectors(drm_radeon_private_t * dev_priv,
2621 drm_radeon_private_t *dev_priv, 2643 drm_radeon_cmd_header_t header,
2622 drm_radeon_cmd_header_t header, 2644 drm_radeon_cmd_buffer_t * cmdbuf)
2623 drm_radeon_cmd_buffer_t *cmdbuf )
2624{ 2645{
2625 int sz = header.vectors.count; 2646 int sz = header.vectors.count;
2626 int start = header.vectors.offset; 2647 int start = header.vectors.offset;
2627 int stride = header.vectors.stride; 2648 int stride = header.vectors.stride;
2628 RING_LOCALS; 2649 RING_LOCALS;
2629 2650
2630 BEGIN_RING( 3+sz ); 2651 BEGIN_RING(3 + sz);
2631 OUT_RING( CP_PACKET0( RADEON_SE_TCL_VECTOR_INDX_REG, 0 ) ); 2652 OUT_RING(CP_PACKET0(RADEON_SE_TCL_VECTOR_INDX_REG, 0));
2632 OUT_RING( start | (stride << RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT)); 2653 OUT_RING(start | (stride << RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT));
2633 OUT_RING( CP_PACKET0_TABLE( RADEON_SE_TCL_VECTOR_DATA_REG, (sz-1) ) ); 2654 OUT_RING(CP_PACKET0_TABLE(RADEON_SE_TCL_VECTOR_DATA_REG, (sz - 1)));
2634 OUT_RING_TABLE( cmdbuf->buf, sz ); 2655 OUT_RING_TABLE(cmdbuf->buf, sz);
2635 ADVANCE_RING(); 2656 ADVANCE_RING();
2636 2657
2637 cmdbuf->buf += sz * sizeof(int); 2658 cmdbuf->buf += sz * sizeof(int);
@@ -2639,10 +2660,9 @@ static __inline__ int radeon_emit_vectors(
2639 return 0; 2660 return 0;
2640} 2661}
2641 2662
2642 2663static int radeon_emit_packet3(drm_device_t * dev,
2643static int radeon_emit_packet3( drm_device_t *dev, 2664 drm_file_t * filp_priv,
2644 drm_file_t *filp_priv, 2665 drm_radeon_cmd_buffer_t * cmdbuf)
2645 drm_radeon_cmd_buffer_t *cmdbuf )
2646{ 2666{
2647 drm_radeon_private_t *dev_priv = dev->dev_private; 2667 drm_radeon_private_t *dev_priv = dev->dev_private;
2648 unsigned int cmdsz; 2668 unsigned int cmdsz;
@@ -2651,14 +2671,14 @@ static int radeon_emit_packet3( drm_device_t *dev,
2651 2671
2652 DRM_DEBUG("\n"); 2672 DRM_DEBUG("\n");
2653 2673
2654 if ( ( ret = radeon_check_and_fixup_packet3( dev_priv, filp_priv, 2674 if ((ret = radeon_check_and_fixup_packet3(dev_priv, filp_priv,
2655 cmdbuf, &cmdsz ) ) ) { 2675 cmdbuf, &cmdsz))) {
2656 DRM_ERROR( "Packet verification failed\n" ); 2676 DRM_ERROR("Packet verification failed\n");
2657 return ret; 2677 return ret;
2658 } 2678 }
2659 2679
2660 BEGIN_RING( cmdsz ); 2680 BEGIN_RING(cmdsz);
2661 OUT_RING_TABLE( cmdbuf->buf, cmdsz ); 2681 OUT_RING_TABLE(cmdbuf->buf, cmdsz);
2662 ADVANCE_RING(); 2682 ADVANCE_RING();
2663 2683
2664 cmdbuf->buf += cmdsz * 4; 2684 cmdbuf->buf += cmdsz * 4;
@@ -2666,11 +2686,10 @@ static int radeon_emit_packet3( drm_device_t *dev,
2666 return 0; 2686 return 0;
2667} 2687}
2668 2688
2669 2689static int radeon_emit_packet3_cliprect(drm_device_t * dev,
2670static int radeon_emit_packet3_cliprect( drm_device_t *dev, 2690 drm_file_t * filp_priv,
2671 drm_file_t *filp_priv, 2691 drm_radeon_cmd_buffer_t * cmdbuf,
2672 drm_radeon_cmd_buffer_t *cmdbuf, 2692 int orig_nbox)
2673 int orig_nbox )
2674{ 2693{
2675 drm_radeon_private_t *dev_priv = dev->dev_private; 2694 drm_radeon_private_t *dev_priv = dev->dev_private;
2676 drm_clip_rect_t box; 2695 drm_clip_rect_t box;
@@ -2682,9 +2701,9 @@ static int radeon_emit_packet3_cliprect( drm_device_t *dev,
2682 2701
2683 DRM_DEBUG("\n"); 2702 DRM_DEBUG("\n");
2684 2703
2685 if ( ( ret = radeon_check_and_fixup_packet3( dev_priv, filp_priv, 2704 if ((ret = radeon_check_and_fixup_packet3(dev_priv, filp_priv,
2686 cmdbuf, &cmdsz ) ) ) { 2705 cmdbuf, &cmdsz))) {
2687 DRM_ERROR( "Packet verification failed\n" ); 2706 DRM_ERROR("Packet verification failed\n");
2688 return ret; 2707 return ret;
2689 } 2708 }
2690 2709
@@ -2692,8 +2711,8 @@ static int radeon_emit_packet3_cliprect( drm_device_t *dev,
2692 goto out; 2711 goto out;
2693 2712
2694 do { 2713 do {
2695 if ( i < cmdbuf->nbox ) { 2714 if (i < cmdbuf->nbox) {
2696 if (DRM_COPY_FROM_USER( &box, &boxes[i], sizeof(box) )) 2715 if (DRM_COPY_FROM_USER(&box, &boxes[i], sizeof(box)))
2697 return DRM_ERR(EFAULT); 2716 return DRM_ERR(EFAULT);
2698 /* FIXME The second and subsequent times round 2717 /* FIXME The second and subsequent times round
2699 * this loop, send a WAIT_UNTIL_3D_IDLE before 2718 * this loop, send a WAIT_UNTIL_3D_IDLE before
@@ -2707,30 +2726,29 @@ static int radeon_emit_packet3_cliprect( drm_device_t *dev,
2707 * the correct place to fix it but this works 2726 * the correct place to fix it but this works
2708 * around it until I can figure that out - Tim 2727 * around it until I can figure that out - Tim
2709 * Smith */ 2728 * Smith */
2710 if ( i ) { 2729 if (i) {
2711 BEGIN_RING( 2 ); 2730 BEGIN_RING(2);
2712 RADEON_WAIT_UNTIL_3D_IDLE(); 2731 RADEON_WAIT_UNTIL_3D_IDLE();
2713 ADVANCE_RING(); 2732 ADVANCE_RING();
2714 } 2733 }
2715 radeon_emit_clip_rect( dev_priv, &box ); 2734 radeon_emit_clip_rect(dev_priv, &box);
2716 } 2735 }
2717 2736
2718 BEGIN_RING( cmdsz ); 2737 BEGIN_RING(cmdsz);
2719 OUT_RING_TABLE( cmdbuf->buf, cmdsz ); 2738 OUT_RING_TABLE(cmdbuf->buf, cmdsz);
2720 ADVANCE_RING(); 2739 ADVANCE_RING();
2721 2740
2722 } while ( ++i < cmdbuf->nbox ); 2741 } while (++i < cmdbuf->nbox);
2723 if (cmdbuf->nbox == 1) 2742 if (cmdbuf->nbox == 1)
2724 cmdbuf->nbox = 0; 2743 cmdbuf->nbox = 0;
2725 2744
2726 out: 2745 out:
2727 cmdbuf->buf += cmdsz * 4; 2746 cmdbuf->buf += cmdsz * 4;
2728 cmdbuf->bufsz -= cmdsz * 4; 2747 cmdbuf->bufsz -= cmdsz * 4;
2729 return 0; 2748 return 0;
2730} 2749}
2731 2750
2732 2751static int radeon_emit_wait(drm_device_t * dev, int flags)
2733static int radeon_emit_wait( drm_device_t *dev, int flags )
2734{ 2752{
2735 drm_radeon_private_t *dev_priv = dev->dev_private; 2753 drm_radeon_private_t *dev_priv = dev->dev_private;
2736 RING_LOCALS; 2754 RING_LOCALS;
@@ -2738,18 +2756,18 @@ static int radeon_emit_wait( drm_device_t *dev, int flags )
2738 DRM_DEBUG("%s: %x\n", __FUNCTION__, flags); 2756 DRM_DEBUG("%s: %x\n", __FUNCTION__, flags);
2739 switch (flags) { 2757 switch (flags) {
2740 case RADEON_WAIT_2D: 2758 case RADEON_WAIT_2D:
2741 BEGIN_RING( 2 ); 2759 BEGIN_RING(2);
2742 RADEON_WAIT_UNTIL_2D_IDLE(); 2760 RADEON_WAIT_UNTIL_2D_IDLE();
2743 ADVANCE_RING(); 2761 ADVANCE_RING();
2744 break; 2762 break;
2745 case RADEON_WAIT_3D: 2763 case RADEON_WAIT_3D:
2746 BEGIN_RING( 2 ); 2764 BEGIN_RING(2);
2747 RADEON_WAIT_UNTIL_3D_IDLE(); 2765 RADEON_WAIT_UNTIL_3D_IDLE();
2748 ADVANCE_RING(); 2766 ADVANCE_RING();
2749 break; 2767 break;
2750 case RADEON_WAIT_2D|RADEON_WAIT_3D: 2768 case RADEON_WAIT_2D | RADEON_WAIT_3D:
2751 BEGIN_RING( 2 ); 2769 BEGIN_RING(2);
2752 RADEON_WAIT_UNTIL_IDLE(); 2770 RADEON_WAIT_UNTIL_IDLE();
2753 ADVANCE_RING(); 2771 ADVANCE_RING();
2754 break; 2772 break;
2755 default: 2773 default:
@@ -2759,7 +2777,7 @@ static int radeon_emit_wait( drm_device_t *dev, int flags )
2759 return 0; 2777 return 0;
2760} 2778}
2761 2779
2762static int radeon_cp_cmdbuf( DRM_IOCTL_ARGS ) 2780static int radeon_cp_cmdbuf(DRM_IOCTL_ARGS)
2763{ 2781{
2764 DRM_DEVICE; 2782 DRM_DEVICE;
2765 drm_radeon_private_t *dev_priv = dev->dev_private; 2783 drm_radeon_private_t *dev_priv = dev->dev_private;
@@ -2770,24 +2788,25 @@ static int radeon_cp_cmdbuf( DRM_IOCTL_ARGS )
2770 drm_radeon_cmd_buffer_t cmdbuf; 2788 drm_radeon_cmd_buffer_t cmdbuf;
2771 drm_radeon_cmd_header_t header; 2789 drm_radeon_cmd_header_t header;
2772 int orig_nbox, orig_bufsz; 2790 int orig_nbox, orig_bufsz;
2773 char *kbuf=NULL; 2791 char *kbuf = NULL;
2774 2792
2775 LOCK_TEST_WITH_RETURN( dev, filp ); 2793 LOCK_TEST_WITH_RETURN(dev, filp);
2776 2794
2777 if ( !dev_priv ) { 2795 if (!dev_priv) {
2778 DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ); 2796 DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
2779 return DRM_ERR(EINVAL); 2797 return DRM_ERR(EINVAL);
2780 } 2798 }
2781 2799
2782 DRM_GET_PRIV_WITH_RETURN( filp_priv, filp ); 2800 DRM_GET_PRIV_WITH_RETURN(filp_priv, filp);
2783 2801
2784 DRM_COPY_FROM_USER_IOCTL( cmdbuf, (drm_radeon_cmd_buffer_t __user *)data, 2802 DRM_COPY_FROM_USER_IOCTL(cmdbuf,
2785 sizeof(cmdbuf) ); 2803 (drm_radeon_cmd_buffer_t __user *) data,
2804 sizeof(cmdbuf));
2786 2805
2787 RING_SPACE_TEST_WITH_RETURN( dev_priv ); 2806 RING_SPACE_TEST_WITH_RETURN(dev_priv);
2788 VB_AGE_TEST_WITH_RETURN( dev_priv ); 2807 VB_AGE_TEST_WITH_RETURN(dev_priv);
2789 2808
2790 if (cmdbuf.bufsz > 64*1024 || cmdbuf.bufsz<0) { 2809 if (cmdbuf.bufsz > 64 * 1024 || cmdbuf.bufsz < 0) {
2791 return DRM_ERR(EINVAL); 2810 return DRM_ERR(EINVAL);
2792 } 2811 }
2793 2812
@@ -2809,27 +2828,28 @@ static int radeon_cp_cmdbuf( DRM_IOCTL_ARGS )
2809 2828
2810 orig_nbox = cmdbuf.nbox; 2829 orig_nbox = cmdbuf.nbox;
2811 2830
2812 if(dev_priv->microcode_version == UCODE_R300) { 2831 if (dev_priv->microcode_version == UCODE_R300) {
2813 int temp; 2832 int temp;
2814 temp=r300_do_cp_cmdbuf(dev, filp, filp_priv, &cmdbuf); 2833 temp = r300_do_cp_cmdbuf(dev, filp, filp_priv, &cmdbuf);
2815 2834
2816 if (orig_bufsz != 0) 2835 if (orig_bufsz != 0)
2817 drm_free(kbuf, orig_bufsz, DRM_MEM_DRIVER); 2836 drm_free(kbuf, orig_bufsz, DRM_MEM_DRIVER);
2818 2837
2819 return temp; 2838 return temp;
2820 } 2839 }
2821 2840
2822 /* microcode_version != r300 */ 2841 /* microcode_version != r300 */
2823 while ( cmdbuf.bufsz >= sizeof(header) ) { 2842 while (cmdbuf.bufsz >= sizeof(header)) {
2824 2843
2825 header.i = *(int *)cmdbuf.buf; 2844 header.i = *(int *)cmdbuf.buf;
2826 cmdbuf.buf += sizeof(header); 2845 cmdbuf.buf += sizeof(header);
2827 cmdbuf.bufsz -= sizeof(header); 2846 cmdbuf.bufsz -= sizeof(header);
2828 2847
2829 switch (header.header.cmd_type) { 2848 switch (header.header.cmd_type) {
2830 case RADEON_CMD_PACKET: 2849 case RADEON_CMD_PACKET:
2831 DRM_DEBUG("RADEON_CMD_PACKET\n"); 2850 DRM_DEBUG("RADEON_CMD_PACKET\n");
2832 if (radeon_emit_packets( dev_priv, filp_priv, header, &cmdbuf )) { 2851 if (radeon_emit_packets
2852 (dev_priv, filp_priv, header, &cmdbuf)) {
2833 DRM_ERROR("radeon_emit_packets failed\n"); 2853 DRM_ERROR("radeon_emit_packets failed\n");
2834 goto err; 2854 goto err;
2835 } 2855 }
@@ -2837,7 +2857,7 @@ static int radeon_cp_cmdbuf( DRM_IOCTL_ARGS )
2837 2857
2838 case RADEON_CMD_SCALARS: 2858 case RADEON_CMD_SCALARS:
2839 DRM_DEBUG("RADEON_CMD_SCALARS\n"); 2859 DRM_DEBUG("RADEON_CMD_SCALARS\n");
2840 if (radeon_emit_scalars( dev_priv, header, &cmdbuf )) { 2860 if (radeon_emit_scalars(dev_priv, header, &cmdbuf)) {
2841 DRM_ERROR("radeon_emit_scalars failed\n"); 2861 DRM_ERROR("radeon_emit_scalars failed\n");
2842 goto err; 2862 goto err;
2843 } 2863 }
@@ -2845,7 +2865,7 @@ static int radeon_cp_cmdbuf( DRM_IOCTL_ARGS )
2845 2865
2846 case RADEON_CMD_VECTORS: 2866 case RADEON_CMD_VECTORS:
2847 DRM_DEBUG("RADEON_CMD_VECTORS\n"); 2867 DRM_DEBUG("RADEON_CMD_VECTORS\n");
2848 if (radeon_emit_vectors( dev_priv, header, &cmdbuf )) { 2868 if (radeon_emit_vectors(dev_priv, header, &cmdbuf)) {
2849 DRM_ERROR("radeon_emit_vectors failed\n"); 2869 DRM_ERROR("radeon_emit_vectors failed\n");
2850 goto err; 2870 goto err;
2851 } 2871 }
@@ -2854,25 +2874,25 @@ static int radeon_cp_cmdbuf( DRM_IOCTL_ARGS )
2854 case RADEON_CMD_DMA_DISCARD: 2874 case RADEON_CMD_DMA_DISCARD:
2855 DRM_DEBUG("RADEON_CMD_DMA_DISCARD\n"); 2875 DRM_DEBUG("RADEON_CMD_DMA_DISCARD\n");
2856 idx = header.dma.buf_idx; 2876 idx = header.dma.buf_idx;
2857 if ( idx < 0 || idx >= dma->buf_count ) { 2877 if (idx < 0 || idx >= dma->buf_count) {
2858 DRM_ERROR( "buffer index %d (of %d max)\n", 2878 DRM_ERROR("buffer index %d (of %d max)\n",
2859 idx, dma->buf_count - 1 ); 2879 idx, dma->buf_count - 1);
2860 goto err; 2880 goto err;
2861 } 2881 }
2862 2882
2863 buf = dma->buflist[idx]; 2883 buf = dma->buflist[idx];
2864 if ( buf->filp != filp || buf->pending ) { 2884 if (buf->filp != filp || buf->pending) {
2865 DRM_ERROR( "bad buffer %p %p %d\n", 2885 DRM_ERROR("bad buffer %p %p %d\n",
2866 buf->filp, filp, buf->pending); 2886 buf->filp, filp, buf->pending);
2867 goto err; 2887 goto err;
2868 } 2888 }
2869 2889
2870 radeon_cp_discard_buffer( dev, buf ); 2890 radeon_cp_discard_buffer(dev, buf);
2871 break; 2891 break;
2872 2892
2873 case RADEON_CMD_PACKET3: 2893 case RADEON_CMD_PACKET3:
2874 DRM_DEBUG("RADEON_CMD_PACKET3\n"); 2894 DRM_DEBUG("RADEON_CMD_PACKET3\n");
2875 if (radeon_emit_packet3( dev, filp_priv, &cmdbuf )) { 2895 if (radeon_emit_packet3(dev, filp_priv, &cmdbuf)) {
2876 DRM_ERROR("radeon_emit_packet3 failed\n"); 2896 DRM_ERROR("radeon_emit_packet3 failed\n");
2877 goto err; 2897 goto err;
2878 } 2898 }
@@ -2880,7 +2900,8 @@ static int radeon_cp_cmdbuf( DRM_IOCTL_ARGS )
2880 2900
2881 case RADEON_CMD_PACKET3_CLIP: 2901 case RADEON_CMD_PACKET3_CLIP:
2882 DRM_DEBUG("RADEON_CMD_PACKET3_CLIP\n"); 2902 DRM_DEBUG("RADEON_CMD_PACKET3_CLIP\n");
2883 if (radeon_emit_packet3_cliprect( dev, filp_priv, &cmdbuf, orig_nbox )) { 2903 if (radeon_emit_packet3_cliprect
2904 (dev, filp_priv, &cmdbuf, orig_nbox)) {
2884 DRM_ERROR("radeon_emit_packet3_clip failed\n"); 2905 DRM_ERROR("radeon_emit_packet3_clip failed\n");
2885 goto err; 2906 goto err;
2886 } 2907 }
@@ -2888,7 +2909,7 @@ static int radeon_cp_cmdbuf( DRM_IOCTL_ARGS )
2888 2909
2889 case RADEON_CMD_SCALARS2: 2910 case RADEON_CMD_SCALARS2:
2890 DRM_DEBUG("RADEON_CMD_SCALARS2\n"); 2911 DRM_DEBUG("RADEON_CMD_SCALARS2\n");
2891 if (radeon_emit_scalars2( dev_priv, header, &cmdbuf )) { 2912 if (radeon_emit_scalars2(dev_priv, header, &cmdbuf)) {
2892 DRM_ERROR("radeon_emit_scalars2 failed\n"); 2913 DRM_ERROR("radeon_emit_scalars2 failed\n");
2893 goto err; 2914 goto err;
2894 } 2915 }
@@ -2896,13 +2917,13 @@ static int radeon_cp_cmdbuf( DRM_IOCTL_ARGS )
2896 2917
2897 case RADEON_CMD_WAIT: 2918 case RADEON_CMD_WAIT:
2898 DRM_DEBUG("RADEON_CMD_WAIT\n"); 2919 DRM_DEBUG("RADEON_CMD_WAIT\n");
2899 if (radeon_emit_wait( dev, header.wait.flags )) { 2920 if (radeon_emit_wait(dev, header.wait.flags)) {
2900 DRM_ERROR("radeon_emit_wait failed\n"); 2921 DRM_ERROR("radeon_emit_wait failed\n");
2901 goto err; 2922 goto err;
2902 } 2923 }
2903 break; 2924 break;
2904 default: 2925 default:
2905 DRM_ERROR("bad cmd_type %d at %p\n", 2926 DRM_ERROR("bad cmd_type %d at %p\n",
2906 header.header.cmd_type, 2927 header.header.cmd_type,
2907 cmdbuf.buf - sizeof(header)); 2928 cmdbuf.buf - sizeof(header));
2908 goto err; 2929 goto err;
@@ -2916,45 +2937,43 @@ static int radeon_cp_cmdbuf( DRM_IOCTL_ARGS )
2916 COMMIT_RING(); 2937 COMMIT_RING();
2917 return 0; 2938 return 0;
2918 2939
2919err: 2940 err:
2920 if (orig_bufsz != 0) 2941 if (orig_bufsz != 0)
2921 drm_free(kbuf, orig_bufsz, DRM_MEM_DRIVER); 2942 drm_free(kbuf, orig_bufsz, DRM_MEM_DRIVER);
2922 return DRM_ERR(EINVAL); 2943 return DRM_ERR(EINVAL);
2923} 2944}
2924 2945
2925 2946static int radeon_cp_getparam(DRM_IOCTL_ARGS)
2926
2927static int radeon_cp_getparam( DRM_IOCTL_ARGS )
2928{ 2947{
2929 DRM_DEVICE; 2948 DRM_DEVICE;
2930 drm_radeon_private_t *dev_priv = dev->dev_private; 2949 drm_radeon_private_t *dev_priv = dev->dev_private;
2931 drm_radeon_getparam_t param; 2950 drm_radeon_getparam_t param;
2932 int value; 2951 int value;
2933 2952
2934 if ( !dev_priv ) { 2953 if (!dev_priv) {
2935 DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ); 2954 DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
2936 return DRM_ERR(EINVAL); 2955 return DRM_ERR(EINVAL);
2937 } 2956 }
2938 2957
2939 DRM_COPY_FROM_USER_IOCTL( param, (drm_radeon_getparam_t __user *)data, 2958 DRM_COPY_FROM_USER_IOCTL(param, (drm_radeon_getparam_t __user *) data,
2940 sizeof(param) ); 2959 sizeof(param));
2941 2960
2942 DRM_DEBUG( "pid=%d\n", DRM_CURRENTPID ); 2961 DRM_DEBUG("pid=%d\n", DRM_CURRENTPID);
2943 2962
2944 switch( param.param ) { 2963 switch (param.param) {
2945 case RADEON_PARAM_GART_BUFFER_OFFSET: 2964 case RADEON_PARAM_GART_BUFFER_OFFSET:
2946 value = dev_priv->gart_buffers_offset; 2965 value = dev_priv->gart_buffers_offset;
2947 break; 2966 break;
2948 case RADEON_PARAM_LAST_FRAME: 2967 case RADEON_PARAM_LAST_FRAME:
2949 dev_priv->stats.last_frame_reads++; 2968 dev_priv->stats.last_frame_reads++;
2950 value = GET_SCRATCH( 0 ); 2969 value = GET_SCRATCH(0);
2951 break; 2970 break;
2952 case RADEON_PARAM_LAST_DISPATCH: 2971 case RADEON_PARAM_LAST_DISPATCH:
2953 value = GET_SCRATCH( 1 ); 2972 value = GET_SCRATCH(1);
2954 break; 2973 break;
2955 case RADEON_PARAM_LAST_CLEAR: 2974 case RADEON_PARAM_LAST_CLEAR:
2956 dev_priv->stats.last_clear_reads++; 2975 dev_priv->stats.last_clear_reads++;
2957 value = GET_SCRATCH( 2 ); 2976 value = GET_SCRATCH(2);
2958 break; 2977 break;
2959 case RADEON_PARAM_IRQ_NR: 2978 case RADEON_PARAM_IRQ_NR:
2960 value = dev->irq; 2979 value = dev->irq;
@@ -2969,15 +2988,15 @@ static int radeon_cp_getparam( DRM_IOCTL_ARGS )
2969 value = dev_priv->ring_rptr_offset; 2988 value = dev_priv->ring_rptr_offset;
2970 break; 2989 break;
2971#if BITS_PER_LONG == 32 2990#if BITS_PER_LONG == 32
2972 /* 2991 /*
2973 * This ioctl() doesn't work on 64-bit platforms because hw_lock is a 2992 * This ioctl() doesn't work on 64-bit platforms because hw_lock is a
2974 * pointer which can't fit into an int-sized variable. According to 2993 * pointer which can't fit into an int-sized variable. According to
2975 * Michel Dänzer, the ioctl() is only used on embedded platforms, so 2994 * Michel Dänzer, the ioctl() is only used on embedded platforms, so
2976 * not supporting it shouldn't be a problem. If the same functionality 2995 * not supporting it shouldn't be a problem. If the same functionality
2977 * is needed on 64-bit platforms, a new ioctl() would have to be added, 2996 * is needed on 64-bit platforms, a new ioctl() would have to be added,
2978 * so backwards-compatibility for the embedded platforms can be 2997 * so backwards-compatibility for the embedded platforms can be
2979 * maintained. --davidm 4-Feb-2004. 2998 * maintained. --davidm 4-Feb-2004.
2980 */ 2999 */
2981 case RADEON_PARAM_SAREA_HANDLE: 3000 case RADEON_PARAM_SAREA_HANDLE:
2982 /* The lock is the first dword in the sarea. */ 3001 /* The lock is the first dword in the sarea. */
2983 value = (long)dev->lock.hw_lock; 3002 value = (long)dev->lock.hw_lock;
@@ -2990,56 +3009,56 @@ static int radeon_cp_getparam( DRM_IOCTL_ARGS )
2990 return DRM_ERR(EINVAL); 3009 return DRM_ERR(EINVAL);
2991 } 3010 }
2992 3011
2993 if ( DRM_COPY_TO_USER( param.value, &value, sizeof(int) ) ) { 3012 if (DRM_COPY_TO_USER(param.value, &value, sizeof(int))) {
2994 DRM_ERROR( "copy_to_user\n" ); 3013 DRM_ERROR("copy_to_user\n");
2995 return DRM_ERR(EFAULT); 3014 return DRM_ERR(EFAULT);
2996 } 3015 }
2997 3016
2998 return 0; 3017 return 0;
2999} 3018}
3000 3019
3001static int radeon_cp_setparam( DRM_IOCTL_ARGS ) { 3020static int radeon_cp_setparam(DRM_IOCTL_ARGS)
3021{
3002 DRM_DEVICE; 3022 DRM_DEVICE;
3003 drm_radeon_private_t *dev_priv = dev->dev_private; 3023 drm_radeon_private_t *dev_priv = dev->dev_private;
3004 drm_file_t *filp_priv; 3024 drm_file_t *filp_priv;
3005 drm_radeon_setparam_t sp; 3025 drm_radeon_setparam_t sp;
3006 struct drm_radeon_driver_file_fields *radeon_priv; 3026 struct drm_radeon_driver_file_fields *radeon_priv;
3007 3027
3008 if ( !dev_priv ) { 3028 if (!dev_priv) {
3009 DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ); 3029 DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
3010 return DRM_ERR( EINVAL ); 3030 return DRM_ERR(EINVAL);
3011 } 3031 }
3012 3032
3013 DRM_GET_PRIV_WITH_RETURN( filp_priv, filp ); 3033 DRM_GET_PRIV_WITH_RETURN(filp_priv, filp);
3014 3034
3015 DRM_COPY_FROM_USER_IOCTL( sp, ( drm_radeon_setparam_t __user * )data, 3035 DRM_COPY_FROM_USER_IOCTL(sp, (drm_radeon_setparam_t __user *) data,
3016 sizeof( sp ) ); 3036 sizeof(sp));
3017 3037
3018 switch( sp.param ) { 3038 switch (sp.param) {
3019 case RADEON_SETPARAM_FB_LOCATION: 3039 case RADEON_SETPARAM_FB_LOCATION:
3020 radeon_priv = filp_priv->driver_priv; 3040 radeon_priv = filp_priv->driver_priv;
3021 radeon_priv->radeon_fb_delta = dev_priv->fb_location - sp.value; 3041 radeon_priv->radeon_fb_delta = dev_priv->fb_location - sp.value;
3022 break; 3042 break;
3023 case RADEON_SETPARAM_SWITCH_TILING: 3043 case RADEON_SETPARAM_SWITCH_TILING:
3024 if (sp.value == 0) { 3044 if (sp.value == 0) {
3025 DRM_DEBUG( "color tiling disabled\n" ); 3045 DRM_DEBUG("color tiling disabled\n");
3026 dev_priv->front_pitch_offset &= ~RADEON_DST_TILE_MACRO; 3046 dev_priv->front_pitch_offset &= ~RADEON_DST_TILE_MACRO;
3027 dev_priv->back_pitch_offset &= ~RADEON_DST_TILE_MACRO; 3047 dev_priv->back_pitch_offset &= ~RADEON_DST_TILE_MACRO;
3028 dev_priv->sarea_priv->tiling_enabled = 0; 3048 dev_priv->sarea_priv->tiling_enabled = 0;
3029 } 3049 } else if (sp.value == 1) {
3030 else if (sp.value == 1) { 3050 DRM_DEBUG("color tiling enabled\n");
3031 DRM_DEBUG( "color tiling enabled\n" );
3032 dev_priv->front_pitch_offset |= RADEON_DST_TILE_MACRO; 3051 dev_priv->front_pitch_offset |= RADEON_DST_TILE_MACRO;
3033 dev_priv->back_pitch_offset |= RADEON_DST_TILE_MACRO; 3052 dev_priv->back_pitch_offset |= RADEON_DST_TILE_MACRO;
3034 dev_priv->sarea_priv->tiling_enabled = 1; 3053 dev_priv->sarea_priv->tiling_enabled = 1;
3035 } 3054 }
3036 break; 3055 break;
3037 case RADEON_SETPARAM_PCIGART_LOCATION: 3056 case RADEON_SETPARAM_PCIGART_LOCATION:
3038 dev_priv->pcigart_offset = sp.value; 3057 dev_priv->pcigart_offset = sp.value;
3039 break; 3058 break;
3040 default: 3059 default:
3041 DRM_DEBUG( "Invalid parameter %d\n", sp.param ); 3060 DRM_DEBUG("Invalid parameter %d\n", sp.param);
3042 return DRM_ERR( EINVAL ); 3061 return DRM_ERR(EINVAL);
3043 } 3062 }
3044 3063
3045 return 0; 3064 return 0;
@@ -3051,78 +3070,106 @@ static int radeon_cp_setparam( DRM_IOCTL_ARGS ) {
3051 * 3070 *
3052 * DRM infrastructure takes care of reclaiming dma buffers. 3071 * DRM infrastructure takes care of reclaiming dma buffers.
3053 */ 3072 */
3054void radeon_driver_prerelease(drm_device_t *dev, DRMFILE filp) 3073void radeon_driver_prerelease(drm_device_t * dev, DRMFILE filp)
3055{ 3074{
3056 if ( dev->dev_private ) { 3075 if (dev->dev_private) {
3057 drm_radeon_private_t *dev_priv = dev->dev_private; 3076 drm_radeon_private_t *dev_priv = dev->dev_private;
3058 if ( dev_priv->page_flipping ) { 3077 if (dev_priv->page_flipping) {
3059 radeon_do_cleanup_pageflip( dev ); 3078 radeon_do_cleanup_pageflip(dev);
3060 } 3079 }
3061 radeon_mem_release( filp, dev_priv->gart_heap ); 3080 radeon_mem_release(filp, dev_priv->gart_heap);
3062 radeon_mem_release( filp, dev_priv->fb_heap ); 3081 radeon_mem_release(filp, dev_priv->fb_heap);
3063 radeon_surfaces_release(filp, dev_priv); 3082 radeon_surfaces_release(filp, dev_priv);
3064 } 3083 }
3065} 3084}
3066 3085
3067void radeon_driver_pretakedown(drm_device_t *dev) 3086void radeon_driver_pretakedown(drm_device_t * dev)
3068{ 3087{
3069 radeon_do_release(dev); 3088 radeon_do_release(dev);
3070} 3089}
3071 3090
3072int radeon_driver_open_helper(drm_device_t *dev, drm_file_t *filp_priv) 3091int radeon_driver_open_helper(drm_device_t * dev, drm_file_t * filp_priv)
3073{ 3092{
3074 drm_radeon_private_t *dev_priv = dev->dev_private; 3093 drm_radeon_private_t *dev_priv = dev->dev_private;
3075 struct drm_radeon_driver_file_fields *radeon_priv; 3094 struct drm_radeon_driver_file_fields *radeon_priv;
3076 3095
3077 radeon_priv = (struct drm_radeon_driver_file_fields *)drm_alloc(sizeof(*radeon_priv), DRM_MEM_FILES); 3096 radeon_priv =
3078 3097 (struct drm_radeon_driver_file_fields *)
3098 drm_alloc(sizeof(*radeon_priv), DRM_MEM_FILES);
3099
3079 if (!radeon_priv) 3100 if (!radeon_priv)
3080 return -ENOMEM; 3101 return -ENOMEM;
3081 3102
3082 filp_priv->driver_priv = radeon_priv; 3103 filp_priv->driver_priv = radeon_priv;
3083 if ( dev_priv ) 3104 if (dev_priv)
3084 radeon_priv->radeon_fb_delta = dev_priv->fb_location; 3105 radeon_priv->radeon_fb_delta = dev_priv->fb_location;
3085 else 3106 else
3086 radeon_priv->radeon_fb_delta = 0; 3107 radeon_priv->radeon_fb_delta = 0;
3087 return 0; 3108 return 0;
3088} 3109}
3089 3110
3090 3111void radeon_driver_free_filp_priv(drm_device_t * dev, drm_file_t * filp_priv)
3091void radeon_driver_free_filp_priv(drm_device_t *dev, drm_file_t *filp_priv)
3092{ 3112{
3093 struct drm_radeon_driver_file_fields *radeon_priv = filp_priv->driver_priv; 3113 struct drm_radeon_driver_file_fields *radeon_priv =
3094 3114 filp_priv->driver_priv;
3095 drm_free(radeon_priv, sizeof(*radeon_priv), DRM_MEM_FILES); 3115
3116 drm_free(radeon_priv, sizeof(*radeon_priv), DRM_MEM_FILES);
3096} 3117}
3097 3118
3098drm_ioctl_desc_t radeon_ioctls[] = { 3119drm_ioctl_desc_t radeon_ioctls[] = {
3099 [DRM_IOCTL_NR(DRM_RADEON_CP_INIT)] = { radeon_cp_init, 1, 1 }, 3120 [DRM_IOCTL_NR(DRM_RADEON_CP_INIT)] = {radeon_cp_init, 1, 1}
3100 [DRM_IOCTL_NR(DRM_RADEON_CP_START)] = { radeon_cp_start, 1, 1 }, 3121 ,
3101 [DRM_IOCTL_NR(DRM_RADEON_CP_STOP)] = { radeon_cp_stop, 1, 1 }, 3122 [DRM_IOCTL_NR(DRM_RADEON_CP_START)] = {radeon_cp_start, 1, 1}
3102 [DRM_IOCTL_NR(DRM_RADEON_CP_RESET)] = { radeon_cp_reset, 1, 1 }, 3123 ,
3103 [DRM_IOCTL_NR(DRM_RADEON_CP_IDLE)] = { radeon_cp_idle, 1, 0 }, 3124 [DRM_IOCTL_NR(DRM_RADEON_CP_STOP)] = {radeon_cp_stop, 1, 1}
3104 [DRM_IOCTL_NR(DRM_RADEON_CP_RESUME)] = { radeon_cp_resume, 1, 0 }, 3125 ,
3105 [DRM_IOCTL_NR(DRM_RADEON_RESET)] = { radeon_engine_reset, 1, 0 }, 3126 [DRM_IOCTL_NR(DRM_RADEON_CP_RESET)] = {radeon_cp_reset, 1, 1}
3106 [DRM_IOCTL_NR(DRM_RADEON_FULLSCREEN)] = { radeon_fullscreen, 1, 0 }, 3127 ,
3107 [DRM_IOCTL_NR(DRM_RADEON_SWAP)] = { radeon_cp_swap, 1, 0 }, 3128 [DRM_IOCTL_NR(DRM_RADEON_CP_IDLE)] = {radeon_cp_idle, 1, 0}
3108 [DRM_IOCTL_NR(DRM_RADEON_CLEAR)] = { radeon_cp_clear, 1, 0 }, 3129 ,
3109 [DRM_IOCTL_NR(DRM_RADEON_VERTEX)] = { radeon_cp_vertex, 1, 0 }, 3130 [DRM_IOCTL_NR(DRM_RADEON_CP_RESUME)] = {radeon_cp_resume, 1, 0}
3110 [DRM_IOCTL_NR(DRM_RADEON_INDICES)] = { radeon_cp_indices, 1, 0 }, 3131 ,
3111 [DRM_IOCTL_NR(DRM_RADEON_TEXTURE)] = { radeon_cp_texture, 1, 0 }, 3132 [DRM_IOCTL_NR(DRM_RADEON_RESET)] = {radeon_engine_reset, 1, 0}
3112 [DRM_IOCTL_NR(DRM_RADEON_STIPPLE)] = { radeon_cp_stipple, 1, 0 }, 3133 ,
3113 [DRM_IOCTL_NR(DRM_RADEON_INDIRECT)] = { radeon_cp_indirect, 1, 1 }, 3134 [DRM_IOCTL_NR(DRM_RADEON_FULLSCREEN)] = {radeon_fullscreen, 1, 0}
3114 [DRM_IOCTL_NR(DRM_RADEON_VERTEX2)] = { radeon_cp_vertex2, 1, 0 }, 3135 ,
3115 [DRM_IOCTL_NR(DRM_RADEON_CMDBUF)] = { radeon_cp_cmdbuf, 1, 0 }, 3136 [DRM_IOCTL_NR(DRM_RADEON_SWAP)] = {radeon_cp_swap, 1, 0}
3116 [DRM_IOCTL_NR(DRM_RADEON_GETPARAM)] = { radeon_cp_getparam, 1, 0 }, 3137 ,
3117 [DRM_IOCTL_NR(DRM_RADEON_FLIP)] = { radeon_cp_flip, 1, 0 }, 3138 [DRM_IOCTL_NR(DRM_RADEON_CLEAR)] = {radeon_cp_clear, 1, 0}
3118 [DRM_IOCTL_NR(DRM_RADEON_ALLOC)] = { radeon_mem_alloc, 1, 0 }, 3139 ,
3119 [DRM_IOCTL_NR(DRM_RADEON_FREE)] = { radeon_mem_free, 1, 0 }, 3140 [DRM_IOCTL_NR(DRM_RADEON_VERTEX)] = {radeon_cp_vertex, 1, 0}
3120 [DRM_IOCTL_NR(DRM_RADEON_INIT_HEAP)] = { radeon_mem_init_heap,1, 1 }, 3141 ,
3121 [DRM_IOCTL_NR(DRM_RADEON_IRQ_EMIT)] = { radeon_irq_emit, 1, 0 }, 3142 [DRM_IOCTL_NR(DRM_RADEON_INDICES)] = {radeon_cp_indices, 1, 0}
3122 [DRM_IOCTL_NR(DRM_RADEON_IRQ_WAIT)] = { radeon_irq_wait, 1, 0 }, 3143 ,
3123 [DRM_IOCTL_NR(DRM_RADEON_SETPARAM)] = { radeon_cp_setparam, 1, 0 }, 3144 [DRM_IOCTL_NR(DRM_RADEON_TEXTURE)] = {radeon_cp_texture, 1, 0}
3124 [DRM_IOCTL_NR(DRM_RADEON_SURF_ALLOC)] = { radeon_surface_alloc,1, 0 }, 3145 ,
3125 [DRM_IOCTL_NR(DRM_RADEON_SURF_FREE)] = { radeon_surface_free, 1, 0 } 3146 [DRM_IOCTL_NR(DRM_RADEON_STIPPLE)] = {radeon_cp_stipple, 1, 0}
3147 ,
3148 [DRM_IOCTL_NR(DRM_RADEON_INDIRECT)] = {radeon_cp_indirect, 1, 1}
3149 ,
3150 [DRM_IOCTL_NR(DRM_RADEON_VERTEX2)] = {radeon_cp_vertex2, 1, 0}
3151 ,
3152 [DRM_IOCTL_NR(DRM_RADEON_CMDBUF)] = {radeon_cp_cmdbuf, 1, 0}
3153 ,
3154 [DRM_IOCTL_NR(DRM_RADEON_GETPARAM)] = {radeon_cp_getparam, 1, 0}
3155 ,
3156 [DRM_IOCTL_NR(DRM_RADEON_FLIP)] = {radeon_cp_flip, 1, 0}
3157 ,
3158 [DRM_IOCTL_NR(DRM_RADEON_ALLOC)] = {radeon_mem_alloc, 1, 0}
3159 ,
3160 [DRM_IOCTL_NR(DRM_RADEON_FREE)] = {radeon_mem_free, 1, 0}
3161 ,
3162 [DRM_IOCTL_NR(DRM_RADEON_INIT_HEAP)] = {radeon_mem_init_heap, 1, 1}
3163 ,
3164 [DRM_IOCTL_NR(DRM_RADEON_IRQ_EMIT)] = {radeon_irq_emit, 1, 0}
3165 ,
3166 [DRM_IOCTL_NR(DRM_RADEON_IRQ_WAIT)] = {radeon_irq_wait, 1, 0}
3167 ,
3168 [DRM_IOCTL_NR(DRM_RADEON_SETPARAM)] = {radeon_cp_setparam, 1, 0}
3169 ,
3170 [DRM_IOCTL_NR(DRM_RADEON_SURF_ALLOC)] = {radeon_surface_alloc, 1, 0}
3171 ,
3172 [DRM_IOCTL_NR(DRM_RADEON_SURF_FREE)] = {radeon_surface_free, 1, 0}
3126}; 3173};
3127 3174
3128int radeon_max_ioctl = DRM_ARRAY_SIZE(radeon_ioctls); 3175int radeon_max_ioctl = DRM_ARRAY_SIZE(radeon_ioctls);
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-11 21:46:56 -0500