diff options
author | Dave Airlie <airlied@linux.ie> | 2006-08-19 03:43:52 -0400 |
---|---|---|
committer | Dave Airlie <airlied@linux.ie> | 2006-09-21 15:32:33 -0400 |
commit | b15ec36806ce3b89a2fddce958de9370efb249da (patch) | |
tree | a7c027ffd411eb719123aec77c69355cdf4aded2 /drivers/char/drm/radeon_drv.h | |
parent | d40c8533a5b8ca1887f81ae1c81136f3c40a8488 (diff) |
drm: realign sosme radeon code with drm git tree
this applies some minor cleanups for the radeon driver, to use the
3D flush and reset the AGP flags on X recycle
Signed-off-by: Dave Airlie <airlied@linux.ie>
Diffstat (limited to 'drivers/char/drm/radeon_drv.h')
-rw-r--r-- | drivers/char/drm/radeon_drv.h | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/drivers/char/drm/radeon_drv.h b/drivers/char/drm/radeon_drv.h index 2f51d5147730..40f1dde6b1bb 100644 --- a/drivers/char/drm/radeon_drv.h +++ b/drivers/char/drm/radeon_drv.h | |||
@@ -142,6 +142,7 @@ enum radeon_chip_flags { | |||
142 | CHIP_HAS_HIERZ = 0x00100000UL, | 142 | CHIP_HAS_HIERZ = 0x00100000UL, |
143 | CHIP_IS_PCIE = 0x00200000UL, | 143 | CHIP_IS_PCIE = 0x00200000UL, |
144 | CHIP_NEW_MEMMAP = 0x00400000UL, | 144 | CHIP_NEW_MEMMAP = 0x00400000UL, |
145 | CHIP_IS_PCI = 0x00800000UL, | ||
145 | }; | 146 | }; |
146 | 147 | ||
147 | #define GET_RING_HEAD(dev_priv) (dev_priv->writeback_works ? \ | 148 | #define GET_RING_HEAD(dev_priv) (dev_priv->writeback_works ? \ |
@@ -993,12 +994,12 @@ do { \ | |||
993 | 994 | ||
994 | #define RADEON_FLUSH_CACHE() do { \ | 995 | #define RADEON_FLUSH_CACHE() do { \ |
995 | OUT_RING( CP_PACKET0( RADEON_RB3D_DSTCACHE_CTLSTAT, 0 ) ); \ | 996 | OUT_RING( CP_PACKET0( RADEON_RB3D_DSTCACHE_CTLSTAT, 0 ) ); \ |
996 | OUT_RING( RADEON_RB2D_DC_FLUSH ); \ | 997 | OUT_RING( RADEON_RB3D_DC_FLUSH ); \ |
997 | } while (0) | 998 | } while (0) |
998 | 999 | ||
999 | #define RADEON_PURGE_CACHE() do { \ | 1000 | #define RADEON_PURGE_CACHE() do { \ |
1000 | OUT_RING( CP_PACKET0( RADEON_RB3D_DSTCACHE_CTLSTAT, 0 ) ); \ | 1001 | OUT_RING( CP_PACKET0( RADEON_RB3D_DSTCACHE_CTLSTAT, 0 ) ); \ |
1001 | OUT_RING( RADEON_RB2D_DC_FLUSH_ALL ); \ | 1002 | OUT_RING( RADEON_RB3D_DC_FLUSH_ALL ); \ |
1002 | } while (0) | 1003 | } while (0) |
1003 | 1004 | ||
1004 | #define RADEON_FLUSH_ZCACHE() do { \ | 1005 | #define RADEON_FLUSH_ZCACHE() do { \ |