diff options
author | Alex Deucher <alexdeucher@gmail.com> | 2008-05-27 21:51:12 -0400 |
---|---|---|
committer | Dave Airlie <airlied@redhat.com> | 2008-06-18 21:27:39 -0400 |
commit | 259434acccbc823ee8bc00b2d2689ccccd25e1fd (patch) | |
tree | 0911c4f17d334ac981680b7da684a8c217957fd8 /drivers/char/drm/radeon_drv.h | |
parent | d7463eb41d88a39de2653fd41857c4ccddb8707b (diff) |
drm/radeon: fix pixcache and purge/cache flushing registers
Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/char/drm/radeon_drv.h')
-rw-r--r-- | drivers/char/drm/radeon_drv.h | 43 |
1 files changed, 35 insertions, 8 deletions
diff --git a/drivers/char/drm/radeon_drv.h b/drivers/char/drm/radeon_drv.h index 3063b0fa512f..5e6f4612adba 100644 --- a/drivers/char/drm/radeon_drv.h +++ b/drivers/char/drm/radeon_drv.h | |||
@@ -659,11 +659,18 @@ extern int r300_do_cp_cmdbuf(struct drm_device * dev, | |||
659 | # define RADEON_RB3D_ZC_FREE (1 << 2) | 659 | # define RADEON_RB3D_ZC_FREE (1 << 2) |
660 | # define RADEON_RB3D_ZC_FLUSH_ALL 0x5 | 660 | # define RADEON_RB3D_ZC_FLUSH_ALL 0x5 |
661 | # define RADEON_RB3D_ZC_BUSY (1 << 31) | 661 | # define RADEON_RB3D_ZC_BUSY (1 << 31) |
662 | #define R300_ZB_ZCACHE_CTLSTAT 0x4f18 | ||
663 | # define R300_ZC_FLUSH (1 << 0) | ||
664 | # define R300_ZC_FREE (1 << 1) | ||
665 | # define R300_ZC_FLUSH_ALL 0x3 | ||
666 | # define R300_ZC_BUSY (1 << 31) | ||
662 | #define RADEON_RB3D_DSTCACHE_CTLSTAT 0x325c | 667 | #define RADEON_RB3D_DSTCACHE_CTLSTAT 0x325c |
663 | # define RADEON_RB3D_DC_FLUSH (3 << 0) | 668 | # define RADEON_RB3D_DC_FLUSH (3 << 0) |
664 | # define RADEON_RB3D_DC_FREE (3 << 2) | 669 | # define RADEON_RB3D_DC_FREE (3 << 2) |
665 | # define RADEON_RB3D_DC_FLUSH_ALL 0xf | 670 | # define RADEON_RB3D_DC_FLUSH_ALL 0xf |
666 | # define RADEON_RB3D_DC_BUSY (1 << 31) | 671 | # define RADEON_RB3D_DC_BUSY (1 << 31) |
672 | #define R300_RB3D_DSTCACHE_CTLSTAT 0x4e4c | ||
673 | # define R300_RB3D_DC_FINISH (1 << 4) | ||
667 | #define RADEON_RB3D_ZSTENCILCNTL 0x1c2c | 674 | #define RADEON_RB3D_ZSTENCILCNTL 0x1c2c |
668 | # define RADEON_Z_TEST_MASK (7 << 4) | 675 | # define RADEON_Z_TEST_MASK (7 << 4) |
669 | # define RADEON_Z_TEST_ALWAYS (7 << 4) | 676 | # define RADEON_Z_TEST_ALWAYS (7 << 4) |
@@ -1178,23 +1185,43 @@ do { \ | |||
1178 | } while (0) | 1185 | } while (0) |
1179 | 1186 | ||
1180 | #define RADEON_FLUSH_CACHE() do { \ | 1187 | #define RADEON_FLUSH_CACHE() do { \ |
1181 | OUT_RING( CP_PACKET0( RADEON_RB3D_DSTCACHE_CTLSTAT, 0 ) ); \ | 1188 | if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \ |
1182 | OUT_RING( RADEON_RB3D_DC_FLUSH ); \ | 1189 | OUT_RING(CP_PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); \ |
1190 | OUT_RING(RADEON_RB3D_DC_FLUSH); \ | ||
1191 | } else { \ | ||
1192 | OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); \ | ||
1193 | OUT_RING(RADEON_RB3D_DC_FLUSH); \ | ||
1194 | } \ | ||
1183 | } while (0) | 1195 | } while (0) |
1184 | 1196 | ||
1185 | #define RADEON_PURGE_CACHE() do { \ | 1197 | #define RADEON_PURGE_CACHE() do { \ |
1186 | OUT_RING( CP_PACKET0( RADEON_RB3D_DSTCACHE_CTLSTAT, 0 ) ); \ | 1198 | if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \ |
1187 | OUT_RING( RADEON_RB3D_DC_FLUSH_ALL ); \ | 1199 | OUT_RING(CP_PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); \ |
1200 | OUT_RING(RADEON_RB3D_DC_FLUSH_ALL); \ | ||
1201 | } else { \ | ||
1202 | OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); \ | ||
1203 | OUT_RING(RADEON_RB3D_DC_FLUSH_ALL); \ | ||
1204 | } \ | ||
1188 | } while (0) | 1205 | } while (0) |
1189 | 1206 | ||
1190 | #define RADEON_FLUSH_ZCACHE() do { \ | 1207 | #define RADEON_FLUSH_ZCACHE() do { \ |
1191 | OUT_RING( CP_PACKET0( RADEON_RB3D_ZCACHE_CTLSTAT, 0 ) ); \ | 1208 | if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \ |
1192 | OUT_RING( RADEON_RB3D_ZC_FLUSH ); \ | 1209 | OUT_RING(CP_PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0)); \ |
1210 | OUT_RING(RADEON_RB3D_ZC_FLUSH); \ | ||
1211 | } else { \ | ||
1212 | OUT_RING(CP_PACKET0(R300_ZB_ZCACHE_CTLSTAT, 0)); \ | ||
1213 | OUT_RING(R300_ZC_FLUSH); \ | ||
1214 | } \ | ||
1193 | } while (0) | 1215 | } while (0) |
1194 | 1216 | ||
1195 | #define RADEON_PURGE_ZCACHE() do { \ | 1217 | #define RADEON_PURGE_ZCACHE() do { \ |
1196 | OUT_RING( CP_PACKET0( RADEON_RB3D_ZCACHE_CTLSTAT, 0 ) ); \ | 1218 | if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \ |
1197 | OUT_RING( RADEON_RB3D_ZC_FLUSH_ALL ); \ | 1219 | OUT_RING(CP_PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0)); \ |
1220 | OUT_RING(RADEON_RB3D_ZC_FLUSH_ALL); \ | ||
1221 | } else { \ | ||
1222 | OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); \ | ||
1223 | OUT_RING(R300_ZC_FLUSH_ALL); \ | ||
1224 | } \ | ||
1198 | } while (0) | 1225 | } while (0) |
1199 | 1226 | ||
1200 | /* ================================================================ | 1227 | /* ================================================================ |