diff options
author | Dave Airlie <airlied@linux.ie> | 2006-06-24 02:55:34 -0400 |
---|---|---|
committer | Dave Airlie <airlied@linux.ie> | 2006-06-24 03:32:04 -0400 |
commit | f2a2279ffc0dfd27f6909184a29910e40ae7eebd (patch) | |
tree | e1e9e8a652256a6fd25a595f429f88a39543b3f2 /drivers/char/drm/radeon_drv.h | |
parent | d384ea691fe4ea8c2dd5b9b8d9042eb181776f18 (diff) |
drm: radeon add a tcl state flush before accessing tcl vector space
Do a tcl state flush before accessing tcl vector space. This fixes some
more problems with flickering (bug #6637). drm may not be appropriate
place for this, since doing that flush there might both be overkill and
insufficient in some cases. However, it's hard to figure out when that
flush is needed, so this has to suffice. There does not seem to be a
performance penalty associated with it.
From: Roland Scheidegger (DRM CVS)
Signed-off-by: Dave Airlie <airlied@linux.ie>
Diffstat (limited to 'drivers/char/drm/radeon_drv.h')
-rw-r--r-- | drivers/char/drm/radeon_drv.h | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/drivers/char/drm/radeon_drv.h b/drivers/char/drm/radeon_drv.h index 78345cee8f8e..b2a6f92d1f0f 100644 --- a/drivers/char/drm/radeon_drv.h +++ b/drivers/char/drm/radeon_drv.h | |||
@@ -38,7 +38,7 @@ | |||
38 | 38 | ||
39 | #define DRIVER_NAME "radeon" | 39 | #define DRIVER_NAME "radeon" |
40 | #define DRIVER_DESC "ATI Radeon" | 40 | #define DRIVER_DESC "ATI Radeon" |
41 | #define DRIVER_DATE "20060225" | 41 | #define DRIVER_DATE "20060519" |
42 | 42 | ||
43 | /* Interface history: | 43 | /* Interface history: |
44 | * | 44 | * |
@@ -884,6 +884,8 @@ extern int r300_do_cp_cmdbuf(drm_device_t * dev, DRMFILE filp, | |||
884 | #define RADEON_PP_CUBIC_OFFSET_T1_0 0x1e00 | 884 | #define RADEON_PP_CUBIC_OFFSET_T1_0 0x1e00 |
885 | #define RADEON_PP_CUBIC_OFFSET_T2_0 0x1e14 | 885 | #define RADEON_PP_CUBIC_OFFSET_T2_0 0x1e14 |
886 | 886 | ||
887 | #define RADEON_SE_TCL_STATE_FLUSH 0x2284 | ||
888 | |||
887 | #define SE_VAP_CNTL__TCL_ENA_MASK 0x00000001 | 889 | #define SE_VAP_CNTL__TCL_ENA_MASK 0x00000001 |
888 | #define SE_VAP_CNTL__FORCE_W_TO_ONE_MASK 0x00010000 | 890 | #define SE_VAP_CNTL__FORCE_W_TO_ONE_MASK 0x00010000 |
889 | #define SE_VAP_CNTL__VF_MAX_VTX_NUM__SHIFT 0x00000012 | 891 | #define SE_VAP_CNTL__VF_MAX_VTX_NUM__SHIFT 0x00000012 |