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authorDave Airlie <airlied@linux.ie>2007-11-04 21:50:58 -0500
committerDave Airlie <airlied@redhat.com>2008-02-07 00:09:38 -0500
commitbc5f4523f772cc7629c5c5a46cf4f2a07a5500b8 (patch)
tree8fa2f5194bb05d7e789e5d24a0fe3a7456568146 /drivers/char/drm/radeon_drv.h
parent8562b3f25d6e23c9d9e48a32672944d1e8a2aa97 (diff)
drm: run cleanfile across drm tree
Signed-off-by: Dave Airlie <airlied@linux.ie>
Diffstat (limited to 'drivers/char/drm/radeon_drv.h')
-rw-r--r--drivers/char/drm/radeon_drv.h12
1 files changed, 6 insertions, 6 deletions
diff --git a/drivers/char/drm/radeon_drv.h b/drivers/char/drm/radeon_drv.h
index bfbb60a9298c..aae030844aef 100644
--- a/drivers/char/drm/radeon_drv.h
+++ b/drivers/char/drm/radeon_drv.h
@@ -429,7 +429,7 @@ extern int r300_do_cp_cmdbuf(struct drm_device * dev,
429#define RADEON_PCIE_INDEX 0x0030 429#define RADEON_PCIE_INDEX 0x0030
430#define RADEON_PCIE_DATA 0x0034 430#define RADEON_PCIE_DATA 0x0034
431#define RADEON_PCIE_TX_GART_CNTL 0x10 431#define RADEON_PCIE_TX_GART_CNTL 0x10
432# define RADEON_PCIE_TX_GART_EN (1 << 0) 432# define RADEON_PCIE_TX_GART_EN (1 << 0)
433# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_PASS_THRU (0<<1) 433# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_PASS_THRU (0<<1)
434# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_CLAMP_LO (1<<1) 434# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_CLAMP_LO (1<<1)
435# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD (3<<1) 435# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD (3<<1)
@@ -439,7 +439,7 @@ extern int r300_do_cp_cmdbuf(struct drm_device * dev,
439# define RADEON_PCIE_TX_GART_INVALIDATE_TLB (1<<8) 439# define RADEON_PCIE_TX_GART_INVALIDATE_TLB (1<<8)
440#define RADEON_PCIE_TX_DISCARD_RD_ADDR_LO 0x11 440#define RADEON_PCIE_TX_DISCARD_RD_ADDR_LO 0x11
441#define RADEON_PCIE_TX_DISCARD_RD_ADDR_HI 0x12 441#define RADEON_PCIE_TX_DISCARD_RD_ADDR_HI 0x12
442#define RADEON_PCIE_TX_GART_BASE 0x13 442#define RADEON_PCIE_TX_GART_BASE 0x13
443#define RADEON_PCIE_TX_GART_START_LO 0x14 443#define RADEON_PCIE_TX_GART_START_LO 0x14
444#define RADEON_PCIE_TX_GART_START_HI 0x15 444#define RADEON_PCIE_TX_GART_START_HI 0x15
445#define RADEON_PCIE_TX_GART_END_LO 0x16 445#define RADEON_PCIE_TX_GART_END_LO 0x16
@@ -512,12 +512,12 @@ extern int r300_do_cp_cmdbuf(struct drm_device * dev,
512 512
513#define RADEON_GEN_INT_STATUS 0x0044 513#define RADEON_GEN_INT_STATUS 0x0044
514# define RADEON_CRTC_VBLANK_STAT (1 << 0) 514# define RADEON_CRTC_VBLANK_STAT (1 << 0)
515# define RADEON_CRTC_VBLANK_STAT_ACK (1 << 0) 515# define RADEON_CRTC_VBLANK_STAT_ACK (1 << 0)
516# define RADEON_CRTC2_VBLANK_STAT (1 << 9) 516# define RADEON_CRTC2_VBLANK_STAT (1 << 9)
517# define RADEON_CRTC2_VBLANK_STAT_ACK (1 << 9) 517# define RADEON_CRTC2_VBLANK_STAT_ACK (1 << 9)
518# define RADEON_GUI_IDLE_INT_TEST_ACK (1 << 19) 518# define RADEON_GUI_IDLE_INT_TEST_ACK (1 << 19)
519# define RADEON_SW_INT_TEST (1 << 25) 519# define RADEON_SW_INT_TEST (1 << 25)
520# define RADEON_SW_INT_TEST_ACK (1 << 25) 520# define RADEON_SW_INT_TEST_ACK (1 << 25)
521# define RADEON_SW_INT_FIRE (1 << 26) 521# define RADEON_SW_INT_FIRE (1 << 26)
522 522
523#define RADEON_HOST_PATH_CNTL 0x0130 523#define RADEON_HOST_PATH_CNTL 0x0130
@@ -1133,7 +1133,7 @@ do { \
1133 write, dev_priv->ring.tail ); \ 1133 write, dev_priv->ring.tail ); \
1134 } \ 1134 } \
1135 if (((dev_priv->ring.tail + _nr) & mask) != write) { \ 1135 if (((dev_priv->ring.tail + _nr) & mask) != write) { \
1136 DRM_ERROR( \ 1136 DRM_ERROR( \
1137 "ADVANCE_RING(): mismatch: nr: %x write: %x line: %d\n", \ 1137 "ADVANCE_RING(): mismatch: nr: %x write: %x line: %d\n", \
1138 ((dev_priv->ring.tail + _nr) & mask), \ 1138 ((dev_priv->ring.tail + _nr) & mask), \
1139 write, __LINE__); \ 1139 write, __LINE__); \