diff options
author | Len Brown <len.brown@intel.com> | 2005-09-03 02:44:09 -0400 |
---|---|---|
committer | Len Brown <len.brown@intel.com> | 2005-09-03 02:44:09 -0400 |
commit | 129521dcc94f781890f8f668219ab79f0073ff9f (patch) | |
tree | 9f70707c88da65577f38814fe37b24c4b4957d64 /drivers/char/drm/radeon_drv.h | |
parent | 824b558bbe2c298b165cdb54c33718994dda30bb (diff) | |
parent | f505380ba7b98ec97bf25300c2a58aeae903530b (diff) |
Merge linux-2.6 into linux-acpi-2.6 test
Diffstat (limited to 'drivers/char/drm/radeon_drv.h')
-rw-r--r-- | drivers/char/drm/radeon_drv.h | 30 |
1 files changed, 29 insertions, 1 deletions
diff --git a/drivers/char/drm/radeon_drv.h b/drivers/char/drm/radeon_drv.h index 771aa80a5e8c..f12a963ede18 100644 --- a/drivers/char/drm/radeon_drv.h +++ b/drivers/char/drm/radeon_drv.h | |||
@@ -82,9 +82,10 @@ | |||
82 | * - Add support for r100 cube maps | 82 | * - Add support for r100 cube maps |
83 | * 1.16- Add R200_EMIT_PP_TRI_PERF_CNTL packet to support brilinear | 83 | * 1.16- Add R200_EMIT_PP_TRI_PERF_CNTL packet to support brilinear |
84 | * texture filtering on r200 | 84 | * texture filtering on r200 |
85 | * 1.17- Add initial support for R300 (3D). | ||
85 | */ | 86 | */ |
86 | #define DRIVER_MAJOR 1 | 87 | #define DRIVER_MAJOR 1 |
87 | #define DRIVER_MINOR 16 | 88 | #define DRIVER_MINOR 17 |
88 | #define DRIVER_PATCHLEVEL 0 | 89 | #define DRIVER_PATCHLEVEL 0 |
89 | 90 | ||
90 | #define GET_RING_HEAD(dev_priv) DRM_READ32( (dev_priv)->ring_rptr, 0 ) | 91 | #define GET_RING_HEAD(dev_priv) DRM_READ32( (dev_priv)->ring_rptr, 0 ) |
@@ -106,7 +107,9 @@ enum radeon_family { | |||
106 | CHIP_RV280, | 107 | CHIP_RV280, |
107 | CHIP_R300, | 108 | CHIP_R300, |
108 | CHIP_RS300, | 109 | CHIP_RS300, |
110 | CHIP_R350, | ||
109 | CHIP_RV350, | 111 | CHIP_RV350, |
112 | CHIP_R420, | ||
110 | CHIP_LAST, | 113 | CHIP_LAST, |
111 | }; | 114 | }; |
112 | 115 | ||
@@ -290,6 +293,7 @@ extern int radeon_wait_ring( drm_radeon_private_t *dev_priv, int n ); | |||
290 | extern int radeon_do_cp_idle( drm_radeon_private_t *dev_priv ); | 293 | extern int radeon_do_cp_idle( drm_radeon_private_t *dev_priv ); |
291 | 294 | ||
292 | extern int radeon_driver_preinit(struct drm_device *dev, unsigned long flags); | 295 | extern int radeon_driver_preinit(struct drm_device *dev, unsigned long flags); |
296 | extern int radeon_presetup(struct drm_device *dev); | ||
293 | extern int radeon_driver_postcleanup(struct drm_device *dev); | 297 | extern int radeon_driver_postcleanup(struct drm_device *dev); |
294 | 298 | ||
295 | extern int radeon_mem_alloc( DRM_IOCTL_ARGS ); | 299 | extern int radeon_mem_alloc( DRM_IOCTL_ARGS ); |
@@ -320,6 +324,14 @@ extern int radeon_postcleanup( struct drm_device *dev ); | |||
320 | extern long radeon_compat_ioctl(struct file *filp, unsigned int cmd, | 324 | extern long radeon_compat_ioctl(struct file *filp, unsigned int cmd, |
321 | unsigned long arg); | 325 | unsigned long arg); |
322 | 326 | ||
327 | |||
328 | /* r300_cmdbuf.c */ | ||
329 | extern void r300_init_reg_flags(void); | ||
330 | |||
331 | extern int r300_do_cp_cmdbuf(drm_device_t* dev, DRMFILE filp, | ||
332 | drm_file_t* filp_priv, | ||
333 | drm_radeon_cmd_buffer_t* cmdbuf); | ||
334 | |||
323 | /* Flags for stats.boxes | 335 | /* Flags for stats.boxes |
324 | */ | 336 | */ |
325 | #define RADEON_BOX_DMA_IDLE 0x1 | 337 | #define RADEON_BOX_DMA_IDLE 0x1 |
@@ -357,6 +369,11 @@ extern long radeon_compat_ioctl(struct file *filp, unsigned int cmd, | |||
357 | #define RADEON_CRTC2_OFFSET 0x0324 | 369 | #define RADEON_CRTC2_OFFSET 0x0324 |
358 | #define RADEON_CRTC2_OFFSET_CNTL 0x0328 | 370 | #define RADEON_CRTC2_OFFSET_CNTL 0x0328 |
359 | 371 | ||
372 | #define RADEON_MPP_TB_CONFIG 0x01c0 | ||
373 | #define RADEON_MEM_CNTL 0x0140 | ||
374 | #define RADEON_MEM_SDRAM_MODE_REG 0x0158 | ||
375 | #define RADEON_AGP_BASE 0x0170 | ||
376 | |||
360 | #define RADEON_RB3D_COLOROFFSET 0x1c40 | 377 | #define RADEON_RB3D_COLOROFFSET 0x1c40 |
361 | #define RADEON_RB3D_COLORPITCH 0x1c48 | 378 | #define RADEON_RB3D_COLORPITCH 0x1c48 |
362 | 379 | ||
@@ -651,16 +668,27 @@ extern long radeon_compat_ioctl(struct file *filp, unsigned int cmd, | |||
651 | #define RADEON_CP_PACKET1 0x40000000 | 668 | #define RADEON_CP_PACKET1 0x40000000 |
652 | #define RADEON_CP_PACKET2 0x80000000 | 669 | #define RADEON_CP_PACKET2 0x80000000 |
653 | #define RADEON_CP_PACKET3 0xC0000000 | 670 | #define RADEON_CP_PACKET3 0xC0000000 |
671 | # define RADEON_CP_NOP 0x00001000 | ||
672 | # define RADEON_CP_NEXT_CHAR 0x00001900 | ||
673 | # define RADEON_CP_PLY_NEXTSCAN 0x00001D00 | ||
674 | # define RADEON_CP_SET_SCISSORS 0x00001E00 | ||
675 | /* GEN_INDX_PRIM is unsupported starting with R300 */ | ||
654 | # define RADEON_3D_RNDR_GEN_INDX_PRIM 0x00002300 | 676 | # define RADEON_3D_RNDR_GEN_INDX_PRIM 0x00002300 |
655 | # define RADEON_WAIT_FOR_IDLE 0x00002600 | 677 | # define RADEON_WAIT_FOR_IDLE 0x00002600 |
656 | # define RADEON_3D_DRAW_VBUF 0x00002800 | 678 | # define RADEON_3D_DRAW_VBUF 0x00002800 |
657 | # define RADEON_3D_DRAW_IMMD 0x00002900 | 679 | # define RADEON_3D_DRAW_IMMD 0x00002900 |
658 | # define RADEON_3D_DRAW_INDX 0x00002A00 | 680 | # define RADEON_3D_DRAW_INDX 0x00002A00 |
681 | # define RADEON_CP_LOAD_PALETTE 0x00002C00 | ||
659 | # define RADEON_3D_LOAD_VBPNTR 0x00002F00 | 682 | # define RADEON_3D_LOAD_VBPNTR 0x00002F00 |
660 | # define RADEON_MPEG_IDCT_MACROBLOCK 0x00003000 | 683 | # define RADEON_MPEG_IDCT_MACROBLOCK 0x00003000 |
661 | # define RADEON_MPEG_IDCT_MACROBLOCK_REV 0x00003100 | 684 | # define RADEON_MPEG_IDCT_MACROBLOCK_REV 0x00003100 |
662 | # define RADEON_3D_CLEAR_ZMASK 0x00003200 | 685 | # define RADEON_3D_CLEAR_ZMASK 0x00003200 |
686 | # define RADEON_CP_INDX_BUFFER 0x00003300 | ||
687 | # define RADEON_CP_3D_DRAW_VBUF_2 0x00003400 | ||
688 | # define RADEON_CP_3D_DRAW_IMMD_2 0x00003500 | ||
689 | # define RADEON_CP_3D_DRAW_INDX_2 0x00003600 | ||
663 | # define RADEON_3D_CLEAR_HIZ 0x00003700 | 690 | # define RADEON_3D_CLEAR_HIZ 0x00003700 |
691 | # define RADEON_CP_3D_CLEAR_CMASK 0x00003802 | ||
664 | # define RADEON_CNTL_HOSTDATA_BLT 0x00009400 | 692 | # define RADEON_CNTL_HOSTDATA_BLT 0x00009400 |
665 | # define RADEON_CNTL_PAINT_MULTI 0x00009A00 | 693 | # define RADEON_CNTL_PAINT_MULTI 0x00009A00 |
666 | # define RADEON_CNTL_BITBLT_MULTI 0x00009B00 | 694 | # define RADEON_CNTL_BITBLT_MULTI 0x00009B00 |