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authorDave Airlie <airlied@starflyer.(none)>2006-01-02 05:32:48 -0500
committerDave Airlie <airlied@linux.ie>2006-01-02 05:32:48 -0500
commitd985c1088146607532093d9eaaaf99758f6a4d21 (patch)
treea289ae9a79e694ef1f0cf3b0a153c6d1258b7aa8 /drivers/char/drm/radeon_cp.c
parentb0cae664ebc85f2431c5a7c9e192a2a2ef72ecc7 (diff)
drm: major update from CVS for radeon and core
This patch pull in a lot of changes from CVS to the main core DRM, and updates the radeon driver to 1.21.0 that supports r300 texrect and radeon card type ioctl. Signed-off-by: Dave Airlie <airlied@linux.ie>
Diffstat (limited to 'drivers/char/drm/radeon_cp.c')
-rw-r--r--drivers/char/drm/radeon_cp.c75
1 files changed, 34 insertions, 41 deletions
diff --git a/drivers/char/drm/radeon_cp.c b/drivers/char/drm/radeon_cp.c
index eaa0e2b7c2f8..915665c7fe7c 100644
--- a/drivers/char/drm/radeon_cp.c
+++ b/drivers/char/drm/radeon_cp.c
@@ -824,7 +824,7 @@ static int RADEON_READ_PLL(drm_device_t * dev, int addr)
824 return RADEON_READ(RADEON_CLOCK_CNTL_DATA); 824 return RADEON_READ(RADEON_CLOCK_CNTL_DATA);
825} 825}
826 826
827static int RADEON_READ_PCIE(drm_radeon_private_t * dev_priv, int addr) 827static int RADEON_READ_PCIE(drm_radeon_private_t *dev_priv, int addr)
828{ 828{
829 RADEON_WRITE8(RADEON_PCIE_INDEX, addr & 0xff); 829 RADEON_WRITE8(RADEON_PCIE_INDEX, addr & 0xff);
830 return RADEON_READ(RADEON_PCIE_DATA); 830 return RADEON_READ(RADEON_PCIE_DATA);
@@ -1125,7 +1125,7 @@ static void radeon_cp_init_ring_buffer(drm_device_t * dev,
1125 | (dev_priv->fb_location >> 16)); 1125 | (dev_priv->fb_location >> 16));
1126 1126
1127#if __OS_HAS_AGP 1127#if __OS_HAS_AGP
1128 if (!dev_priv->is_pci) { 1128 if (dev_priv->flags & CHIP_IS_AGP) {
1129 RADEON_WRITE(RADEON_MC_AGP_LOCATION, 1129 RADEON_WRITE(RADEON_MC_AGP_LOCATION,
1130 (((dev_priv->gart_vm_start - 1 + 1130 (((dev_priv->gart_vm_start - 1 +
1131 dev_priv->gart_size) & 0xffff0000) | 1131 dev_priv->gart_size) & 0xffff0000) |
@@ -1152,7 +1152,7 @@ static void radeon_cp_init_ring_buffer(drm_device_t * dev,
1152 dev_priv->ring.tail = cur_read_ptr; 1152 dev_priv->ring.tail = cur_read_ptr;
1153 1153
1154#if __OS_HAS_AGP 1154#if __OS_HAS_AGP
1155 if (!dev_priv->is_pci) { 1155 if (dev_priv->flags & CHIP_IS_AGP) {
1156 /* set RADEON_AGP_BASE here instead of relying on X from user space */ 1156 /* set RADEON_AGP_BASE here instead of relying on X from user space */
1157 RADEON_WRITE(RADEON_AGP_BASE, (unsigned int)dev->agp->base); 1157 RADEON_WRITE(RADEON_AGP_BASE, (unsigned int)dev->agp->base);
1158 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR, 1158 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR,
@@ -1278,13 +1278,15 @@ static void radeon_set_pciegart(drm_radeon_private_t * dev_priv, int on)
1278/* Enable or disable PCI GART on the chip */ 1278/* Enable or disable PCI GART on the chip */
1279static void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on) 1279static void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on)
1280{ 1280{
1281 u32 tmp = RADEON_READ(RADEON_AIC_CNTL); 1281 u32 tmp;
1282 1282
1283 if (dev_priv->flags & CHIP_IS_PCIE) { 1283 if (dev_priv->flags & CHIP_IS_PCIE) {
1284 radeon_set_pciegart(dev_priv, on); 1284 radeon_set_pciegart(dev_priv, on);
1285 return; 1285 return;
1286 } 1286 }
1287 1287
1288 tmp = RADEON_READ(RADEON_AIC_CNTL);
1289
1288 if (on) { 1290 if (on) {
1289 RADEON_WRITE(RADEON_AIC_CNTL, 1291 RADEON_WRITE(RADEON_AIC_CNTL,
1290 tmp | RADEON_PCIGART_TRANSLATE_EN); 1292 tmp | RADEON_PCIGART_TRANSLATE_EN);
@@ -1311,14 +1313,18 @@ static void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on)
1311 1313
1312static int radeon_do_init_cp(drm_device_t * dev, drm_radeon_init_t * init) 1314static int radeon_do_init_cp(drm_device_t * dev, drm_radeon_init_t * init)
1313{ 1315{
1314 drm_radeon_private_t *dev_priv = dev->dev_private;; 1316 drm_radeon_private_t *dev_priv = dev->dev_private;
1317
1315 DRM_DEBUG("\n"); 1318 DRM_DEBUG("\n");
1316 1319
1317 dev_priv->is_pci = init->is_pci; 1320 if (init->is_pci && (dev_priv->flags & CHIP_IS_AGP))
1321 {
1322 DRM_DEBUG("Forcing AGP card to PCI mode\n");
1323 dev_priv->flags &= ~CHIP_IS_AGP;
1324 }
1318 1325
1319 if (dev_priv->is_pci && !dev->sg) { 1326 if ((!(dev_priv->flags & CHIP_IS_AGP)) && !dev->sg) {
1320 DRM_ERROR("PCI GART memory not allocated!\n"); 1327 DRM_ERROR("PCI GART memory not allocated!\n");
1321 dev->dev_private = (void *)dev_priv;
1322 radeon_do_cleanup_cp(dev); 1328 radeon_do_cleanup_cp(dev);
1323 return DRM_ERR(EINVAL); 1329 return DRM_ERR(EINVAL);
1324 } 1330 }
@@ -1327,12 +1333,11 @@ static int radeon_do_init_cp(drm_device_t * dev, drm_radeon_init_t * init)
1327 if (dev_priv->usec_timeout < 1 || 1333 if (dev_priv->usec_timeout < 1 ||
1328 dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT) { 1334 dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT) {
1329 DRM_DEBUG("TIMEOUT problem!\n"); 1335 DRM_DEBUG("TIMEOUT problem!\n");
1330 dev->dev_private = (void *)dev_priv;
1331 radeon_do_cleanup_cp(dev); 1336 radeon_do_cleanup_cp(dev);
1332 return DRM_ERR(EINVAL); 1337 return DRM_ERR(EINVAL);
1333 } 1338 }
1334 1339
1335 switch (init->func) { 1340 switch(init->func) {
1336 case RADEON_INIT_R200_CP: 1341 case RADEON_INIT_R200_CP:
1337 dev_priv->microcode_version = UCODE_R200; 1342 dev_priv->microcode_version = UCODE_R200;
1338 break; 1343 break;
@@ -1353,7 +1358,6 @@ static int radeon_do_init_cp(drm_device_t * dev, drm_radeon_init_t * init)
1353 if ((init->cp_mode != RADEON_CSQ_PRIBM_INDDIS) && 1358 if ((init->cp_mode != RADEON_CSQ_PRIBM_INDDIS) &&
1354 (init->cp_mode != RADEON_CSQ_PRIBM_INDBM)) { 1359 (init->cp_mode != RADEON_CSQ_PRIBM_INDBM)) {
1355 DRM_DEBUG("BAD cp_mode (%x)!\n", init->cp_mode); 1360 DRM_DEBUG("BAD cp_mode (%x)!\n", init->cp_mode);
1356 dev->dev_private = (void *)dev_priv;
1357 radeon_do_cleanup_cp(dev); 1361 radeon_do_cleanup_cp(dev);
1358 return DRM_ERR(EINVAL); 1362 return DRM_ERR(EINVAL);
1359 } 1363 }
@@ -1416,8 +1420,6 @@ static int radeon_do_init_cp(drm_device_t * dev, drm_radeon_init_t * init)
1416 1420
1417 DRM_GETSAREA(); 1421 DRM_GETSAREA();
1418 1422
1419 dev_priv->fb_offset = init->fb_offset;
1420 dev_priv->mmio_offset = init->mmio_offset;
1421 dev_priv->ring_offset = init->ring_offset; 1423 dev_priv->ring_offset = init->ring_offset;
1422 dev_priv->ring_rptr_offset = init->ring_rptr_offset; 1424 dev_priv->ring_rptr_offset = init->ring_rptr_offset;
1423 dev_priv->buffers_offset = init->buffers_offset; 1425 dev_priv->buffers_offset = init->buffers_offset;
@@ -1425,29 +1427,19 @@ static int radeon_do_init_cp(drm_device_t * dev, drm_radeon_init_t * init)
1425 1427
1426 if (!dev_priv->sarea) { 1428 if (!dev_priv->sarea) {
1427 DRM_ERROR("could not find sarea!\n"); 1429 DRM_ERROR("could not find sarea!\n");
1428 dev->dev_private = (void *)dev_priv;
1429 radeon_do_cleanup_cp(dev); 1430 radeon_do_cleanup_cp(dev);
1430 return DRM_ERR(EINVAL); 1431 return DRM_ERR(EINVAL);
1431 } 1432 }
1432 1433
1433 dev_priv->mmio = drm_core_findmap(dev, init->mmio_offset);
1434 if (!dev_priv->mmio) {
1435 DRM_ERROR("could not find mmio region!\n");
1436 dev->dev_private = (void *)dev_priv;
1437 radeon_do_cleanup_cp(dev);
1438 return DRM_ERR(EINVAL);
1439 }
1440 dev_priv->cp_ring = drm_core_findmap(dev, init->ring_offset); 1434 dev_priv->cp_ring = drm_core_findmap(dev, init->ring_offset);
1441 if (!dev_priv->cp_ring) { 1435 if (!dev_priv->cp_ring) {
1442 DRM_ERROR("could not find cp ring region!\n"); 1436 DRM_ERROR("could not find cp ring region!\n");
1443 dev->dev_private = (void *)dev_priv;
1444 radeon_do_cleanup_cp(dev); 1437 radeon_do_cleanup_cp(dev);
1445 return DRM_ERR(EINVAL); 1438 return DRM_ERR(EINVAL);
1446 } 1439 }
1447 dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset); 1440 dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset);
1448 if (!dev_priv->ring_rptr) { 1441 if (!dev_priv->ring_rptr) {
1449 DRM_ERROR("could not find ring read pointer!\n"); 1442 DRM_ERROR("could not find ring read pointer!\n");
1450 dev->dev_private = (void *)dev_priv;
1451 radeon_do_cleanup_cp(dev); 1443 radeon_do_cleanup_cp(dev);
1452 return DRM_ERR(EINVAL); 1444 return DRM_ERR(EINVAL);
1453 } 1445 }
@@ -1455,7 +1447,6 @@ static int radeon_do_init_cp(drm_device_t * dev, drm_radeon_init_t * init)
1455 dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset); 1447 dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset);
1456 if (!dev->agp_buffer_map) { 1448 if (!dev->agp_buffer_map) {
1457 DRM_ERROR("could not find dma buffer region!\n"); 1449 DRM_ERROR("could not find dma buffer region!\n");
1458 dev->dev_private = (void *)dev_priv;
1459 radeon_do_cleanup_cp(dev); 1450 radeon_do_cleanup_cp(dev);
1460 return DRM_ERR(EINVAL); 1451 return DRM_ERR(EINVAL);
1461 } 1452 }
@@ -1465,7 +1456,6 @@ static int radeon_do_init_cp(drm_device_t * dev, drm_radeon_init_t * init)
1465 drm_core_findmap(dev, init->gart_textures_offset); 1456 drm_core_findmap(dev, init->gart_textures_offset);
1466 if (!dev_priv->gart_textures) { 1457 if (!dev_priv->gart_textures) {
1467 DRM_ERROR("could not find GART texture region!\n"); 1458 DRM_ERROR("could not find GART texture region!\n");
1468 dev->dev_private = (void *)dev_priv;
1469 radeon_do_cleanup_cp(dev); 1459 radeon_do_cleanup_cp(dev);
1470 return DRM_ERR(EINVAL); 1460 return DRM_ERR(EINVAL);
1471 } 1461 }
@@ -1476,7 +1466,7 @@ static int radeon_do_init_cp(drm_device_t * dev, drm_radeon_init_t * init)
1476 init->sarea_priv_offset); 1466 init->sarea_priv_offset);
1477 1467
1478#if __OS_HAS_AGP 1468#if __OS_HAS_AGP
1479 if (!dev_priv->is_pci) { 1469 if (dev_priv->flags & CHIP_IS_AGP) {
1480 drm_core_ioremap(dev_priv->cp_ring, dev); 1470 drm_core_ioremap(dev_priv->cp_ring, dev);
1481 drm_core_ioremap(dev_priv->ring_rptr, dev); 1471 drm_core_ioremap(dev_priv->ring_rptr, dev);
1482 drm_core_ioremap(dev->agp_buffer_map, dev); 1472 drm_core_ioremap(dev->agp_buffer_map, dev);
@@ -1484,7 +1474,6 @@ static int radeon_do_init_cp(drm_device_t * dev, drm_radeon_init_t * init)
1484 !dev_priv->ring_rptr->handle || 1474 !dev_priv->ring_rptr->handle ||
1485 !dev->agp_buffer_map->handle) { 1475 !dev->agp_buffer_map->handle) {
1486 DRM_ERROR("could not find ioremap agp regions!\n"); 1476 DRM_ERROR("could not find ioremap agp regions!\n");
1487 dev->dev_private = (void *)dev_priv;
1488 radeon_do_cleanup_cp(dev); 1477 radeon_do_cleanup_cp(dev);
1489 return DRM_ERR(EINVAL); 1478 return DRM_ERR(EINVAL);
1490 } 1479 }
@@ -1525,7 +1514,7 @@ static int radeon_do_init_cp(drm_device_t * dev, drm_radeon_init_t * init)
1525 + RADEON_READ(RADEON_CONFIG_APER_SIZE); 1514 + RADEON_READ(RADEON_CONFIG_APER_SIZE);
1526 1515
1527#if __OS_HAS_AGP 1516#if __OS_HAS_AGP
1528 if (!dev_priv->is_pci) 1517 if (dev_priv->flags & CHIP_IS_AGP)
1529 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset 1518 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1530 - dev->agp->base 1519 - dev->agp->base
1531 + dev_priv->gart_vm_start); 1520 + dev_priv->gart_vm_start);
@@ -1551,7 +1540,7 @@ static int radeon_do_init_cp(drm_device_t * dev, drm_radeon_init_t * init)
1551 dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK; 1540 dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK;
1552 1541
1553#if __OS_HAS_AGP 1542#if __OS_HAS_AGP
1554 if (!dev_priv->is_pci) { 1543 if (dev_priv->flags & CHIP_IS_AGP) {
1555 /* Turn off PCI GART */ 1544 /* Turn off PCI GART */
1556 radeon_set_pcigart(dev_priv, 0); 1545 radeon_set_pcigart(dev_priv, 0);
1557 } else 1546 } else
@@ -1593,7 +1582,6 @@ static int radeon_do_init_cp(drm_device_t * dev, drm_radeon_init_t * init)
1593 1582
1594 if (!drm_ati_pcigart_init(dev, &dev_priv->gart_info)) { 1583 if (!drm_ati_pcigart_init(dev, &dev_priv->gart_info)) {
1595 DRM_ERROR("failed to init PCI GART!\n"); 1584 DRM_ERROR("failed to init PCI GART!\n");
1596 dev->dev_private = (void *)dev_priv;
1597 radeon_do_cleanup_cp(dev); 1585 radeon_do_cleanup_cp(dev);
1598 return DRM_ERR(ENOMEM); 1586 return DRM_ERR(ENOMEM);
1599 } 1587 }
@@ -1607,8 +1595,6 @@ static int radeon_do_init_cp(drm_device_t * dev, drm_radeon_init_t * init)
1607 1595
1608 dev_priv->last_buf = 0; 1596 dev_priv->last_buf = 0;
1609 1597
1610 dev->dev_private = (void *)dev_priv;
1611
1612 radeon_do_engine_reset(dev); 1598 radeon_do_engine_reset(dev);
1613 1599
1614 return 0; 1600 return 0;
@@ -1627,11 +1613,15 @@ static int radeon_do_cleanup_cp(drm_device_t * dev)
1627 drm_irq_uninstall(dev); 1613 drm_irq_uninstall(dev);
1628 1614
1629#if __OS_HAS_AGP 1615#if __OS_HAS_AGP
1630 if (!dev_priv->is_pci) { 1616 if (dev_priv->flags & CHIP_IS_AGP) {
1631 if (dev_priv->cp_ring != NULL) 1617 if (dev_priv->cp_ring != NULL) {
1632 drm_core_ioremapfree(dev_priv->cp_ring, dev); 1618 drm_core_ioremapfree(dev_priv->cp_ring, dev);
1633 if (dev_priv->ring_rptr != NULL) 1619 dev_priv->cp_ring = NULL;
1620 }
1621 if (dev_priv->ring_rptr != NULL) {
1634 drm_core_ioremapfree(dev_priv->ring_rptr, dev); 1622 drm_core_ioremapfree(dev_priv->ring_rptr, dev);
1623 dev_priv->ring_rptr = NULL;
1624 }
1635 if (dev->agp_buffer_map != NULL) { 1625 if (dev->agp_buffer_map != NULL) {
1636 drm_core_ioremapfree(dev->agp_buffer_map, dev); 1626 drm_core_ioremapfree(dev->agp_buffer_map, dev);
1637 dev->agp_buffer_map = NULL; 1627 dev->agp_buffer_map = NULL;
@@ -1639,16 +1629,20 @@ static int radeon_do_cleanup_cp(drm_device_t * dev)
1639 } else 1629 } else
1640#endif 1630#endif
1641 { 1631 {
1642 if (dev_priv->gart_info.bus_addr) 1632
1633 if (dev_priv->gart_info.bus_addr) {
1634 /* Turn off PCI GART */
1635 radeon_set_pcigart(dev_priv, 0);
1643 if (!drm_ati_pcigart_cleanup(dev, &dev_priv->gart_info)) 1636 if (!drm_ati_pcigart_cleanup(dev, &dev_priv->gart_info))
1644 DRM_ERROR("failed to cleanup PCI GART!\n"); 1637 DRM_ERROR("failed to cleanup PCI GART!\n");
1638 }
1645 1639
1646 if (dev_priv->gart_info.gart_table_location == DRM_ATI_GART_FB) { 1640 if (dev_priv->gart_info.gart_table_location == DRM_ATI_GART_FB)
1641 {
1647 drm_core_ioremapfree(&dev_priv->gart_info.mapping, dev); 1642 drm_core_ioremapfree(&dev_priv->gart_info.mapping, dev);
1648 dev_priv->gart_info.addr = 0; 1643 dev_priv->gart_info.addr = 0;
1649 } 1644 }
1650 } 1645 }
1651
1652 /* only clear to the start of flags */ 1646 /* only clear to the start of flags */
1653 memset(dev_priv, 0, offsetof(drm_radeon_private_t, flags)); 1647 memset(dev_priv, 0, offsetof(drm_radeon_private_t, flags));
1654 1648
@@ -1674,7 +1668,7 @@ static int radeon_do_resume_cp(drm_device_t * dev)
1674 DRM_DEBUG("Starting radeon_do_resume_cp()\n"); 1668 DRM_DEBUG("Starting radeon_do_resume_cp()\n");
1675 1669
1676#if __OS_HAS_AGP 1670#if __OS_HAS_AGP
1677 if (!dev_priv->is_pci) { 1671 if (dev_priv->flags & CHIP_IS_AGP) {
1678 /* Turn off PCI GART */ 1672 /* Turn off PCI GART */
1679 radeon_set_pcigart(dev_priv, 0); 1673 radeon_set_pcigart(dev_priv, 0);
1680 } else 1674 } else
@@ -2138,7 +2132,7 @@ int radeon_driver_load(struct drm_device *dev, unsigned long flags)
2138 dev_priv->flags |= CHIP_IS_PCIE; 2132 dev_priv->flags |= CHIP_IS_PCIE;
2139 2133
2140 DRM_DEBUG("%s card detected\n", 2134 DRM_DEBUG("%s card detected\n",
2141 ((dev_priv->flags & CHIP_IS_AGP) ? "AGP" : "PCI")); 2135 ((dev_priv->flags & CHIP_IS_AGP) ? "AGP" : (((dev_priv->flags & CHIP_IS_PCIE) ? "PCIE" : "PCI"))));
2142 return ret; 2136 return ret;
2143} 2137}
2144 2138
@@ -2171,7 +2165,6 @@ int radeon_driver_unload(struct drm_device *dev)
2171 drm_radeon_private_t *dev_priv = dev->dev_private; 2165 drm_radeon_private_t *dev_priv = dev->dev_private;
2172 2166
2173 DRM_DEBUG("\n"); 2167 DRM_DEBUG("\n");
2174
2175 drm_free(dev_priv, sizeof(*dev_priv), DRM_MEM_DRIVER); 2168 drm_free(dev_priv, sizeof(*dev_priv), DRM_MEM_DRIVER);
2176 2169
2177 dev->dev_private = NULL; 2170 dev->dev_private = NULL;