diff options
| author | Alex Deucher <alexdeucher@gmail.com> | 2008-05-27 21:54:06 -0400 |
|---|---|---|
| committer | Dave Airlie <airlied@redhat.com> | 2008-06-18 21:27:39 -0400 |
| commit | d396db321bcaec54345e7e9e87cea8482d6ae3a8 (patch) | |
| tree | abc725575d0b2acb00e01b8261a118f04db1c9a8 /drivers/char/drm/radeon_cp.c | |
| parent | 259434acccbc823ee8bc00b2d2689ccccd25e1fd (diff) | |
drm/radeon: fixup radeon_do_engine_reset
Cleanup do engine reset for different chip families.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/char/drm/radeon_cp.c')
| -rw-r--r-- | drivers/char/drm/radeon_cp.c | 49 |
1 files changed, 26 insertions, 23 deletions
diff --git a/drivers/char/drm/radeon_cp.c b/drivers/char/drm/radeon_cp.c index 8fce12e73403..77bd90f6d414 100644 --- a/drivers/char/drm/radeon_cp.c +++ b/drivers/char/drm/radeon_cp.c | |||
| @@ -418,12 +418,13 @@ static void radeon_do_cp_stop(drm_radeon_private_t * dev_priv) | |||
| 418 | static int radeon_do_engine_reset(struct drm_device * dev) | 418 | static int radeon_do_engine_reset(struct drm_device * dev) |
| 419 | { | 419 | { |
| 420 | drm_radeon_private_t *dev_priv = dev->dev_private; | 420 | drm_radeon_private_t *dev_priv = dev->dev_private; |
| 421 | u32 clock_cntl_index, mclk_cntl, rbbm_soft_reset; | 421 | u32 clock_cntl_index = 0, mclk_cntl = 0, rbbm_soft_reset; |
| 422 | DRM_DEBUG("\n"); | 422 | DRM_DEBUG("\n"); |
| 423 | 423 | ||
| 424 | radeon_do_pixcache_flush(dev_priv); | 424 | radeon_do_pixcache_flush(dev_priv); |
| 425 | 425 | ||
| 426 | if ((dev_priv->flags & RADEON_FAMILY_MASK) < CHIP_RV515) { | 426 | if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) { |
| 427 | /* may need something similar for newer chips */ | ||
| 427 | clock_cntl_index = RADEON_READ(RADEON_CLOCK_CNTL_INDEX); | 428 | clock_cntl_index = RADEON_READ(RADEON_CLOCK_CNTL_INDEX); |
| 428 | mclk_cntl = RADEON_READ_PLL(dev, RADEON_MCLK_CNTL); | 429 | mclk_cntl = RADEON_READ_PLL(dev, RADEON_MCLK_CNTL); |
| 429 | 430 | ||
| @@ -434,28 +435,30 @@ static int radeon_do_engine_reset(struct drm_device * dev) | |||
| 434 | RADEON_FORCEON_YCLKB | | 435 | RADEON_FORCEON_YCLKB | |
| 435 | RADEON_FORCEON_MC | | 436 | RADEON_FORCEON_MC | |
| 436 | RADEON_FORCEON_AIC)); | 437 | RADEON_FORCEON_AIC)); |
| 438 | } | ||
| 437 | 439 | ||
| 438 | rbbm_soft_reset = RADEON_READ(RADEON_RBBM_SOFT_RESET); | 440 | rbbm_soft_reset = RADEON_READ(RADEON_RBBM_SOFT_RESET); |
| 439 | 441 | ||
| 440 | RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset | | 442 | RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset | |
| 441 | RADEON_SOFT_RESET_CP | | 443 | RADEON_SOFT_RESET_CP | |
| 442 | RADEON_SOFT_RESET_HI | | 444 | RADEON_SOFT_RESET_HI | |
| 443 | RADEON_SOFT_RESET_SE | | 445 | RADEON_SOFT_RESET_SE | |
| 444 | RADEON_SOFT_RESET_RE | | 446 | RADEON_SOFT_RESET_RE | |
| 445 | RADEON_SOFT_RESET_PP | | 447 | RADEON_SOFT_RESET_PP | |
| 446 | RADEON_SOFT_RESET_E2 | | 448 | RADEON_SOFT_RESET_E2 | |
| 447 | RADEON_SOFT_RESET_RB)); | 449 | RADEON_SOFT_RESET_RB)); |
| 448 | RADEON_READ(RADEON_RBBM_SOFT_RESET); | 450 | RADEON_READ(RADEON_RBBM_SOFT_RESET); |
| 449 | RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset & | 451 | RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset & |
| 450 | ~(RADEON_SOFT_RESET_CP | | 452 | ~(RADEON_SOFT_RESET_CP | |
| 451 | RADEON_SOFT_RESET_HI | | 453 | RADEON_SOFT_RESET_HI | |
| 452 | RADEON_SOFT_RESET_SE | | 454 | RADEON_SOFT_RESET_SE | |
| 453 | RADEON_SOFT_RESET_RE | | 455 | RADEON_SOFT_RESET_RE | |
| 454 | RADEON_SOFT_RESET_PP | | 456 | RADEON_SOFT_RESET_PP | |
| 455 | RADEON_SOFT_RESET_E2 | | 457 | RADEON_SOFT_RESET_E2 | |
| 456 | RADEON_SOFT_RESET_RB))); | 458 | RADEON_SOFT_RESET_RB))); |
| 457 | RADEON_READ(RADEON_RBBM_SOFT_RESET); | 459 | RADEON_READ(RADEON_RBBM_SOFT_RESET); |
| 458 | 460 | ||
| 461 | if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) { | ||
| 459 | RADEON_WRITE_PLL(RADEON_MCLK_CNTL, mclk_cntl); | 462 | RADEON_WRITE_PLL(RADEON_MCLK_CNTL, mclk_cntl); |
| 460 | RADEON_WRITE(RADEON_CLOCK_CNTL_INDEX, clock_cntl_index); | 463 | RADEON_WRITE(RADEON_CLOCK_CNTL_INDEX, clock_cntl_index); |
| 461 | RADEON_WRITE(RADEON_RBBM_SOFT_RESET, rbbm_soft_reset); | 464 | RADEON_WRITE(RADEON_RBBM_SOFT_RESET, rbbm_soft_reset); |