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authorLinus Torvalds <torvalds@g5.osdl.org>2005-11-02 00:49:07 -0500
committerLinus Torvalds <torvalds@g5.osdl.org>2005-11-02 00:49:07 -0500
commitd8762748cae4f85b3201c0304969d993b42d5258 (patch)
tree559819d9b17e5ee305d705cf9f31ac5de2aab54a /drivers/char/drm/radeon_cp.c
parentce4633704038f9bf39f20c10691747d6fc127bf4 (diff)
parenta4e62fa031a9681477207b08391c3a5c5c831ce7 (diff)
Merge master.kernel.org:/pub/scm/linux/kernel/git/airlied/drm-2.6
Manual fixups for some clashes due to re-indenting.
Diffstat (limited to 'drivers/char/drm/radeon_cp.c')
-rw-r--r--drivers/char/drm/radeon_cp.c2483
1 files changed, 1280 insertions, 1203 deletions
diff --git a/drivers/char/drm/radeon_cp.c b/drivers/char/drm/radeon_cp.c
index 12ef13ff04ca..03839ea31092 100644
--- a/drivers/char/drm/radeon_cp.c
+++ b/drivers/char/drm/radeon_cp.c
@@ -36,788 +36,787 @@
36 36
37#define RADEON_FIFO_DEBUG 0 37#define RADEON_FIFO_DEBUG 0
38 38
39static int radeon_do_cleanup_cp( drm_device_t *dev ); 39static int radeon_do_cleanup_cp(drm_device_t * dev);
40 40
41/* CP microcode (from ATI) */ 41/* CP microcode (from ATI) */
42static u32 R200_cp_microcode[][2] = { 42static u32 R200_cp_microcode[][2] = {
43 { 0x21007000, 0000000000 }, 43 {0x21007000, 0000000000},
44 { 0x20007000, 0000000000 }, 44 {0x20007000, 0000000000},
45 { 0x000000ab, 0x00000004 }, 45 {0x000000ab, 0x00000004},
46 { 0x000000af, 0x00000004 }, 46 {0x000000af, 0x00000004},
47 { 0x66544a49, 0000000000 }, 47 {0x66544a49, 0000000000},
48 { 0x49494174, 0000000000 }, 48 {0x49494174, 0000000000},
49 { 0x54517d83, 0000000000 }, 49 {0x54517d83, 0000000000},
50 { 0x498d8b64, 0000000000 }, 50 {0x498d8b64, 0000000000},
51 { 0x49494949, 0000000000 }, 51 {0x49494949, 0000000000},
52 { 0x49da493c, 0000000000 }, 52 {0x49da493c, 0000000000},
53 { 0x49989898, 0000000000 }, 53 {0x49989898, 0000000000},
54 { 0xd34949d5, 0000000000 }, 54 {0xd34949d5, 0000000000},
55 { 0x9dc90e11, 0000000000 }, 55 {0x9dc90e11, 0000000000},
56 { 0xce9b9b9b, 0000000000 }, 56 {0xce9b9b9b, 0000000000},
57 { 0x000f0000, 0x00000016 }, 57 {0x000f0000, 0x00000016},
58 { 0x352e232c, 0000000000 }, 58 {0x352e232c, 0000000000},
59 { 0x00000013, 0x00000004 }, 59 {0x00000013, 0x00000004},
60 { 0x000f0000, 0x00000016 }, 60 {0x000f0000, 0x00000016},
61 { 0x352e272c, 0000000000 }, 61 {0x352e272c, 0000000000},
62 { 0x000f0001, 0x00000016 }, 62 {0x000f0001, 0x00000016},
63 { 0x3239362f, 0000000000 }, 63 {0x3239362f, 0000000000},
64 { 0x000077ef, 0x00000002 }, 64 {0x000077ef, 0x00000002},
65 { 0x00061000, 0x00000002 }, 65 {0x00061000, 0x00000002},
66 { 0x00000020, 0x0000001a }, 66 {0x00000020, 0x0000001a},
67 { 0x00004000, 0x0000001e }, 67 {0x00004000, 0x0000001e},
68 { 0x00061000, 0x00000002 }, 68 {0x00061000, 0x00000002},
69 { 0x00000020, 0x0000001a }, 69 {0x00000020, 0x0000001a},
70 { 0x00004000, 0x0000001e }, 70 {0x00004000, 0x0000001e},
71 { 0x00061000, 0x00000002 }, 71 {0x00061000, 0x00000002},
72 { 0x00000020, 0x0000001a }, 72 {0x00000020, 0x0000001a},
73 { 0x00004000, 0x0000001e }, 73 {0x00004000, 0x0000001e},
74 { 0x00000016, 0x00000004 }, 74 {0x00000016, 0x00000004},
75 { 0x0003802a, 0x00000002 }, 75 {0x0003802a, 0x00000002},
76 { 0x040067e0, 0x00000002 }, 76 {0x040067e0, 0x00000002},
77 { 0x00000016, 0x00000004 }, 77 {0x00000016, 0x00000004},
78 { 0x000077e0, 0x00000002 }, 78 {0x000077e0, 0x00000002},
79 { 0x00065000, 0x00000002 }, 79 {0x00065000, 0x00000002},
80 { 0x000037e1, 0x00000002 }, 80 {0x000037e1, 0x00000002},
81 { 0x040067e1, 0x00000006 }, 81 {0x040067e1, 0x00000006},
82 { 0x000077e0, 0x00000002 }, 82 {0x000077e0, 0x00000002},
83 { 0x000077e1, 0x00000002 }, 83 {0x000077e1, 0x00000002},
84 { 0x000077e1, 0x00000006 }, 84 {0x000077e1, 0x00000006},
85 { 0xffffffff, 0000000000 }, 85 {0xffffffff, 0000000000},
86 { 0x10000000, 0000000000 }, 86 {0x10000000, 0000000000},
87 { 0x0003802a, 0x00000002 }, 87 {0x0003802a, 0x00000002},
88 { 0x040067e0, 0x00000006 }, 88 {0x040067e0, 0x00000006},
89 { 0x00007675, 0x00000002 }, 89 {0x00007675, 0x00000002},
90 { 0x00007676, 0x00000002 }, 90 {0x00007676, 0x00000002},
91 { 0x00007677, 0x00000002 }, 91 {0x00007677, 0x00000002},
92 { 0x00007678, 0x00000006 }, 92 {0x00007678, 0x00000006},
93 { 0x0003802b, 0x00000002 }, 93 {0x0003802b, 0x00000002},
94 { 0x04002676, 0x00000002 }, 94 {0x04002676, 0x00000002},
95 { 0x00007677, 0x00000002 }, 95 {0x00007677, 0x00000002},
96 { 0x00007678, 0x00000006 }, 96 {0x00007678, 0x00000006},
97 { 0x0000002e, 0x00000018 }, 97 {0x0000002e, 0x00000018},
98 { 0x0000002e, 0x00000018 }, 98 {0x0000002e, 0x00000018},
99 { 0000000000, 0x00000006 }, 99 {0000000000, 0x00000006},
100 { 0x0000002f, 0x00000018 }, 100 {0x0000002f, 0x00000018},
101 { 0x0000002f, 0x00000018 }, 101 {0x0000002f, 0x00000018},
102 { 0000000000, 0x00000006 }, 102 {0000000000, 0x00000006},
103 { 0x01605000, 0x00000002 }, 103 {0x01605000, 0x00000002},
104 { 0x00065000, 0x00000002 }, 104 {0x00065000, 0x00000002},
105 { 0x00098000, 0x00000002 }, 105 {0x00098000, 0x00000002},
106 { 0x00061000, 0x00000002 }, 106 {0x00061000, 0x00000002},
107 { 0x64c0603d, 0x00000004 }, 107 {0x64c0603d, 0x00000004},
108 { 0x00080000, 0x00000016 }, 108 {0x00080000, 0x00000016},
109 { 0000000000, 0000000000 }, 109 {0000000000, 0000000000},
110 { 0x0400251d, 0x00000002 }, 110 {0x0400251d, 0x00000002},
111 { 0x00007580, 0x00000002 }, 111 {0x00007580, 0x00000002},
112 { 0x00067581, 0x00000002 }, 112 {0x00067581, 0x00000002},
113 { 0x04002580, 0x00000002 }, 113 {0x04002580, 0x00000002},
114 { 0x00067581, 0x00000002 }, 114 {0x00067581, 0x00000002},
115 { 0x00000046, 0x00000004 }, 115 {0x00000046, 0x00000004},
116 { 0x00005000, 0000000000 }, 116 {0x00005000, 0000000000},
117 { 0x00061000, 0x00000002 }, 117 {0x00061000, 0x00000002},
118 { 0x0000750e, 0x00000002 }, 118 {0x0000750e, 0x00000002},
119 { 0x00019000, 0x00000002 }, 119 {0x00019000, 0x00000002},
120 { 0x00011055, 0x00000014 }, 120 {0x00011055, 0x00000014},
121 { 0x00000055, 0x00000012 }, 121 {0x00000055, 0x00000012},
122 { 0x0400250f, 0x00000002 }, 122 {0x0400250f, 0x00000002},
123 { 0x0000504a, 0x00000004 }, 123 {0x0000504a, 0x00000004},
124 { 0x00007565, 0x00000002 }, 124 {0x00007565, 0x00000002},
125 { 0x00007566, 0x00000002 }, 125 {0x00007566, 0x00000002},
126 { 0x00000051, 0x00000004 }, 126 {0x00000051, 0x00000004},
127 { 0x01e655b4, 0x00000002 }, 127 {0x01e655b4, 0x00000002},
128 { 0x4401b0dc, 0x00000002 }, 128 {0x4401b0dc, 0x00000002},
129 { 0x01c110dc, 0x00000002 }, 129 {0x01c110dc, 0x00000002},
130 { 0x2666705d, 0x00000018 }, 130 {0x2666705d, 0x00000018},
131 { 0x040c2565, 0x00000002 }, 131 {0x040c2565, 0x00000002},
132 { 0x0000005d, 0x00000018 }, 132 {0x0000005d, 0x00000018},
133 { 0x04002564, 0x00000002 }, 133 {0x04002564, 0x00000002},
134 { 0x00007566, 0x00000002 }, 134 {0x00007566, 0x00000002},
135 { 0x00000054, 0x00000004 }, 135 {0x00000054, 0x00000004},
136 { 0x00401060, 0x00000008 }, 136 {0x00401060, 0x00000008},
137 { 0x00101000, 0x00000002 }, 137 {0x00101000, 0x00000002},
138 { 0x000d80ff, 0x00000002 }, 138 {0x000d80ff, 0x00000002},
139 { 0x00800063, 0x00000008 }, 139 {0x00800063, 0x00000008},
140 { 0x000f9000, 0x00000002 }, 140 {0x000f9000, 0x00000002},
141 { 0x000e00ff, 0x00000002 }, 141 {0x000e00ff, 0x00000002},
142 { 0000000000, 0x00000006 }, 142 {0000000000, 0x00000006},
143 { 0x00000080, 0x00000018 }, 143 {0x00000080, 0x00000018},
144 { 0x00000054, 0x00000004 }, 144 {0x00000054, 0x00000004},
145 { 0x00007576, 0x00000002 }, 145 {0x00007576, 0x00000002},
146 { 0x00065000, 0x00000002 }, 146 {0x00065000, 0x00000002},
147 { 0x00009000, 0x00000002 }, 147 {0x00009000, 0x00000002},
148 { 0x00041000, 0x00000002 }, 148 {0x00041000, 0x00000002},
149 { 0x0c00350e, 0x00000002 }, 149 {0x0c00350e, 0x00000002},
150 { 0x00049000, 0x00000002 }, 150 {0x00049000, 0x00000002},
151 { 0x00051000, 0x00000002 }, 151 {0x00051000, 0x00000002},
152 { 0x01e785f8, 0x00000002 }, 152 {0x01e785f8, 0x00000002},
153 { 0x00200000, 0x00000002 }, 153 {0x00200000, 0x00000002},
154 { 0x00600073, 0x0000000c }, 154 {0x00600073, 0x0000000c},
155 { 0x00007563, 0x00000002 }, 155 {0x00007563, 0x00000002},
156 { 0x006075f0, 0x00000021 }, 156 {0x006075f0, 0x00000021},
157 { 0x20007068, 0x00000004 }, 157 {0x20007068, 0x00000004},
158 { 0x00005068, 0x00000004 }, 158 {0x00005068, 0x00000004},
159 { 0x00007576, 0x00000002 }, 159 {0x00007576, 0x00000002},
160 { 0x00007577, 0x00000002 }, 160 {0x00007577, 0x00000002},
161 { 0x0000750e, 0x00000002 }, 161 {0x0000750e, 0x00000002},
162 { 0x0000750f, 0x00000002 }, 162 {0x0000750f, 0x00000002},
163 { 0x00a05000, 0x00000002 }, 163 {0x00a05000, 0x00000002},
164 { 0x00600076, 0x0000000c }, 164 {0x00600076, 0x0000000c},
165 { 0x006075f0, 0x00000021 }, 165 {0x006075f0, 0x00000021},
166 { 0x000075f8, 0x00000002 }, 166 {0x000075f8, 0x00000002},
167 { 0x00000076, 0x00000004 }, 167 {0x00000076, 0x00000004},
168 { 0x000a750e, 0x00000002 }, 168 {0x000a750e, 0x00000002},
169 { 0x0020750f, 0x00000002 }, 169 {0x0020750f, 0x00000002},
170 { 0x00600079, 0x00000004 }, 170 {0x00600079, 0x00000004},
171 { 0x00007570, 0x00000002 }, 171 {0x00007570, 0x00000002},
172 { 0x00007571, 0x00000002 }, 172 {0x00007571, 0x00000002},
173 { 0x00007572, 0x00000006 }, 173 {0x00007572, 0x00000006},
174 { 0x00005000, 0x00000002 }, 174 {0x00005000, 0x00000002},
175 { 0x00a05000, 0x00000002 }, 175 {0x00a05000, 0x00000002},
176 { 0x00007568, 0x00000002 }, 176 {0x00007568, 0x00000002},
177 { 0x00061000, 0x00000002 }, 177 {0x00061000, 0x00000002},
178 { 0x00000084, 0x0000000c }, 178 {0x00000084, 0x0000000c},
179 { 0x00058000, 0x00000002 }, 179 {0x00058000, 0x00000002},
180 { 0x0c607562, 0x00000002 }, 180 {0x0c607562, 0x00000002},
181 { 0x00000086, 0x00000004 }, 181 {0x00000086, 0x00000004},
182 { 0x00600085, 0x00000004 }, 182 {0x00600085, 0x00000004},
183 { 0x400070dd, 0000000000 }, 183 {0x400070dd, 0000000000},
184 { 0x000380dd, 0x00000002 }, 184 {0x000380dd, 0x00000002},
185 { 0x00000093, 0x0000001c }, 185 {0x00000093, 0x0000001c},
186 { 0x00065095, 0x00000018 }, 186 {0x00065095, 0x00000018},
187 { 0x040025bb, 0x00000002 }, 187 {0x040025bb, 0x00000002},
188 { 0x00061096, 0x00000018 }, 188 {0x00061096, 0x00000018},
189 { 0x040075bc, 0000000000 }, 189 {0x040075bc, 0000000000},
190 { 0x000075bb, 0x00000002 }, 190 {0x000075bb, 0x00000002},
191 { 0x000075bc, 0000000000 }, 191 {0x000075bc, 0000000000},
192 { 0x00090000, 0x00000006 }, 192 {0x00090000, 0x00000006},
193 { 0x00090000, 0x00000002 }, 193 {0x00090000, 0x00000002},
194 { 0x000d8002, 0x00000006 }, 194 {0x000d8002, 0x00000006},
195 { 0x00005000, 0x00000002 }, 195 {0x00005000, 0x00000002},
196 { 0x00007821, 0x00000002 }, 196 {0x00007821, 0x00000002},
197 { 0x00007800, 0000000000 }, 197 {0x00007800, 0000000000},
198 { 0x00007821, 0x00000002 }, 198 {0x00007821, 0x00000002},
199 { 0x00007800, 0000000000 }, 199 {0x00007800, 0000000000},
200 { 0x01665000, 0x00000002 }, 200 {0x01665000, 0x00000002},
201 { 0x000a0000, 0x00000002 }, 201 {0x000a0000, 0x00000002},
202 { 0x000671cc, 0x00000002 }, 202 {0x000671cc, 0x00000002},
203 { 0x0286f1cd, 0x00000002 }, 203 {0x0286f1cd, 0x00000002},
204 { 0x000000a3, 0x00000010 }, 204 {0x000000a3, 0x00000010},
205 { 0x21007000, 0000000000 }, 205 {0x21007000, 0000000000},
206 { 0x000000aa, 0x0000001c }, 206 {0x000000aa, 0x0000001c},
207 { 0x00065000, 0x00000002 }, 207 {0x00065000, 0x00000002},
208 { 0x000a0000, 0x00000002 }, 208 {0x000a0000, 0x00000002},
209 { 0x00061000, 0x00000002 }, 209 {0x00061000, 0x00000002},
210 { 0x000b0000, 0x00000002 }, 210 {0x000b0000, 0x00000002},
211 { 0x38067000, 0x00000002 }, 211 {0x38067000, 0x00000002},
212 { 0x000a00a6, 0x00000004 }, 212 {0x000a00a6, 0x00000004},
213 { 0x20007000, 0000000000 }, 213 {0x20007000, 0000000000},
214 { 0x01200000, 0x00000002 }, 214 {0x01200000, 0x00000002},
215 { 0x20077000, 0x00000002 }, 215 {0x20077000, 0x00000002},
216 { 0x01200000, 0x00000002 }, 216 {0x01200000, 0x00000002},
217 { 0x20007000, 0000000000 }, 217 {0x20007000, 0000000000},
218 { 0x00061000, 0x00000002 }, 218 {0x00061000, 0x00000002},
219 { 0x0120751b, 0x00000002 }, 219 {0x0120751b, 0x00000002},
220 { 0x8040750a, 0x00000002 }, 220 {0x8040750a, 0x00000002},
221 { 0x8040750b, 0x00000002 }, 221 {0x8040750b, 0x00000002},
222 { 0x00110000, 0x00000002 }, 222 {0x00110000, 0x00000002},
223 { 0x000380dd, 0x00000002 }, 223 {0x000380dd, 0x00000002},
224 { 0x000000bd, 0x0000001c }, 224 {0x000000bd, 0x0000001c},
225 { 0x00061096, 0x00000018 }, 225 {0x00061096, 0x00000018},
226 { 0x844075bd, 0x00000002 }, 226 {0x844075bd, 0x00000002},
227 { 0x00061095, 0x00000018 }, 227 {0x00061095, 0x00000018},
228 { 0x840075bb, 0x00000002 }, 228 {0x840075bb, 0x00000002},
229 { 0x00061096, 0x00000018 }, 229 {0x00061096, 0x00000018},
230 { 0x844075bc, 0x00000002 }, 230 {0x844075bc, 0x00000002},
231 { 0x000000c0, 0x00000004 }, 231 {0x000000c0, 0x00000004},
232 { 0x804075bd, 0x00000002 }, 232 {0x804075bd, 0x00000002},
233 { 0x800075bb, 0x00000002 }, 233 {0x800075bb, 0x00000002},
234 { 0x804075bc, 0x00000002 }, 234 {0x804075bc, 0x00000002},
235 { 0x00108000, 0x00000002 }, 235 {0x00108000, 0x00000002},
236 { 0x01400000, 0x00000002 }, 236 {0x01400000, 0x00000002},
237 { 0x006000c4, 0x0000000c }, 237 {0x006000c4, 0x0000000c},
238 { 0x20c07000, 0x00000020 }, 238 {0x20c07000, 0x00000020},
239 { 0x000000c6, 0x00000012 }, 239 {0x000000c6, 0x00000012},
240 { 0x00800000, 0x00000006 }, 240 {0x00800000, 0x00000006},
241 { 0x0080751d, 0x00000006 }, 241 {0x0080751d, 0x00000006},
242 { 0x000025bb, 0x00000002 }, 242 {0x000025bb, 0x00000002},
243 { 0x000040c0, 0x00000004 }, 243 {0x000040c0, 0x00000004},
244 { 0x0000775c, 0x00000002 }, 244 {0x0000775c, 0x00000002},
245 { 0x00a05000, 0x00000002 }, 245 {0x00a05000, 0x00000002},
246 { 0x00661000, 0x00000002 }, 246 {0x00661000, 0x00000002},
247 { 0x0460275d, 0x00000020 }, 247 {0x0460275d, 0x00000020},
248 { 0x00004000, 0000000000 }, 248 {0x00004000, 0000000000},
249 { 0x00007999, 0x00000002 }, 249 {0x00007999, 0x00000002},
250 { 0x00a05000, 0x00000002 }, 250 {0x00a05000, 0x00000002},
251 { 0x00661000, 0x00000002 }, 251 {0x00661000, 0x00000002},
252 { 0x0460299b, 0x00000020 }, 252 {0x0460299b, 0x00000020},
253 { 0x00004000, 0000000000 }, 253 {0x00004000, 0000000000},
254 { 0x01e00830, 0x00000002 }, 254 {0x01e00830, 0x00000002},
255 { 0x21007000, 0000000000 }, 255 {0x21007000, 0000000000},
256 { 0x00005000, 0x00000002 }, 256 {0x00005000, 0x00000002},
257 { 0x00038042, 0x00000002 }, 257 {0x00038042, 0x00000002},
258 { 0x040025e0, 0x00000002 }, 258 {0x040025e0, 0x00000002},
259 { 0x000075e1, 0000000000 }, 259 {0x000075e1, 0000000000},
260 { 0x00000001, 0000000000 }, 260 {0x00000001, 0000000000},
261 { 0x000380d9, 0x00000002 }, 261 {0x000380d9, 0x00000002},
262 { 0x04007394, 0000000000 }, 262 {0x04007394, 0000000000},
263 { 0000000000, 0000000000 }, 263 {0000000000, 0000000000},
264 { 0000000000, 0000000000 }, 264 {0000000000, 0000000000},
265 { 0000000000, 0000000000 }, 265 {0000000000, 0000000000},
266 { 0000000000, 0000000000 }, 266 {0000000000, 0000000000},
267 { 0000000000, 0000000000 }, 267 {0000000000, 0000000000},
268 { 0000000000, 0000000000 }, 268 {0000000000, 0000000000},
269 { 0000000000, 0000000000 }, 269 {0000000000, 0000000000},
270 { 0000000000, 0000000000 }, 270 {0000000000, 0000000000},
271 { 0000000000, 0000000000 }, 271 {0000000000, 0000000000},
272 { 0000000000, 0000000000 }, 272 {0000000000, 0000000000},
273 { 0000000000, 0000000000 }, 273 {0000000000, 0000000000},
274 { 0000000000, 0000000000 }, 274 {0000000000, 0000000000},
275 { 0000000000, 0000000000 }, 275 {0000000000, 0000000000},
276 { 0000000000, 0000000000 }, 276 {0000000000, 0000000000},
277 { 0000000000, 0000000000 }, 277 {0000000000, 0000000000},
278 { 0000000000, 0000000000 }, 278 {0000000000, 0000000000},
279 { 0000000000, 0000000000 }, 279 {0000000000, 0000000000},
280 { 0000000000, 0000000000 }, 280 {0000000000, 0000000000},
281 { 0000000000, 0000000000 }, 281 {0000000000, 0000000000},
282 { 0000000000, 0000000000 }, 282 {0000000000, 0000000000},
283 { 0000000000, 0000000000 }, 283 {0000000000, 0000000000},
284 { 0000000000, 0000000000 }, 284 {0000000000, 0000000000},
285 { 0000000000, 0000000000 }, 285 {0000000000, 0000000000},
286 { 0000000000, 0000000000 }, 286 {0000000000, 0000000000},
287 { 0000000000, 0000000000 }, 287 {0000000000, 0000000000},
288 { 0000000000, 0000000000 }, 288 {0000000000, 0000000000},
289 { 0000000000, 0000000000 }, 289 {0000000000, 0000000000},
290 { 0000000000, 0000000000 }, 290 {0000000000, 0000000000},
291 { 0000000000, 0000000000 }, 291 {0000000000, 0000000000},
292 { 0000000000, 0000000000 }, 292 {0000000000, 0000000000},
293 { 0000000000, 0000000000 }, 293 {0000000000, 0000000000},
294 { 0000000000, 0000000000 }, 294 {0000000000, 0000000000},
295 { 0000000000, 0000000000 }, 295 {0000000000, 0000000000},
296 { 0000000000, 0000000000 }, 296 {0000000000, 0000000000},
297 { 0000000000, 0000000000 }, 297 {0000000000, 0000000000},
298 { 0000000000, 0000000000 }, 298 {0000000000, 0000000000},
299}; 299};
300 300
301
302static u32 radeon_cp_microcode[][2] = { 301static u32 radeon_cp_microcode[][2] = {
303 { 0x21007000, 0000000000 }, 302 {0x21007000, 0000000000},
304 { 0x20007000, 0000000000 }, 303 {0x20007000, 0000000000},
305 { 0x000000b4, 0x00000004 }, 304 {0x000000b4, 0x00000004},
306 { 0x000000b8, 0x00000004 }, 305 {0x000000b8, 0x00000004},
307 { 0x6f5b4d4c, 0000000000 }, 306 {0x6f5b4d4c, 0000000000},
308 { 0x4c4c427f, 0000000000 }, 307 {0x4c4c427f, 0000000000},
309 { 0x5b568a92, 0000000000 }, 308 {0x5b568a92, 0000000000},
310 { 0x4ca09c6d, 0000000000 }, 309 {0x4ca09c6d, 0000000000},
311 { 0xad4c4c4c, 0000000000 }, 310 {0xad4c4c4c, 0000000000},
312 { 0x4ce1af3d, 0000000000 }, 311 {0x4ce1af3d, 0000000000},
313 { 0xd8afafaf, 0000000000 }, 312 {0xd8afafaf, 0000000000},
314 { 0xd64c4cdc, 0000000000 }, 313 {0xd64c4cdc, 0000000000},
315 { 0x4cd10d10, 0000000000 }, 314 {0x4cd10d10, 0000000000},
316 { 0x000f0000, 0x00000016 }, 315 {0x000f0000, 0x00000016},
317 { 0x362f242d, 0000000000 }, 316 {0x362f242d, 0000000000},
318 { 0x00000012, 0x00000004 }, 317 {0x00000012, 0x00000004},
319 { 0x000f0000, 0x00000016 }, 318 {0x000f0000, 0x00000016},
320 { 0x362f282d, 0000000000 }, 319 {0x362f282d, 0000000000},
321 { 0x000380e7, 0x00000002 }, 320 {0x000380e7, 0x00000002},
322 { 0x04002c97, 0x00000002 }, 321 {0x04002c97, 0x00000002},
323 { 0x000f0001, 0x00000016 }, 322 {0x000f0001, 0x00000016},
324 { 0x333a3730, 0000000000 }, 323 {0x333a3730, 0000000000},
325 { 0x000077ef, 0x00000002 }, 324 {0x000077ef, 0x00000002},
326 { 0x00061000, 0x00000002 }, 325 {0x00061000, 0x00000002},
327 { 0x00000021, 0x0000001a }, 326 {0x00000021, 0x0000001a},
328 { 0x00004000, 0x0000001e }, 327 {0x00004000, 0x0000001e},
329 { 0x00061000, 0x00000002 }, 328 {0x00061000, 0x00000002},
330 { 0x00000021, 0x0000001a }, 329 {0x00000021, 0x0000001a},
331 { 0x00004000, 0x0000001e }, 330 {0x00004000, 0x0000001e},
332 { 0x00061000, 0x00000002 }, 331 {0x00061000, 0x00000002},
333 { 0x00000021, 0x0000001a }, 332 {0x00000021, 0x0000001a},
334 { 0x00004000, 0x0000001e }, 333 {0x00004000, 0x0000001e},
335 { 0x00000017, 0x00000004 }, 334 {0x00000017, 0x00000004},
336 { 0x0003802b, 0x00000002 }, 335 {0x0003802b, 0x00000002},
337 { 0x040067e0, 0x00000002 }, 336 {0x040067e0, 0x00000002},
338 { 0x00000017, 0x00000004 }, 337 {0x00000017, 0x00000004},
339 { 0x000077e0, 0x00000002 }, 338 {0x000077e0, 0x00000002},
340 { 0x00065000, 0x00000002 }, 339 {0x00065000, 0x00000002},
341 { 0x000037e1, 0x00000002 }, 340 {0x000037e1, 0x00000002},
342 { 0x040067e1, 0x00000006 }, 341 {0x040067e1, 0x00000006},
343 { 0x000077e0, 0x00000002 }, 342 {0x000077e0, 0x00000002},
344 { 0x000077e1, 0x00000002 }, 343 {0x000077e1, 0x00000002},
345 { 0x000077e1, 0x00000006 }, 344 {0x000077e1, 0x00000006},
346 { 0xffffffff, 0000000000 }, 345 {0xffffffff, 0000000000},
347 { 0x10000000, 0000000000 }, 346 {0x10000000, 0000000000},
348 { 0x0003802b, 0x00000002 }, 347 {0x0003802b, 0x00000002},
349 { 0x040067e0, 0x00000006 }, 348 {0x040067e0, 0x00000006},
350 { 0x00007675, 0x00000002 }, 349 {0x00007675, 0x00000002},
351 { 0x00007676, 0x00000002 }, 350 {0x00007676, 0x00000002},
352 { 0x00007677, 0x00000002 }, 351 {0x00007677, 0x00000002},
353 { 0x00007678, 0x00000006 }, 352 {0x00007678, 0x00000006},
354 { 0x0003802c, 0x00000002 }, 353 {0x0003802c, 0x00000002},
355 { 0x04002676, 0x00000002 }, 354 {0x04002676, 0x00000002},
356 { 0x00007677, 0x00000002 }, 355 {0x00007677, 0x00000002},
357 { 0x00007678, 0x00000006 }, 356 {0x00007678, 0x00000006},
358 { 0x0000002f, 0x00000018 }, 357 {0x0000002f, 0x00000018},
359 { 0x0000002f, 0x00000018 }, 358 {0x0000002f, 0x00000018},
360 { 0000000000, 0x00000006 }, 359 {0000000000, 0x00000006},
361 { 0x00000030, 0x00000018 }, 360 {0x00000030, 0x00000018},
362 { 0x00000030, 0x00000018 }, 361 {0x00000030, 0x00000018},
363 { 0000000000, 0x00000006 }, 362 {0000000000, 0x00000006},
364 { 0x01605000, 0x00000002 }, 363 {0x01605000, 0x00000002},
365 { 0x00065000, 0x00000002 }, 364 {0x00065000, 0x00000002},
366 { 0x00098000, 0x00000002 }, 365 {0x00098000, 0x00000002},
367 { 0x00061000, 0x00000002 }, 366 {0x00061000, 0x00000002},
368 { 0x64c0603e, 0x00000004 }, 367 {0x64c0603e, 0x00000004},
369 { 0x000380e6, 0x00000002 }, 368 {0x000380e6, 0x00000002},
370 { 0x040025c5, 0x00000002 }, 369 {0x040025c5, 0x00000002},
371 { 0x00080000, 0x00000016 }, 370 {0x00080000, 0x00000016},
372 { 0000000000, 0000000000 }, 371 {0000000000, 0000000000},
373 { 0x0400251d, 0x00000002 }, 372 {0x0400251d, 0x00000002},
374 { 0x00007580, 0x00000002 }, 373 {0x00007580, 0x00000002},
375 { 0x00067581, 0x00000002 }, 374 {0x00067581, 0x00000002},
376 { 0x04002580, 0x00000002 }, 375 {0x04002580, 0x00000002},
377 { 0x00067581, 0x00000002 }, 376 {0x00067581, 0x00000002},
378 { 0x00000049, 0x00000004 }, 377 {0x00000049, 0x00000004},
379 { 0x00005000, 0000000000 }, 378 {0x00005000, 0000000000},
380 { 0x000380e6, 0x00000002 }, 379 {0x000380e6, 0x00000002},
381 { 0x040025c5, 0x00000002 }, 380 {0x040025c5, 0x00000002},
382 { 0x00061000, 0x00000002 }, 381 {0x00061000, 0x00000002},
383 { 0x0000750e, 0x00000002 }, 382 {0x0000750e, 0x00000002},
384 { 0x00019000, 0x00000002 }, 383 {0x00019000, 0x00000002},
385 { 0x00011055, 0x00000014 }, 384 {0x00011055, 0x00000014},
386 { 0x00000055, 0x00000012 }, 385 {0x00000055, 0x00000012},
387 { 0x0400250f, 0x00000002 }, 386 {0x0400250f, 0x00000002},
388 { 0x0000504f, 0x00000004 }, 387 {0x0000504f, 0x00000004},
389 { 0x000380e6, 0x00000002 }, 388 {0x000380e6, 0x00000002},
390 { 0x040025c5, 0x00000002 }, 389 {0x040025c5, 0x00000002},
391 { 0x00007565, 0x00000002 }, 390 {0x00007565, 0x00000002},
392 { 0x00007566, 0x00000002 }, 391 {0x00007566, 0x00000002},
393 { 0x00000058, 0x00000004 }, 392 {0x00000058, 0x00000004},
394 { 0x000380e6, 0x00000002 }, 393 {0x000380e6, 0x00000002},
395 { 0x040025c5, 0x00000002 }, 394 {0x040025c5, 0x00000002},
396 { 0x01e655b4, 0x00000002 }, 395 {0x01e655b4, 0x00000002},
397 { 0x4401b0e4, 0x00000002 }, 396 {0x4401b0e4, 0x00000002},
398 { 0x01c110e4, 0x00000002 }, 397 {0x01c110e4, 0x00000002},
399 { 0x26667066, 0x00000018 }, 398 {0x26667066, 0x00000018},
400 { 0x040c2565, 0x00000002 }, 399 {0x040c2565, 0x00000002},
401 { 0x00000066, 0x00000018 }, 400 {0x00000066, 0x00000018},
402 { 0x04002564, 0x00000002 }, 401 {0x04002564, 0x00000002},
403 { 0x00007566, 0x00000002 }, 402 {0x00007566, 0x00000002},
404 { 0x0000005d, 0x00000004 }, 403 {0x0000005d, 0x00000004},
405 { 0x00401069, 0x00000008 }, 404 {0x00401069, 0x00000008},
406 { 0x00101000, 0x00000002 }, 405 {0x00101000, 0x00000002},
407 { 0x000d80ff, 0x00000002 }, 406 {0x000d80ff, 0x00000002},
408 { 0x0080006c, 0x00000008 }, 407 {0x0080006c, 0x00000008},
409 { 0x000f9000, 0x00000002 }, 408 {0x000f9000, 0x00000002},
410 { 0x000e00ff, 0x00000002 }, 409 {0x000e00ff, 0x00000002},
411 { 0000000000, 0x00000006 }, 410 {0000000000, 0x00000006},
412 { 0x0000008f, 0x00000018 }, 411 {0x0000008f, 0x00000018},
413 { 0x0000005b, 0x00000004 }, 412 {0x0000005b, 0x00000004},
414 { 0x000380e6, 0x00000002 }, 413 {0x000380e6, 0x00000002},
415 { 0x040025c5, 0x00000002 }, 414 {0x040025c5, 0x00000002},
416 { 0x00007576, 0x00000002 }, 415 {0x00007576, 0x00000002},
417 { 0x00065000, 0x00000002 }, 416 {0x00065000, 0x00000002},
418 { 0x00009000, 0x00000002 }, 417 {0x00009000, 0x00000002},
419 { 0x00041000, 0x00000002 }, 418 {0x00041000, 0x00000002},
420 { 0x0c00350e, 0x00000002 }, 419 {0x0c00350e, 0x00000002},
421 { 0x00049000, 0x00000002 }, 420 {0x00049000, 0x00000002},
422 { 0x00051000, 0x00000002 }, 421 {0x00051000, 0x00000002},
423 { 0x01e785f8, 0x00000002 }, 422 {0x01e785f8, 0x00000002},
424 { 0x00200000, 0x00000002 }, 423 {0x00200000, 0x00000002},
425 { 0x0060007e, 0x0000000c }, 424 {0x0060007e, 0x0000000c},
426 { 0x00007563, 0x00000002 }, 425 {0x00007563, 0x00000002},
427 { 0x006075f0, 0x00000021 }, 426 {0x006075f0, 0x00000021},
428 { 0x20007073, 0x00000004 }, 427 {0x20007073, 0x00000004},
429 { 0x00005073, 0x00000004 }, 428 {0x00005073, 0x00000004},
430 { 0x000380e6, 0x00000002 }, 429 {0x000380e6, 0x00000002},
431 { 0x040025c5, 0x00000002 }, 430 {0x040025c5, 0x00000002},
432 { 0x00007576, 0x00000002 }, 431 {0x00007576, 0x00000002},
433 { 0x00007577, 0x00000002 }, 432 {0x00007577, 0x00000002},
434 { 0x0000750e, 0x00000002 }, 433 {0x0000750e, 0x00000002},
435 { 0x0000750f, 0x00000002 }, 434 {0x0000750f, 0x00000002},
436 { 0x00a05000, 0x00000002 }, 435 {0x00a05000, 0x00000002},
437 { 0x00600083, 0x0000000c }, 436 {0x00600083, 0x0000000c},
438 { 0x006075f0, 0x00000021 }, 437 {0x006075f0, 0x00000021},
439 { 0x000075f8, 0x00000002 }, 438 {0x000075f8, 0x00000002},
440 { 0x00000083, 0x00000004 }, 439 {0x00000083, 0x00000004},
441 { 0x000a750e, 0x00000002 }, 440 {0x000a750e, 0x00000002},
442 { 0x000380e6, 0x00000002 }, 441 {0x000380e6, 0x00000002},
443 { 0x040025c5, 0x00000002 }, 442 {0x040025c5, 0x00000002},
444 { 0x0020750f, 0x00000002 }, 443 {0x0020750f, 0x00000002},
445 { 0x00600086, 0x00000004 }, 444 {0x00600086, 0x00000004},
446 { 0x00007570, 0x00000002 }, 445 {0x00007570, 0x00000002},
447 { 0x00007571, 0x00000002 }, 446 {0x00007571, 0x00000002},
448 { 0x00007572, 0x00000006 }, 447 {0x00007572, 0x00000006},
449 { 0x000380e6, 0x00000002 }, 448 {0x000380e6, 0x00000002},
450 { 0x040025c5, 0x00000002 }, 449 {0x040025c5, 0x00000002},
451 { 0x00005000, 0x00000002 }, 450 {0x00005000, 0x00000002},
452 { 0x00a05000, 0x00000002 }, 451 {0x00a05000, 0x00000002},
453 { 0x00007568, 0x00000002 }, 452 {0x00007568, 0x00000002},
454 { 0x00061000, 0x00000002 }, 453 {0x00061000, 0x00000002},
455 { 0x00000095, 0x0000000c }, 454 {0x00000095, 0x0000000c},
456 { 0x00058000, 0x00000002 }, 455 {0x00058000, 0x00000002},
457 { 0x0c607562, 0x00000002 }, 456 {0x0c607562, 0x00000002},
458 { 0x00000097, 0x00000004 }, 457 {0x00000097, 0x00000004},
459 { 0x000380e6, 0x00000002 }, 458 {0x000380e6, 0x00000002},
460 { 0x040025c5, 0x00000002 }, 459 {0x040025c5, 0x00000002},
461 { 0x00600096, 0x00000004 }, 460 {0x00600096, 0x00000004},
462 { 0x400070e5, 0000000000 }, 461 {0x400070e5, 0000000000},
463 { 0x000380e6, 0x00000002 }, 462 {0x000380e6, 0x00000002},
464 { 0x040025c5, 0x00000002 }, 463 {0x040025c5, 0x00000002},
465 { 0x000380e5, 0x00000002 }, 464 {0x000380e5, 0x00000002},
466 { 0x000000a8, 0x0000001c }, 465 {0x000000a8, 0x0000001c},
467 { 0x000650aa, 0x00000018 }, 466 {0x000650aa, 0x00000018},
468 { 0x040025bb, 0x00000002 }, 467 {0x040025bb, 0x00000002},
469 { 0x000610ab, 0x00000018 }, 468 {0x000610ab, 0x00000018},
470 { 0x040075bc, 0000000000 }, 469 {0x040075bc, 0000000000},
471 { 0x000075bb, 0x00000002 }, 470 {0x000075bb, 0x00000002},
472 { 0x000075bc, 0000000000 }, 471 {0x000075bc, 0000000000},
473 { 0x00090000, 0x00000006 }, 472 {0x00090000, 0x00000006},
474 { 0x00090000, 0x00000002 }, 473 {0x00090000, 0x00000002},
475 { 0x000d8002, 0x00000006 }, 474 {0x000d8002, 0x00000006},
476 { 0x00007832, 0x00000002 }, 475 {0x00007832, 0x00000002},
477 { 0x00005000, 0x00000002 }, 476 {0x00005000, 0x00000002},
478 { 0x000380e7, 0x00000002 }, 477 {0x000380e7, 0x00000002},
479 { 0x04002c97, 0x00000002 }, 478 {0x04002c97, 0x00000002},
480 { 0x00007820, 0x00000002 }, 479 {0x00007820, 0x00000002},
481 { 0x00007821, 0x00000002 }, 480 {0x00007821, 0x00000002},
482 { 0x00007800, 0000000000 }, 481 {0x00007800, 0000000000},
483 { 0x01200000, 0x00000002 }, 482 {0x01200000, 0x00000002},
484 { 0x20077000, 0x00000002 }, 483 {0x20077000, 0x00000002},
485 { 0x01200000, 0x00000002 }, 484 {0x01200000, 0x00000002},
486 { 0x20007000, 0x00000002 }, 485 {0x20007000, 0x00000002},
487 { 0x00061000, 0x00000002 }, 486 {0x00061000, 0x00000002},
488 { 0x0120751b, 0x00000002 }, 487 {0x0120751b, 0x00000002},
489 { 0x8040750a, 0x00000002 }, 488 {0x8040750a, 0x00000002},
490 { 0x8040750b, 0x00000002 }, 489 {0x8040750b, 0x00000002},
491 { 0x00110000, 0x00000002 }, 490 {0x00110000, 0x00000002},
492 { 0x000380e5, 0x00000002 }, 491 {0x000380e5, 0x00000002},
493 { 0x000000c6, 0x0000001c }, 492 {0x000000c6, 0x0000001c},
494 { 0x000610ab, 0x00000018 }, 493 {0x000610ab, 0x00000018},
495 { 0x844075bd, 0x00000002 }, 494 {0x844075bd, 0x00000002},
496 { 0x000610aa, 0x00000018 }, 495 {0x000610aa, 0x00000018},
497 { 0x840075bb, 0x00000002 }, 496 {0x840075bb, 0x00000002},
498 { 0x000610ab, 0x00000018 }, 497 {0x000610ab, 0x00000018},
499 { 0x844075bc, 0x00000002 }, 498 {0x844075bc, 0x00000002},
500 { 0x000000c9, 0x00000004 }, 499 {0x000000c9, 0x00000004},
501 { 0x804075bd, 0x00000002 }, 500 {0x804075bd, 0x00000002},
502 { 0x800075bb, 0x00000002 }, 501 {0x800075bb, 0x00000002},
503 { 0x804075bc, 0x00000002 }, 502 {0x804075bc, 0x00000002},
504 { 0x00108000, 0x00000002 }, 503 {0x00108000, 0x00000002},
505 { 0x01400000, 0x00000002 }, 504 {0x01400000, 0x00000002},
506 { 0x006000cd, 0x0000000c }, 505 {0x006000cd, 0x0000000c},
507 { 0x20c07000, 0x00000020 }, 506 {0x20c07000, 0x00000020},
508 { 0x000000cf, 0x00000012 }, 507 {0x000000cf, 0x00000012},
509 { 0x00800000, 0x00000006 }, 508 {0x00800000, 0x00000006},
510 { 0x0080751d, 0x00000006 }, 509 {0x0080751d, 0x00000006},
511 { 0000000000, 0000000000 }, 510 {0000000000, 0000000000},
512 { 0x0000775c, 0x00000002 }, 511 {0x0000775c, 0x00000002},
513 { 0x00a05000, 0x00000002 }, 512 {0x00a05000, 0x00000002},
514 { 0x00661000, 0x00000002 }, 513 {0x00661000, 0x00000002},
515 { 0x0460275d, 0x00000020 }, 514 {0x0460275d, 0x00000020},
516 { 0x00004000, 0000000000 }, 515 {0x00004000, 0000000000},
517 { 0x01e00830, 0x00000002 }, 516 {0x01e00830, 0x00000002},
518 { 0x21007000, 0000000000 }, 517 {0x21007000, 0000000000},
519 { 0x6464614d, 0000000000 }, 518 {0x6464614d, 0000000000},
520 { 0x69687420, 0000000000 }, 519 {0x69687420, 0000000000},
521 { 0x00000073, 0000000000 }, 520 {0x00000073, 0000000000},
522 { 0000000000, 0000000000 }, 521 {0000000000, 0000000000},
523 { 0x00005000, 0x00000002 }, 522 {0x00005000, 0x00000002},
524 { 0x000380d0, 0x00000002 }, 523 {0x000380d0, 0x00000002},
525 { 0x040025e0, 0x00000002 }, 524 {0x040025e0, 0x00000002},
526 { 0x000075e1, 0000000000 }, 525 {0x000075e1, 0000000000},
527 { 0x00000001, 0000000000 }, 526 {0x00000001, 0000000000},
528 { 0x000380e0, 0x00000002 }, 527 {0x000380e0, 0x00000002},
529 { 0x04002394, 0x00000002 }, 528 {0x04002394, 0x00000002},
530 { 0x00005000, 0000000000 }, 529 {0x00005000, 0000000000},
531 { 0000000000, 0000000000 }, 530 {0000000000, 0000000000},
532 { 0000000000, 0000000000 }, 531 {0000000000, 0000000000},
533 { 0x00000008, 0000000000 }, 532 {0x00000008, 0000000000},
534 { 0x00000004, 0000000000 }, 533 {0x00000004, 0000000000},
535 { 0000000000, 0000000000 }, 534 {0000000000, 0000000000},
536 { 0000000000, 0000000000 }, 535 {0000000000, 0000000000},
537 { 0000000000, 0000000000 }, 536 {0000000000, 0000000000},
538 { 0000000000, 0000000000 }, 537 {0000000000, 0000000000},
539 { 0000000000, 0000000000 }, 538 {0000000000, 0000000000},
540 { 0000000000, 0000000000 }, 539 {0000000000, 0000000000},
541 { 0000000000, 0000000000 }, 540 {0000000000, 0000000000},
542 { 0000000000, 0000000000 }, 541 {0000000000, 0000000000},
543 { 0000000000, 0000000000 }, 542 {0000000000, 0000000000},
544 { 0000000000, 0000000000 }, 543 {0000000000, 0000000000},
545 { 0000000000, 0000000000 }, 544 {0000000000, 0000000000},
546 { 0000000000, 0000000000 }, 545 {0000000000, 0000000000},
547 { 0000000000, 0000000000 }, 546 {0000000000, 0000000000},
548 { 0000000000, 0000000000 }, 547 {0000000000, 0000000000},
549 { 0000000000, 0000000000 }, 548 {0000000000, 0000000000},
550 { 0000000000, 0000000000 }, 549 {0000000000, 0000000000},
551 { 0000000000, 0000000000 }, 550 {0000000000, 0000000000},
552 { 0000000000, 0000000000 }, 551 {0000000000, 0000000000},
553 { 0000000000, 0000000000 }, 552 {0000000000, 0000000000},
554 { 0000000000, 0000000000 }, 553 {0000000000, 0000000000},
555 { 0000000000, 0000000000 }, 554 {0000000000, 0000000000},
556 { 0000000000, 0000000000 }, 555 {0000000000, 0000000000},
557 { 0000000000, 0000000000 }, 556 {0000000000, 0000000000},
558 { 0000000000, 0000000000 }, 557 {0000000000, 0000000000},
559}; 558};
560 559
561static u32 R300_cp_microcode[][2] = { 560static u32 R300_cp_microcode[][2] = {
562 { 0x4200e000, 0000000000 }, 561 {0x4200e000, 0000000000},
563 { 0x4000e000, 0000000000 }, 562 {0x4000e000, 0000000000},
564 { 0x000000af, 0x00000008 }, 563 {0x000000af, 0x00000008},
565 { 0x000000b3, 0x00000008 }, 564 {0x000000b3, 0x00000008},
566 { 0x6c5a504f, 0000000000 }, 565 {0x6c5a504f, 0000000000},
567 { 0x4f4f497a, 0000000000 }, 566 {0x4f4f497a, 0000000000},
568 { 0x5a578288, 0000000000 }, 567 {0x5a578288, 0000000000},
569 { 0x4f91906a, 0000000000 }, 568 {0x4f91906a, 0000000000},
570 { 0x4f4f4f4f, 0000000000 }, 569 {0x4f4f4f4f, 0000000000},
571 { 0x4fe24f44, 0000000000 }, 570 {0x4fe24f44, 0000000000},
572 { 0x4f9c9c9c, 0000000000 }, 571 {0x4f9c9c9c, 0000000000},
573 { 0xdc4f4fde, 0000000000 }, 572 {0xdc4f4fde, 0000000000},
574 { 0xa1cd4f4f, 0000000000 }, 573 {0xa1cd4f4f, 0000000000},
575 { 0xd29d9d9d, 0000000000 }, 574 {0xd29d9d9d, 0000000000},
576 { 0x4f0f9fd7, 0000000000 }, 575 {0x4f0f9fd7, 0000000000},
577 { 0x000ca000, 0x00000004 }, 576 {0x000ca000, 0x00000004},
578 { 0x000d0012, 0x00000038 }, 577 {0x000d0012, 0x00000038},
579 { 0x0000e8b4, 0x00000004 }, 578 {0x0000e8b4, 0x00000004},
580 { 0x000d0014, 0x00000038 }, 579 {0x000d0014, 0x00000038},
581 { 0x0000e8b6, 0x00000004 }, 580 {0x0000e8b6, 0x00000004},
582 { 0x000d0016, 0x00000038 }, 581 {0x000d0016, 0x00000038},
583 { 0x0000e854, 0x00000004 }, 582 {0x0000e854, 0x00000004},
584 { 0x000d0018, 0x00000038 }, 583 {0x000d0018, 0x00000038},
585 { 0x0000e855, 0x00000004 }, 584 {0x0000e855, 0x00000004},
586 { 0x000d001a, 0x00000038 }, 585 {0x000d001a, 0x00000038},
587 { 0x0000e856, 0x00000004 }, 586 {0x0000e856, 0x00000004},
588 { 0x000d001c, 0x00000038 }, 587 {0x000d001c, 0x00000038},
589 { 0x0000e857, 0x00000004 }, 588 {0x0000e857, 0x00000004},
590 { 0x000d001e, 0x00000038 }, 589 {0x000d001e, 0x00000038},
591 { 0x0000e824, 0x00000004 }, 590 {0x0000e824, 0x00000004},
592 { 0x000d0020, 0x00000038 }, 591 {0x000d0020, 0x00000038},
593 { 0x0000e825, 0x00000004 }, 592 {0x0000e825, 0x00000004},
594 { 0x000d0022, 0x00000038 }, 593 {0x000d0022, 0x00000038},
595 { 0x0000e830, 0x00000004 }, 594 {0x0000e830, 0x00000004},
596 { 0x000d0024, 0x00000038 }, 595 {0x000d0024, 0x00000038},
597 { 0x0000f0c0, 0x00000004 }, 596 {0x0000f0c0, 0x00000004},
598 { 0x000d0026, 0x00000038 }, 597 {0x000d0026, 0x00000038},
599 { 0x0000f0c1, 0x00000004 }, 598 {0x0000f0c1, 0x00000004},
600 { 0x000d0028, 0x00000038 }, 599 {0x000d0028, 0x00000038},
601 { 0x0000f041, 0x00000004 }, 600 {0x0000f041, 0x00000004},
602 { 0x000d002a, 0x00000038 }, 601 {0x000d002a, 0x00000038},
603 { 0x0000f184, 0x00000004 }, 602 {0x0000f184, 0x00000004},
604 { 0x000d002c, 0x00000038 }, 603 {0x000d002c, 0x00000038},
605 { 0x0000f185, 0x00000004 }, 604 {0x0000f185, 0x00000004},
606 { 0x000d002e, 0x00000038 }, 605 {0x000d002e, 0x00000038},
607 { 0x0000f186, 0x00000004 }, 606 {0x0000f186, 0x00000004},
608 { 0x000d0030, 0x00000038 }, 607 {0x000d0030, 0x00000038},
609 { 0x0000f187, 0x00000004 }, 608 {0x0000f187, 0x00000004},
610 { 0x000d0032, 0x00000038 }, 609 {0x000d0032, 0x00000038},
611 { 0x0000f180, 0x00000004 }, 610 {0x0000f180, 0x00000004},
612 { 0x000d0034, 0x00000038 }, 611 {0x000d0034, 0x00000038},
613 { 0x0000f393, 0x00000004 }, 612 {0x0000f393, 0x00000004},
614 { 0x000d0036, 0x00000038 }, 613 {0x000d0036, 0x00000038},
615 { 0x0000f38a, 0x00000004 }, 614 {0x0000f38a, 0x00000004},
616 { 0x000d0038, 0x00000038 }, 615 {0x000d0038, 0x00000038},
617 { 0x0000f38e, 0x00000004 }, 616 {0x0000f38e, 0x00000004},
618 { 0x0000e821, 0x00000004 }, 617 {0x0000e821, 0x00000004},
619 { 0x0140a000, 0x00000004 }, 618 {0x0140a000, 0x00000004},
620 { 0x00000043, 0x00000018 }, 619 {0x00000043, 0x00000018},
621 { 0x00cce800, 0x00000004 }, 620 {0x00cce800, 0x00000004},
622 { 0x001b0001, 0x00000004 }, 621 {0x001b0001, 0x00000004},
623 { 0x08004800, 0x00000004 }, 622 {0x08004800, 0x00000004},
624 { 0x001b0001, 0x00000004 }, 623 {0x001b0001, 0x00000004},
625 { 0x08004800, 0x00000004 }, 624 {0x08004800, 0x00000004},
626 { 0x001b0001, 0x00000004 }, 625 {0x001b0001, 0x00000004},
627 { 0x08004800, 0x00000004 }, 626 {0x08004800, 0x00000004},
628 { 0x0000003a, 0x00000008 }, 627 {0x0000003a, 0x00000008},
629 { 0x0000a000, 0000000000 }, 628 {0x0000a000, 0000000000},
630 { 0x02c0a000, 0x00000004 }, 629 {0x02c0a000, 0x00000004},
631 { 0x000ca000, 0x00000004 }, 630 {0x000ca000, 0x00000004},
632 { 0x00130000, 0x00000004 }, 631 {0x00130000, 0x00000004},
633 { 0x000c2000, 0x00000004 }, 632 {0x000c2000, 0x00000004},
634 { 0xc980c045, 0x00000008 }, 633 {0xc980c045, 0x00000008},
635 { 0x2000451d, 0x00000004 }, 634 {0x2000451d, 0x00000004},
636 { 0x0000e580, 0x00000004 }, 635 {0x0000e580, 0x00000004},
637 { 0x000ce581, 0x00000004 }, 636 {0x000ce581, 0x00000004},
638 { 0x08004580, 0x00000004 }, 637 {0x08004580, 0x00000004},
639 { 0x000ce581, 0x00000004 }, 638 {0x000ce581, 0x00000004},
640 { 0x0000004c, 0x00000008 }, 639 {0x0000004c, 0x00000008},
641 { 0x0000a000, 0000000000 }, 640 {0x0000a000, 0000000000},
642 { 0x000c2000, 0x00000004 }, 641 {0x000c2000, 0x00000004},
643 { 0x0000e50e, 0x00000004 }, 642 {0x0000e50e, 0x00000004},
644 { 0x00032000, 0x00000004 }, 643 {0x00032000, 0x00000004},
645 { 0x00022056, 0x00000028 }, 644 {0x00022056, 0x00000028},
646 { 0x00000056, 0x00000024 }, 645 {0x00000056, 0x00000024},
647 { 0x0800450f, 0x00000004 }, 646 {0x0800450f, 0x00000004},
648 { 0x0000a050, 0x00000008 }, 647 {0x0000a050, 0x00000008},
649 { 0x0000e565, 0x00000004 }, 648 {0x0000e565, 0x00000004},
650 { 0x0000e566, 0x00000004 }, 649 {0x0000e566, 0x00000004},
651 { 0x00000057, 0x00000008 }, 650 {0x00000057, 0x00000008},
652 { 0x03cca5b4, 0x00000004 }, 651 {0x03cca5b4, 0x00000004},
653 { 0x05432000, 0x00000004 }, 652 {0x05432000, 0x00000004},
654 { 0x00022000, 0x00000004 }, 653 {0x00022000, 0x00000004},
655 { 0x4ccce063, 0x00000030 }, 654 {0x4ccce063, 0x00000030},
656 { 0x08274565, 0x00000004 }, 655 {0x08274565, 0x00000004},
657 { 0x00000063, 0x00000030 }, 656 {0x00000063, 0x00000030},
658 { 0x08004564, 0x00000004 }, 657 {0x08004564, 0x00000004},
659 { 0x0000e566, 0x00000004 }, 658 {0x0000e566, 0x00000004},
660 { 0x0000005a, 0x00000008 }, 659 {0x0000005a, 0x00000008},
661 { 0x00802066, 0x00000010 }, 660 {0x00802066, 0x00000010},
662 { 0x00202000, 0x00000004 }, 661 {0x00202000, 0x00000004},
663 { 0x001b00ff, 0x00000004 }, 662 {0x001b00ff, 0x00000004},
664 { 0x01000069, 0x00000010 }, 663 {0x01000069, 0x00000010},
665 { 0x001f2000, 0x00000004 }, 664 {0x001f2000, 0x00000004},
666 { 0x001c00ff, 0x00000004 }, 665 {0x001c00ff, 0x00000004},
667 { 0000000000, 0x0000000c }, 666 {0000000000, 0x0000000c},
668 { 0x00000085, 0x00000030 }, 667 {0x00000085, 0x00000030},
669 { 0x0000005a, 0x00000008 }, 668 {0x0000005a, 0x00000008},
670 { 0x0000e576, 0x00000004 }, 669 {0x0000e576, 0x00000004},
671 { 0x000ca000, 0x00000004 }, 670 {0x000ca000, 0x00000004},
672 { 0x00012000, 0x00000004 }, 671 {0x00012000, 0x00000004},
673 { 0x00082000, 0x00000004 }, 672 {0x00082000, 0x00000004},
674 { 0x1800650e, 0x00000004 }, 673 {0x1800650e, 0x00000004},
675 { 0x00092000, 0x00000004 }, 674 {0x00092000, 0x00000004},
676 { 0x000a2000, 0x00000004 }, 675 {0x000a2000, 0x00000004},
677 { 0x000f0000, 0x00000004 }, 676 {0x000f0000, 0x00000004},
678 { 0x00400000, 0x00000004 }, 677 {0x00400000, 0x00000004},
679 { 0x00000079, 0x00000018 }, 678 {0x00000079, 0x00000018},
680 { 0x0000e563, 0x00000004 }, 679 {0x0000e563, 0x00000004},
681 { 0x00c0e5f9, 0x000000c2 }, 680 {0x00c0e5f9, 0x000000c2},
682 { 0x0000006e, 0x00000008 }, 681 {0x0000006e, 0x00000008},
683 { 0x0000a06e, 0x00000008 }, 682 {0x0000a06e, 0x00000008},
684 { 0x0000e576, 0x00000004 }, 683 {0x0000e576, 0x00000004},
685 { 0x0000e577, 0x00000004 }, 684 {0x0000e577, 0x00000004},
686 { 0x0000e50e, 0x00000004 }, 685 {0x0000e50e, 0x00000004},
687 { 0x0000e50f, 0x00000004 }, 686 {0x0000e50f, 0x00000004},
688 { 0x0140a000, 0x00000004 }, 687 {0x0140a000, 0x00000004},
689 { 0x0000007c, 0x00000018 }, 688 {0x0000007c, 0x00000018},
690 { 0x00c0e5f9, 0x000000c2 }, 689 {0x00c0e5f9, 0x000000c2},
691 { 0x0000007c, 0x00000008 }, 690 {0x0000007c, 0x00000008},
692 { 0x0014e50e, 0x00000004 }, 691 {0x0014e50e, 0x00000004},
693 { 0x0040e50f, 0x00000004 }, 692 {0x0040e50f, 0x00000004},
694 { 0x00c0007f, 0x00000008 }, 693 {0x00c0007f, 0x00000008},
695 { 0x0000e570, 0x00000004 }, 694 {0x0000e570, 0x00000004},
696 { 0x0000e571, 0x00000004 }, 695 {0x0000e571, 0x00000004},
697 { 0x0000e572, 0x0000000c }, 696 {0x0000e572, 0x0000000c},
698 { 0x0000a000, 0x00000004 }, 697 {0x0000a000, 0x00000004},
699 { 0x0140a000, 0x00000004 }, 698 {0x0140a000, 0x00000004},
700 { 0x0000e568, 0x00000004 }, 699 {0x0000e568, 0x00000004},
701 { 0x000c2000, 0x00000004 }, 700 {0x000c2000, 0x00000004},
702 { 0x00000089, 0x00000018 }, 701 {0x00000089, 0x00000018},
703 { 0x000b0000, 0x00000004 }, 702 {0x000b0000, 0x00000004},
704 { 0x18c0e562, 0x00000004 }, 703 {0x18c0e562, 0x00000004},
705 { 0x0000008b, 0x00000008 }, 704 {0x0000008b, 0x00000008},
706 { 0x00c0008a, 0x00000008 }, 705 {0x00c0008a, 0x00000008},
707 { 0x000700e4, 0x00000004 }, 706 {0x000700e4, 0x00000004},
708 { 0x00000097, 0x00000038 }, 707 {0x00000097, 0x00000038},
709 { 0x000ca099, 0x00000030 }, 708 {0x000ca099, 0x00000030},
710 { 0x080045bb, 0x00000004 }, 709 {0x080045bb, 0x00000004},
711 { 0x000c209a, 0x00000030 }, 710 {0x000c209a, 0x00000030},
712 { 0x0800e5bc, 0000000000 }, 711 {0x0800e5bc, 0000000000},
713 { 0x0000e5bb, 0x00000004 }, 712 {0x0000e5bb, 0x00000004},
714 { 0x0000e5bc, 0000000000 }, 713 {0x0000e5bc, 0000000000},
715 { 0x00120000, 0x0000000c }, 714 {0x00120000, 0x0000000c},
716 { 0x00120000, 0x00000004 }, 715 {0x00120000, 0x00000004},
717 { 0x001b0002, 0x0000000c }, 716 {0x001b0002, 0x0000000c},
718 { 0x0000a000, 0x00000004 }, 717 {0x0000a000, 0x00000004},
719 { 0x0000e821, 0x00000004 }, 718 {0x0000e821, 0x00000004},
720 { 0x0000e800, 0000000000 }, 719 {0x0000e800, 0000000000},
721 { 0x0000e821, 0x00000004 }, 720 {0x0000e821, 0x00000004},
722 { 0x0000e82e, 0000000000 }, 721 {0x0000e82e, 0000000000},
723 { 0x02cca000, 0x00000004 }, 722 {0x02cca000, 0x00000004},
724 { 0x00140000, 0x00000004 }, 723 {0x00140000, 0x00000004},
725 { 0x000ce1cc, 0x00000004 }, 724 {0x000ce1cc, 0x00000004},
726 { 0x050de1cd, 0x00000004 }, 725 {0x050de1cd, 0x00000004},
727 { 0x000000a7, 0x00000020 }, 726 {0x000000a7, 0x00000020},
728 { 0x4200e000, 0000000000 }, 727 {0x4200e000, 0000000000},
729 { 0x000000ae, 0x00000038 }, 728 {0x000000ae, 0x00000038},
730 { 0x000ca000, 0x00000004 }, 729 {0x000ca000, 0x00000004},
731 { 0x00140000, 0x00000004 }, 730 {0x00140000, 0x00000004},
732 { 0x000c2000, 0x00000004 }, 731 {0x000c2000, 0x00000004},
733 { 0x00160000, 0x00000004 }, 732 {0x00160000, 0x00000004},
734 { 0x700ce000, 0x00000004 }, 733 {0x700ce000, 0x00000004},
735 { 0x001400aa, 0x00000008 }, 734 {0x001400aa, 0x00000008},
736 { 0x4000e000, 0000000000 }, 735 {0x4000e000, 0000000000},
737 { 0x02400000, 0x00000004 }, 736 {0x02400000, 0x00000004},
738 { 0x400ee000, 0x00000004 }, 737 {0x400ee000, 0x00000004},
739 { 0x02400000, 0x00000004 }, 738 {0x02400000, 0x00000004},
740 { 0x4000e000, 0000000000 }, 739 {0x4000e000, 0000000000},
741 { 0x000c2000, 0x00000004 }, 740 {0x000c2000, 0x00000004},
742 { 0x0240e51b, 0x00000004 }, 741 {0x0240e51b, 0x00000004},
743 { 0x0080e50a, 0x00000005 }, 742 {0x0080e50a, 0x00000005},
744 { 0x0080e50b, 0x00000005 }, 743 {0x0080e50b, 0x00000005},
745 { 0x00220000, 0x00000004 }, 744 {0x00220000, 0x00000004},
746 { 0x000700e4, 0x00000004 }, 745 {0x000700e4, 0x00000004},
747 { 0x000000c1, 0x00000038 }, 746 {0x000000c1, 0x00000038},
748 { 0x000c209a, 0x00000030 }, 747 {0x000c209a, 0x00000030},
749 { 0x0880e5bd, 0x00000005 }, 748 {0x0880e5bd, 0x00000005},
750 { 0x000c2099, 0x00000030 }, 749 {0x000c2099, 0x00000030},
751 { 0x0800e5bb, 0x00000005 }, 750 {0x0800e5bb, 0x00000005},
752 { 0x000c209a, 0x00000030 }, 751 {0x000c209a, 0x00000030},
753 { 0x0880e5bc, 0x00000005 }, 752 {0x0880e5bc, 0x00000005},
754 { 0x000000c4, 0x00000008 }, 753 {0x000000c4, 0x00000008},
755 { 0x0080e5bd, 0x00000005 }, 754 {0x0080e5bd, 0x00000005},
756 { 0x0000e5bb, 0x00000005 }, 755 {0x0000e5bb, 0x00000005},
757 { 0x0080e5bc, 0x00000005 }, 756 {0x0080e5bc, 0x00000005},
758 { 0x00210000, 0x00000004 }, 757 {0x00210000, 0x00000004},
759 { 0x02800000, 0x00000004 }, 758 {0x02800000, 0x00000004},
760 { 0x00c000c8, 0x00000018 }, 759 {0x00c000c8, 0x00000018},
761 { 0x4180e000, 0x00000040 }, 760 {0x4180e000, 0x00000040},
762 { 0x000000ca, 0x00000024 }, 761 {0x000000ca, 0x00000024},
763 { 0x01000000, 0x0000000c }, 762 {0x01000000, 0x0000000c},
764 { 0x0100e51d, 0x0000000c }, 763 {0x0100e51d, 0x0000000c},
765 { 0x000045bb, 0x00000004 }, 764 {0x000045bb, 0x00000004},
766 { 0x000080c4, 0x00000008 }, 765 {0x000080c4, 0x00000008},
767 { 0x0000f3ce, 0x00000004 }, 766 {0x0000f3ce, 0x00000004},
768 { 0x0140a000, 0x00000004 }, 767 {0x0140a000, 0x00000004},
769 { 0x00cc2000, 0x00000004 }, 768 {0x00cc2000, 0x00000004},
770 { 0x08c053cf, 0x00000040 }, 769 {0x08c053cf, 0x00000040},
771 { 0x00008000, 0000000000 }, 770 {0x00008000, 0000000000},
772 { 0x0000f3d2, 0x00000004 }, 771 {0x0000f3d2, 0x00000004},
773 { 0x0140a000, 0x00000004 }, 772 {0x0140a000, 0x00000004},
774 { 0x00cc2000, 0x00000004 }, 773 {0x00cc2000, 0x00000004},
775 { 0x08c053d3, 0x00000040 }, 774 {0x08c053d3, 0x00000040},
776 { 0x00008000, 0000000000 }, 775 {0x00008000, 0000000000},
777 { 0x0000f39d, 0x00000004 }, 776 {0x0000f39d, 0x00000004},
778 { 0x0140a000, 0x00000004 }, 777 {0x0140a000, 0x00000004},
779 { 0x00cc2000, 0x00000004 }, 778 {0x00cc2000, 0x00000004},
780 { 0x08c0539e, 0x00000040 }, 779 {0x08c0539e, 0x00000040},
781 { 0x00008000, 0000000000 }, 780 {0x00008000, 0000000000},
782 { 0x03c00830, 0x00000004 }, 781 {0x03c00830, 0x00000004},
783 { 0x4200e000, 0000000000 }, 782 {0x4200e000, 0000000000},
784 { 0x0000a000, 0x00000004 }, 783 {0x0000a000, 0x00000004},
785 { 0x200045e0, 0x00000004 }, 784 {0x200045e0, 0x00000004},
786 { 0x0000e5e1, 0000000000 }, 785 {0x0000e5e1, 0000000000},
787 { 0x00000001, 0000000000 }, 786 {0x00000001, 0000000000},
788 { 0x000700e1, 0x00000004 }, 787 {0x000700e1, 0x00000004},
789 { 0x0800e394, 0000000000 }, 788 {0x0800e394, 0000000000},
790 { 0000000000, 0000000000 }, 789 {0000000000, 0000000000},
791 { 0000000000, 0000000000 }, 790 {0000000000, 0000000000},
792 { 0000000000, 0000000000 }, 791 {0000000000, 0000000000},
793 { 0000000000, 0000000000 }, 792 {0000000000, 0000000000},
794 { 0000000000, 0000000000 }, 793 {0000000000, 0000000000},
795 { 0000000000, 0000000000 }, 794 {0000000000, 0000000000},
796 { 0000000000, 0000000000 }, 795 {0000000000, 0000000000},
797 { 0000000000, 0000000000 }, 796 {0000000000, 0000000000},
798 { 0000000000, 0000000000 }, 797 {0000000000, 0000000000},
799 { 0000000000, 0000000000 }, 798 {0000000000, 0000000000},
800 { 0000000000, 0000000000 }, 799 {0000000000, 0000000000},
801 { 0000000000, 0000000000 }, 800 {0000000000, 0000000000},
802 { 0000000000, 0000000000 }, 801 {0000000000, 0000000000},
803 { 0000000000, 0000000000 }, 802 {0000000000, 0000000000},
804 { 0000000000, 0000000000 }, 803 {0000000000, 0000000000},
805 { 0000000000, 0000000000 }, 804 {0000000000, 0000000000},
806 { 0000000000, 0000000000 }, 805 {0000000000, 0000000000},
807 { 0000000000, 0000000000 }, 806 {0000000000, 0000000000},
808 { 0000000000, 0000000000 }, 807 {0000000000, 0000000000},
809 { 0000000000, 0000000000 }, 808 {0000000000, 0000000000},
810 { 0000000000, 0000000000 }, 809 {0000000000, 0000000000},
811 { 0000000000, 0000000000 }, 810 {0000000000, 0000000000},
812 { 0000000000, 0000000000 }, 811 {0000000000, 0000000000},
813 { 0000000000, 0000000000 }, 812 {0000000000, 0000000000},
814 { 0000000000, 0000000000 }, 813 {0000000000, 0000000000},
815 { 0000000000, 0000000000 }, 814 {0000000000, 0000000000},
816 { 0000000000, 0000000000 }, 815 {0000000000, 0000000000},
817 { 0000000000, 0000000000 }, 816 {0000000000, 0000000000},
818}; 817};
819 818
820static int RADEON_READ_PLL(drm_device_t *dev, int addr) 819static int RADEON_READ_PLL(drm_device_t * dev, int addr)
821{ 820{
822 drm_radeon_private_t *dev_priv = dev->dev_private; 821 drm_radeon_private_t *dev_priv = dev->dev_private;
823 822
@@ -825,145 +824,148 @@ static int RADEON_READ_PLL(drm_device_t *dev, int addr)
825 return RADEON_READ(RADEON_CLOCK_CNTL_DATA); 824 return RADEON_READ(RADEON_CLOCK_CNTL_DATA);
826} 825}
827 826
827static int RADEON_READ_PCIE(drm_radeon_private_t * dev_priv, int addr)
828{
829 RADEON_WRITE8(RADEON_PCIE_INDEX, addr & 0xff);
830 return RADEON_READ(RADEON_PCIE_DATA);
831}
832
828#if RADEON_FIFO_DEBUG 833#if RADEON_FIFO_DEBUG
829static void radeon_status( drm_radeon_private_t *dev_priv ) 834static void radeon_status(drm_radeon_private_t * dev_priv)
830{ 835{
831 printk( "%s:\n", __FUNCTION__ ); 836 printk("%s:\n", __FUNCTION__);
832 printk( "RBBM_STATUS = 0x%08x\n", 837 printk("RBBM_STATUS = 0x%08x\n",
833 (unsigned int)RADEON_READ( RADEON_RBBM_STATUS ) ); 838 (unsigned int)RADEON_READ(RADEON_RBBM_STATUS));
834 printk( "CP_RB_RTPR = 0x%08x\n", 839 printk("CP_RB_RTPR = 0x%08x\n",
835 (unsigned int)RADEON_READ( RADEON_CP_RB_RPTR ) ); 840 (unsigned int)RADEON_READ(RADEON_CP_RB_RPTR));
836 printk( "CP_RB_WTPR = 0x%08x\n", 841 printk("CP_RB_WTPR = 0x%08x\n",
837 (unsigned int)RADEON_READ( RADEON_CP_RB_WPTR ) ); 842 (unsigned int)RADEON_READ(RADEON_CP_RB_WPTR));
838 printk( "AIC_CNTL = 0x%08x\n", 843 printk("AIC_CNTL = 0x%08x\n",
839 (unsigned int)RADEON_READ( RADEON_AIC_CNTL ) ); 844 (unsigned int)RADEON_READ(RADEON_AIC_CNTL));
840 printk( "AIC_STAT = 0x%08x\n", 845 printk("AIC_STAT = 0x%08x\n",
841 (unsigned int)RADEON_READ( RADEON_AIC_STAT ) ); 846 (unsigned int)RADEON_READ(RADEON_AIC_STAT));
842 printk( "AIC_PT_BASE = 0x%08x\n", 847 printk("AIC_PT_BASE = 0x%08x\n",
843 (unsigned int)RADEON_READ( RADEON_AIC_PT_BASE ) ); 848 (unsigned int)RADEON_READ(RADEON_AIC_PT_BASE));
844 printk( "TLB_ADDR = 0x%08x\n", 849 printk("TLB_ADDR = 0x%08x\n",
845 (unsigned int)RADEON_READ( RADEON_AIC_TLB_ADDR ) ); 850 (unsigned int)RADEON_READ(RADEON_AIC_TLB_ADDR));
846 printk( "TLB_DATA = 0x%08x\n", 851 printk("TLB_DATA = 0x%08x\n",
847 (unsigned int)RADEON_READ( RADEON_AIC_TLB_DATA ) ); 852 (unsigned int)RADEON_READ(RADEON_AIC_TLB_DATA));
848} 853}
849#endif 854#endif
850 855
851
852/* ================================================================ 856/* ================================================================
853 * Engine, FIFO control 857 * Engine, FIFO control
854 */ 858 */
855 859
856static int radeon_do_pixcache_flush( drm_radeon_private_t *dev_priv ) 860static int radeon_do_pixcache_flush(drm_radeon_private_t * dev_priv)
857{ 861{
858 u32 tmp; 862 u32 tmp;
859 int i; 863 int i;
860 864
861 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; 865 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
862 866
863 tmp = RADEON_READ( RADEON_RB2D_DSTCACHE_CTLSTAT ); 867 tmp = RADEON_READ(RADEON_RB2D_DSTCACHE_CTLSTAT);
864 tmp |= RADEON_RB2D_DC_FLUSH_ALL; 868 tmp |= RADEON_RB2D_DC_FLUSH_ALL;
865 RADEON_WRITE( RADEON_RB2D_DSTCACHE_CTLSTAT, tmp ); 869 RADEON_WRITE(RADEON_RB2D_DSTCACHE_CTLSTAT, tmp);
866 870
867 for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) { 871 for (i = 0; i < dev_priv->usec_timeout; i++) {
868 if ( !(RADEON_READ( RADEON_RB2D_DSTCACHE_CTLSTAT ) 872 if (!(RADEON_READ(RADEON_RB2D_DSTCACHE_CTLSTAT)
869 & RADEON_RB2D_DC_BUSY) ) { 873 & RADEON_RB2D_DC_BUSY)) {
870 return 0; 874 return 0;
871 } 875 }
872 DRM_UDELAY( 1 ); 876 DRM_UDELAY(1);
873 } 877 }
874 878
875#if RADEON_FIFO_DEBUG 879#if RADEON_FIFO_DEBUG
876 DRM_ERROR( "failed!\n" ); 880 DRM_ERROR("failed!\n");
877 radeon_status( dev_priv ); 881 radeon_status(dev_priv);
878#endif 882#endif
879 return DRM_ERR(EBUSY); 883 return DRM_ERR(EBUSY);
880} 884}
881 885
882static int radeon_do_wait_for_fifo( drm_radeon_private_t *dev_priv, 886static int radeon_do_wait_for_fifo(drm_radeon_private_t * dev_priv, int entries)
883 int entries )
884{ 887{
885 int i; 888 int i;
886 889
887 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; 890 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
888 891
889 for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) { 892 for (i = 0; i < dev_priv->usec_timeout; i++) {
890 int slots = ( RADEON_READ( RADEON_RBBM_STATUS ) 893 int slots = (RADEON_READ(RADEON_RBBM_STATUS)
891 & RADEON_RBBM_FIFOCNT_MASK ); 894 & RADEON_RBBM_FIFOCNT_MASK);
892 if ( slots >= entries ) return 0; 895 if (slots >= entries)
893 DRM_UDELAY( 1 ); 896 return 0;
897 DRM_UDELAY(1);
894 } 898 }
895 899
896#if RADEON_FIFO_DEBUG 900#if RADEON_FIFO_DEBUG
897 DRM_ERROR( "failed!\n" ); 901 DRM_ERROR("failed!\n");
898 radeon_status( dev_priv ); 902 radeon_status(dev_priv);
899#endif 903#endif
900 return DRM_ERR(EBUSY); 904 return DRM_ERR(EBUSY);
901} 905}
902 906
903static int radeon_do_wait_for_idle( drm_radeon_private_t *dev_priv ) 907static int radeon_do_wait_for_idle(drm_radeon_private_t * dev_priv)
904{ 908{
905 int i, ret; 909 int i, ret;
906 910
907 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; 911 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
908 912
909 ret = radeon_do_wait_for_fifo( dev_priv, 64 ); 913 ret = radeon_do_wait_for_fifo(dev_priv, 64);
910 if ( ret ) return ret; 914 if (ret)
915 return ret;
911 916
912 for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) { 917 for (i = 0; i < dev_priv->usec_timeout; i++) {
913 if ( !(RADEON_READ( RADEON_RBBM_STATUS ) 918 if (!(RADEON_READ(RADEON_RBBM_STATUS)
914 & RADEON_RBBM_ACTIVE) ) { 919 & RADEON_RBBM_ACTIVE)) {
915 radeon_do_pixcache_flush( dev_priv ); 920 radeon_do_pixcache_flush(dev_priv);
916 return 0; 921 return 0;
917 } 922 }
918 DRM_UDELAY( 1 ); 923 DRM_UDELAY(1);
919 } 924 }
920 925
921#if RADEON_FIFO_DEBUG 926#if RADEON_FIFO_DEBUG
922 DRM_ERROR( "failed!\n" ); 927 DRM_ERROR("failed!\n");
923 radeon_status( dev_priv ); 928 radeon_status(dev_priv);
924#endif 929#endif
925 return DRM_ERR(EBUSY); 930 return DRM_ERR(EBUSY);
926} 931}
927 932
928
929/* ================================================================ 933/* ================================================================
930 * CP control, initialization 934 * CP control, initialization
931 */ 935 */
932 936
933/* Load the microcode for the CP */ 937/* Load the microcode for the CP */
934static void radeon_cp_load_microcode( drm_radeon_private_t *dev_priv ) 938static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv)
935{ 939{
936 int i; 940 int i;
937 DRM_DEBUG( "\n" ); 941 DRM_DEBUG("\n");
938 942
939 radeon_do_wait_for_idle( dev_priv ); 943 radeon_do_wait_for_idle(dev_priv);
940 944
941 RADEON_WRITE( RADEON_CP_ME_RAM_ADDR, 0 ); 945 RADEON_WRITE(RADEON_CP_ME_RAM_ADDR, 0);
942 946
943 if (dev_priv->microcode_version==UCODE_R200) { 947 if (dev_priv->microcode_version == UCODE_R200) {
944 DRM_INFO("Loading R200 Microcode\n"); 948 DRM_INFO("Loading R200 Microcode\n");
945 for ( i = 0 ; i < 256 ; i++ ) 949 for (i = 0; i < 256; i++) {
946 { 950 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
947 RADEON_WRITE( RADEON_CP_ME_RAM_DATAH, 951 R200_cp_microcode[i][1]);
948 R200_cp_microcode[i][1] ); 952 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
949 RADEON_WRITE( RADEON_CP_ME_RAM_DATAL, 953 R200_cp_microcode[i][0]);
950 R200_cp_microcode[i][0] );
951 } 954 }
952 } else if (dev_priv->microcode_version==UCODE_R300) { 955 } else if (dev_priv->microcode_version == UCODE_R300) {
953 DRM_INFO("Loading R300 Microcode\n"); 956 DRM_INFO("Loading R300 Microcode\n");
954 for ( i = 0 ; i < 256 ; i++ ) 957 for (i = 0; i < 256; i++) {
955 { 958 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
956 RADEON_WRITE( RADEON_CP_ME_RAM_DATAH, 959 R300_cp_microcode[i][1]);
957 R300_cp_microcode[i][1] ); 960 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
958 RADEON_WRITE( RADEON_CP_ME_RAM_DATAL, 961 R300_cp_microcode[i][0]);
959 R300_cp_microcode[i][0] );
960 } 962 }
961 } else { 963 } else {
962 for ( i = 0 ; i < 256 ; i++ ) { 964 for (i = 0; i < 256; i++) {
963 RADEON_WRITE( RADEON_CP_ME_RAM_DATAH, 965 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
964 radeon_cp_microcode[i][1] ); 966 radeon_cp_microcode[i][1]);
965 RADEON_WRITE( RADEON_CP_ME_RAM_DATAL, 967 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
966 radeon_cp_microcode[i][0] ); 968 radeon_cp_microcode[i][0]);
967 } 969 }
968 } 970 }
969} 971}
@@ -972,25 +974,25 @@ static void radeon_cp_load_microcode( drm_radeon_private_t *dev_priv )
972 * prior to a wait for idle, as it informs the engine that the command 974 * prior to a wait for idle, as it informs the engine that the command
973 * stream is ending. 975 * stream is ending.
974 */ 976 */
975static void radeon_do_cp_flush( drm_radeon_private_t *dev_priv ) 977static void radeon_do_cp_flush(drm_radeon_private_t * dev_priv)
976{ 978{
977 DRM_DEBUG( "\n" ); 979 DRM_DEBUG("\n");
978#if 0 980#if 0
979 u32 tmp; 981 u32 tmp;
980 982
981 tmp = RADEON_READ( RADEON_CP_RB_WPTR ) | (1 << 31); 983 tmp = RADEON_READ(RADEON_CP_RB_WPTR) | (1 << 31);
982 RADEON_WRITE( RADEON_CP_RB_WPTR, tmp ); 984 RADEON_WRITE(RADEON_CP_RB_WPTR, tmp);
983#endif 985#endif
984} 986}
985 987
986/* Wait for the CP to go idle. 988/* Wait for the CP to go idle.
987 */ 989 */
988int radeon_do_cp_idle( drm_radeon_private_t *dev_priv ) 990int radeon_do_cp_idle(drm_radeon_private_t * dev_priv)
989{ 991{
990 RING_LOCALS; 992 RING_LOCALS;
991 DRM_DEBUG( "\n" ); 993 DRM_DEBUG("\n");
992 994
993 BEGIN_RING( 6 ); 995 BEGIN_RING(6);
994 996
995 RADEON_PURGE_CACHE(); 997 RADEON_PURGE_CACHE();
996 RADEON_PURGE_ZCACHE(); 998 RADEON_PURGE_ZCACHE();
@@ -999,23 +1001,23 @@ int radeon_do_cp_idle( drm_radeon_private_t *dev_priv )
999 ADVANCE_RING(); 1001 ADVANCE_RING();
1000 COMMIT_RING(); 1002 COMMIT_RING();
1001 1003
1002 return radeon_do_wait_for_idle( dev_priv ); 1004 return radeon_do_wait_for_idle(dev_priv);
1003} 1005}
1004 1006
1005/* Start the Command Processor. 1007/* Start the Command Processor.
1006 */ 1008 */
1007static void radeon_do_cp_start( drm_radeon_private_t *dev_priv ) 1009static void radeon_do_cp_start(drm_radeon_private_t * dev_priv)
1008{ 1010{
1009 RING_LOCALS; 1011 RING_LOCALS;
1010 DRM_DEBUG( "\n" ); 1012 DRM_DEBUG("\n");
1011 1013
1012 radeon_do_wait_for_idle( dev_priv ); 1014 radeon_do_wait_for_idle(dev_priv);
1013 1015
1014 RADEON_WRITE( RADEON_CP_CSQ_CNTL, dev_priv->cp_mode ); 1016 RADEON_WRITE(RADEON_CP_CSQ_CNTL, dev_priv->cp_mode);
1015 1017
1016 dev_priv->cp_running = 1; 1018 dev_priv->cp_running = 1;
1017 1019
1018 BEGIN_RING( 6 ); 1020 BEGIN_RING(6);
1019 1021
1020 RADEON_PURGE_CACHE(); 1022 RADEON_PURGE_CACHE();
1021 RADEON_PURGE_ZCACHE(); 1023 RADEON_PURGE_ZCACHE();
@@ -1029,14 +1031,14 @@ static void radeon_do_cp_start( drm_radeon_private_t *dev_priv )
1029 * commands, so you must wait for the CP command stream to complete 1031 * commands, so you must wait for the CP command stream to complete
1030 * before calling this routine. 1032 * before calling this routine.
1031 */ 1033 */
1032static void radeon_do_cp_reset( drm_radeon_private_t *dev_priv ) 1034static void radeon_do_cp_reset(drm_radeon_private_t * dev_priv)
1033{ 1035{
1034 u32 cur_read_ptr; 1036 u32 cur_read_ptr;
1035 DRM_DEBUG( "\n" ); 1037 DRM_DEBUG("\n");
1036 1038
1037 cur_read_ptr = RADEON_READ( RADEON_CP_RB_RPTR ); 1039 cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
1038 RADEON_WRITE( RADEON_CP_RB_WPTR, cur_read_ptr ); 1040 RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
1039 SET_RING_HEAD( dev_priv, cur_read_ptr ); 1041 SET_RING_HEAD(dev_priv, cur_read_ptr);
1040 dev_priv->ring.tail = cur_read_ptr; 1042 dev_priv->ring.tail = cur_read_ptr;
1041} 1043}
1042 1044
@@ -1044,91 +1046,90 @@ static void radeon_do_cp_reset( drm_radeon_private_t *dev_priv )
1044 * commands, so you must flush the command stream and wait for the CP 1046 * commands, so you must flush the command stream and wait for the CP
1045 * to go idle before calling this routine. 1047 * to go idle before calling this routine.
1046 */ 1048 */
1047static void radeon_do_cp_stop( drm_radeon_private_t *dev_priv ) 1049static void radeon_do_cp_stop(drm_radeon_private_t * dev_priv)
1048{ 1050{
1049 DRM_DEBUG( "\n" ); 1051 DRM_DEBUG("\n");
1050 1052
1051 RADEON_WRITE( RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS ); 1053 RADEON_WRITE(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS);
1052 1054
1053 dev_priv->cp_running = 0; 1055 dev_priv->cp_running = 0;
1054} 1056}
1055 1057
1056/* Reset the engine. This will stop the CP if it is running. 1058/* Reset the engine. This will stop the CP if it is running.
1057 */ 1059 */
1058static int radeon_do_engine_reset( drm_device_t *dev ) 1060static int radeon_do_engine_reset(drm_device_t * dev)
1059{ 1061{
1060 drm_radeon_private_t *dev_priv = dev->dev_private; 1062 drm_radeon_private_t *dev_priv = dev->dev_private;
1061 u32 clock_cntl_index, mclk_cntl, rbbm_soft_reset; 1063 u32 clock_cntl_index, mclk_cntl, rbbm_soft_reset;
1062 DRM_DEBUG( "\n" ); 1064 DRM_DEBUG("\n");
1063
1064 radeon_do_pixcache_flush( dev_priv );
1065
1066 clock_cntl_index = RADEON_READ( RADEON_CLOCK_CNTL_INDEX );
1067 mclk_cntl = RADEON_READ_PLL( dev, RADEON_MCLK_CNTL );
1068
1069 RADEON_WRITE_PLL( RADEON_MCLK_CNTL, ( mclk_cntl |
1070 RADEON_FORCEON_MCLKA |
1071 RADEON_FORCEON_MCLKB |
1072 RADEON_FORCEON_YCLKA |
1073 RADEON_FORCEON_YCLKB |
1074 RADEON_FORCEON_MC |
1075 RADEON_FORCEON_AIC ) );
1076
1077 rbbm_soft_reset = RADEON_READ( RADEON_RBBM_SOFT_RESET );
1078 1065
1079 RADEON_WRITE( RADEON_RBBM_SOFT_RESET, ( rbbm_soft_reset | 1066 radeon_do_pixcache_flush(dev_priv);
1080 RADEON_SOFT_RESET_CP | 1067
1068 clock_cntl_index = RADEON_READ(RADEON_CLOCK_CNTL_INDEX);
1069 mclk_cntl = RADEON_READ_PLL(dev, RADEON_MCLK_CNTL);
1070
1071 RADEON_WRITE_PLL(RADEON_MCLK_CNTL, (mclk_cntl |
1072 RADEON_FORCEON_MCLKA |
1073 RADEON_FORCEON_MCLKB |
1074 RADEON_FORCEON_YCLKA |
1075 RADEON_FORCEON_YCLKB |
1076 RADEON_FORCEON_MC |
1077 RADEON_FORCEON_AIC));
1078
1079 rbbm_soft_reset = RADEON_READ(RADEON_RBBM_SOFT_RESET);
1080
1081 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset |
1082 RADEON_SOFT_RESET_CP |
1083 RADEON_SOFT_RESET_HI |
1084 RADEON_SOFT_RESET_SE |
1085 RADEON_SOFT_RESET_RE |
1086 RADEON_SOFT_RESET_PP |
1087 RADEON_SOFT_RESET_E2 |
1088 RADEON_SOFT_RESET_RB));
1089 RADEON_READ(RADEON_RBBM_SOFT_RESET);
1090 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset &
1091 ~(RADEON_SOFT_RESET_CP |
1081 RADEON_SOFT_RESET_HI | 1092 RADEON_SOFT_RESET_HI |
1082 RADEON_SOFT_RESET_SE | 1093 RADEON_SOFT_RESET_SE |
1083 RADEON_SOFT_RESET_RE | 1094 RADEON_SOFT_RESET_RE |
1084 RADEON_SOFT_RESET_PP | 1095 RADEON_SOFT_RESET_PP |
1085 RADEON_SOFT_RESET_E2 | 1096 RADEON_SOFT_RESET_E2 |
1086 RADEON_SOFT_RESET_RB ) ); 1097 RADEON_SOFT_RESET_RB)));
1087 RADEON_READ( RADEON_RBBM_SOFT_RESET ); 1098 RADEON_READ(RADEON_RBBM_SOFT_RESET);
1088 RADEON_WRITE( RADEON_RBBM_SOFT_RESET, ( rbbm_soft_reset & 1099
1089 ~( RADEON_SOFT_RESET_CP | 1100 RADEON_WRITE_PLL(RADEON_MCLK_CNTL, mclk_cntl);
1090 RADEON_SOFT_RESET_HI | 1101 RADEON_WRITE(RADEON_CLOCK_CNTL_INDEX, clock_cntl_index);
1091 RADEON_SOFT_RESET_SE | 1102 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, rbbm_soft_reset);
1092 RADEON_SOFT_RESET_RE |
1093 RADEON_SOFT_RESET_PP |
1094 RADEON_SOFT_RESET_E2 |
1095 RADEON_SOFT_RESET_RB ) ) );
1096 RADEON_READ( RADEON_RBBM_SOFT_RESET );
1097
1098
1099 RADEON_WRITE_PLL( RADEON_MCLK_CNTL, mclk_cntl );
1100 RADEON_WRITE( RADEON_CLOCK_CNTL_INDEX, clock_cntl_index );
1101 RADEON_WRITE( RADEON_RBBM_SOFT_RESET, rbbm_soft_reset );
1102 1103
1103 /* Reset the CP ring */ 1104 /* Reset the CP ring */
1104 radeon_do_cp_reset( dev_priv ); 1105 radeon_do_cp_reset(dev_priv);
1105 1106
1106 /* The CP is no longer running after an engine reset */ 1107 /* The CP is no longer running after an engine reset */
1107 dev_priv->cp_running = 0; 1108 dev_priv->cp_running = 0;
1108 1109
1109 /* Reset any pending vertex, indirect buffers */ 1110 /* Reset any pending vertex, indirect buffers */
1110 radeon_freelist_reset( dev ); 1111 radeon_freelist_reset(dev);
1111 1112
1112 return 0; 1113 return 0;
1113} 1114}
1114 1115
1115static void radeon_cp_init_ring_buffer( drm_device_t *dev, 1116static void radeon_cp_init_ring_buffer(drm_device_t * dev,
1116 drm_radeon_private_t *dev_priv ) 1117 drm_radeon_private_t * dev_priv)
1117{ 1118{
1118 u32 ring_start, cur_read_ptr; 1119 u32 ring_start, cur_read_ptr;
1119 u32 tmp; 1120 u32 tmp;
1120 1121
1121 /* Initialize the memory controller */ 1122 /* Initialize the memory controller */
1122 RADEON_WRITE( RADEON_MC_FB_LOCATION, 1123 RADEON_WRITE(RADEON_MC_FB_LOCATION,
1123 ( ( dev_priv->gart_vm_start - 1 ) & 0xffff0000 ) 1124 ((dev_priv->gart_vm_start - 1) & 0xffff0000)
1124 | ( dev_priv->fb_location >> 16 ) ); 1125 | (dev_priv->fb_location >> 16));
1125 1126
1126#if __OS_HAS_AGP 1127#if __OS_HAS_AGP
1127 if ( !dev_priv->is_pci ) { 1128 if (!dev_priv->is_pci) {
1128 RADEON_WRITE( RADEON_MC_AGP_LOCATION, 1129 RADEON_WRITE(RADEON_MC_AGP_LOCATION,
1129 (((dev_priv->gart_vm_start - 1 + 1130 (((dev_priv->gart_vm_start - 1 +
1130 dev_priv->gart_size) & 0xffff0000) | 1131 dev_priv->gart_size) & 0xffff0000) |
1131 (dev_priv->gart_vm_start >> 16)) ); 1132 (dev_priv->gart_vm_start >> 16)));
1132 1133
1133 ring_start = (dev_priv->cp_ring->offset 1134 ring_start = (dev_priv->cp_ring->offset
1134 - dev->agp->base 1135 - dev->agp->base
@@ -1139,25 +1140,24 @@ static void radeon_cp_init_ring_buffer( drm_device_t *dev,
1139 - (unsigned long)dev->sg->virtual 1140 - (unsigned long)dev->sg->virtual
1140 + dev_priv->gart_vm_start); 1141 + dev_priv->gart_vm_start);
1141 1142
1142 RADEON_WRITE( RADEON_CP_RB_BASE, ring_start ); 1143 RADEON_WRITE(RADEON_CP_RB_BASE, ring_start);
1143 1144
1144 /* Set the write pointer delay */ 1145 /* Set the write pointer delay */
1145 RADEON_WRITE( RADEON_CP_RB_WPTR_DELAY, 0 ); 1146 RADEON_WRITE(RADEON_CP_RB_WPTR_DELAY, 0);
1146 1147
1147 /* Initialize the ring buffer's read and write pointers */ 1148 /* Initialize the ring buffer's read and write pointers */
1148 cur_read_ptr = RADEON_READ( RADEON_CP_RB_RPTR ); 1149 cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
1149 RADEON_WRITE( RADEON_CP_RB_WPTR, cur_read_ptr ); 1150 RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
1150 SET_RING_HEAD( dev_priv, cur_read_ptr ); 1151 SET_RING_HEAD(dev_priv, cur_read_ptr);
1151 dev_priv->ring.tail = cur_read_ptr; 1152 dev_priv->ring.tail = cur_read_ptr;
1152 1153
1153#if __OS_HAS_AGP 1154#if __OS_HAS_AGP
1154 if ( !dev_priv->is_pci ) { 1155 if (!dev_priv->is_pci) {
1155 /* set RADEON_AGP_BASE here instead of relying on X from user space */ 1156 /* set RADEON_AGP_BASE here instead of relying on X from user space */
1156 RADEON_WRITE(RADEON_AGP_BASE, (unsigned int)dev->agp->base); 1157 RADEON_WRITE(RADEON_AGP_BASE, (unsigned int)dev->agp->base);
1157 RADEON_WRITE( RADEON_CP_RB_RPTR_ADDR, 1158 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR,
1158 dev_priv->ring_rptr->offset 1159 dev_priv->ring_rptr->offset
1159 - dev->agp->base 1160 - dev->agp->base + dev_priv->gart_vm_start);
1160 + dev_priv->gart_vm_start);
1161 } else 1161 } else
1162#endif 1162#endif
1163 { 1163 {
@@ -1168,11 +1168,10 @@ static void radeon_cp_init_ring_buffer( drm_device_t *dev,
1168 (unsigned long)dev->sg->virtual; 1168 (unsigned long)dev->sg->virtual;
1169 page_ofs = tmp_ofs >> PAGE_SHIFT; 1169 page_ofs = tmp_ofs >> PAGE_SHIFT;
1170 1170
1171 RADEON_WRITE( RADEON_CP_RB_RPTR_ADDR, 1171 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR, entry->busaddr[page_ofs]);
1172 entry->busaddr[page_ofs]); 1172 DRM_DEBUG("ring rptr: offset=0x%08lx handle=0x%08lx\n",
1173 DRM_DEBUG( "ring rptr: offset=0x%08lx handle=0x%08lx\n", 1173 (unsigned long)entry->busaddr[page_ofs],
1174 (unsigned long) entry->busaddr[page_ofs], 1174 entry->handle + tmp_ofs);
1175 entry->handle + tmp_ofs );
1176 } 1175 }
1177 1176
1178 /* Initialize the scratch register pointer. This will cause 1177 /* Initialize the scratch register pointer. This will cause
@@ -1182,127 +1181,168 @@ static void radeon_cp_init_ring_buffer( drm_device_t *dev,
1182 * We simply put this behind the ring read pointer, this works 1181 * We simply put this behind the ring read pointer, this works
1183 * with PCI GART as well as (whatever kind of) AGP GART 1182 * with PCI GART as well as (whatever kind of) AGP GART
1184 */ 1183 */
1185 RADEON_WRITE( RADEON_SCRATCH_ADDR, RADEON_READ( RADEON_CP_RB_RPTR_ADDR ) 1184 RADEON_WRITE(RADEON_SCRATCH_ADDR, RADEON_READ(RADEON_CP_RB_RPTR_ADDR)
1186 + RADEON_SCRATCH_REG_OFFSET ); 1185 + RADEON_SCRATCH_REG_OFFSET);
1187 1186
1188 dev_priv->scratch = ((__volatile__ u32 *) 1187 dev_priv->scratch = ((__volatile__ u32 *)
1189 dev_priv->ring_rptr->handle + 1188 dev_priv->ring_rptr->handle +
1190 (RADEON_SCRATCH_REG_OFFSET / sizeof(u32))); 1189 (RADEON_SCRATCH_REG_OFFSET / sizeof(u32)));
1191 1190
1192 RADEON_WRITE( RADEON_SCRATCH_UMSK, 0x7 ); 1191 RADEON_WRITE(RADEON_SCRATCH_UMSK, 0x7);
1193 1192
1194 /* Writeback doesn't seem to work everywhere, test it first */ 1193 /* Writeback doesn't seem to work everywhere, test it first */
1195 DRM_WRITE32( dev_priv->ring_rptr, RADEON_SCRATCHOFF(1), 0 ); 1194 DRM_WRITE32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1), 0);
1196 RADEON_WRITE( RADEON_SCRATCH_REG1, 0xdeadbeef ); 1195 RADEON_WRITE(RADEON_SCRATCH_REG1, 0xdeadbeef);
1197 1196
1198 for ( tmp = 0 ; tmp < dev_priv->usec_timeout ; tmp++ ) { 1197 for (tmp = 0; tmp < dev_priv->usec_timeout; tmp++) {
1199 if ( DRM_READ32( dev_priv->ring_rptr, RADEON_SCRATCHOFF(1) ) == 0xdeadbeef ) 1198 if (DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1)) ==
1199 0xdeadbeef)
1200 break; 1200 break;
1201 DRM_UDELAY( 1 ); 1201 DRM_UDELAY(1);
1202 } 1202 }
1203 1203
1204 if ( tmp < dev_priv->usec_timeout ) { 1204 if (tmp < dev_priv->usec_timeout) {
1205 dev_priv->writeback_works = 1; 1205 dev_priv->writeback_works = 1;
1206 DRM_DEBUG( "writeback test succeeded, tmp=%d\n", tmp ); 1206 DRM_DEBUG("writeback test succeeded, tmp=%d\n", tmp);
1207 } else { 1207 } else {
1208 dev_priv->writeback_works = 0; 1208 dev_priv->writeback_works = 0;
1209 DRM_DEBUG( "writeback test failed\n" ); 1209 DRM_DEBUG("writeback test failed\n");
1210 }
1211 if (radeon_no_wb == 1) {
1212 dev_priv->writeback_works = 0;
1213 DRM_DEBUG("writeback forced off\n");
1210 } 1214 }
1211 1215
1212 dev_priv->sarea_priv->last_frame = dev_priv->scratch[0] = 0; 1216 dev_priv->sarea_priv->last_frame = dev_priv->scratch[0] = 0;
1213 RADEON_WRITE( RADEON_LAST_FRAME_REG, 1217 RADEON_WRITE(RADEON_LAST_FRAME_REG, dev_priv->sarea_priv->last_frame);
1214 dev_priv->sarea_priv->last_frame );
1215 1218
1216 dev_priv->sarea_priv->last_dispatch = dev_priv->scratch[1] = 0; 1219 dev_priv->sarea_priv->last_dispatch = dev_priv->scratch[1] = 0;
1217 RADEON_WRITE( RADEON_LAST_DISPATCH_REG, 1220 RADEON_WRITE(RADEON_LAST_DISPATCH_REG,
1218 dev_priv->sarea_priv->last_dispatch ); 1221 dev_priv->sarea_priv->last_dispatch);
1219 1222
1220 dev_priv->sarea_priv->last_clear = dev_priv->scratch[2] = 0; 1223 dev_priv->sarea_priv->last_clear = dev_priv->scratch[2] = 0;
1221 RADEON_WRITE( RADEON_LAST_CLEAR_REG, 1224 RADEON_WRITE(RADEON_LAST_CLEAR_REG, dev_priv->sarea_priv->last_clear);
1222 dev_priv->sarea_priv->last_clear );
1223 1225
1224 /* Set ring buffer size */ 1226 /* Set ring buffer size */
1225#ifdef __BIG_ENDIAN 1227#ifdef __BIG_ENDIAN
1226 RADEON_WRITE( RADEON_CP_RB_CNTL, dev_priv->ring.size_l2qw | RADEON_BUF_SWAP_32BIT ); 1228 RADEON_WRITE(RADEON_CP_RB_CNTL,
1229 dev_priv->ring.size_l2qw | RADEON_BUF_SWAP_32BIT);
1227#else 1230#else
1228 RADEON_WRITE( RADEON_CP_RB_CNTL, dev_priv->ring.size_l2qw ); 1231 RADEON_WRITE(RADEON_CP_RB_CNTL, dev_priv->ring.size_l2qw);
1229#endif 1232#endif
1230 1233
1231 radeon_do_wait_for_idle( dev_priv ); 1234 radeon_do_wait_for_idle(dev_priv);
1232 1235
1233 /* Turn on bus mastering */ 1236 /* Turn on bus mastering */
1234 tmp = RADEON_READ( RADEON_BUS_CNTL ) & ~RADEON_BUS_MASTER_DIS; 1237 tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
1235 RADEON_WRITE( RADEON_BUS_CNTL, tmp ); 1238 RADEON_WRITE(RADEON_BUS_CNTL, tmp);
1236 1239
1237 /* Sync everything up */ 1240 /* Sync everything up */
1238 RADEON_WRITE( RADEON_ISYNC_CNTL, 1241 RADEON_WRITE(RADEON_ISYNC_CNTL,
1239 (RADEON_ISYNC_ANY2D_IDLE3D | 1242 (RADEON_ISYNC_ANY2D_IDLE3D |
1240 RADEON_ISYNC_ANY3D_IDLE2D | 1243 RADEON_ISYNC_ANY3D_IDLE2D |
1241 RADEON_ISYNC_WAIT_IDLEGUI | 1244 RADEON_ISYNC_WAIT_IDLEGUI |
1242 RADEON_ISYNC_CPSCRATCH_IDLEGUI) ); 1245 RADEON_ISYNC_CPSCRATCH_IDLEGUI));
1246}
1247
1248/* Enable or disable PCI-E GART on the chip */
1249static void radeon_set_pciegart(drm_radeon_private_t * dev_priv, int on)
1250{
1251 u32 tmp = RADEON_READ_PCIE(dev_priv, RADEON_PCIE_TX_GART_CNTL);
1252 if (on) {
1253
1254 DRM_DEBUG("programming pcie %08X %08lX %08X\n",
1255 dev_priv->gart_vm_start,
1256 (long)dev_priv->gart_info.bus_addr,
1257 dev_priv->gart_size);
1258 RADEON_WRITE_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO,
1259 dev_priv->gart_vm_start);
1260 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_BASE,
1261 dev_priv->gart_info.bus_addr);
1262 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_START_LO,
1263 dev_priv->gart_vm_start);
1264 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_END_LO,
1265 dev_priv->gart_vm_start +
1266 dev_priv->gart_size - 1);
1267
1268 RADEON_WRITE(RADEON_MC_AGP_LOCATION, 0xffffffc0); /* ?? */
1269
1270 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
1271 RADEON_PCIE_TX_GART_EN);
1272 } else {
1273 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
1274 tmp & ~RADEON_PCIE_TX_GART_EN);
1275 }
1243} 1276}
1244 1277
1245/* Enable or disable PCI GART on the chip */ 1278/* Enable or disable PCI GART on the chip */
1246static void radeon_set_pcigart( drm_radeon_private_t *dev_priv, int on ) 1279static void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on)
1247{ 1280{
1248 u32 tmp = RADEON_READ( RADEON_AIC_CNTL ); 1281 u32 tmp = RADEON_READ(RADEON_AIC_CNTL);
1282
1283 if (dev_priv->flags & CHIP_IS_PCIE) {
1284 radeon_set_pciegart(dev_priv, on);
1285 return;
1286 }
1249 1287
1250 if ( on ) { 1288 if (on) {
1251 RADEON_WRITE( RADEON_AIC_CNTL, tmp | RADEON_PCIGART_TRANSLATE_EN ); 1289 RADEON_WRITE(RADEON_AIC_CNTL,
1290 tmp | RADEON_PCIGART_TRANSLATE_EN);
1252 1291
1253 /* set PCI GART page-table base address 1292 /* set PCI GART page-table base address
1254 */ 1293 */
1255 RADEON_WRITE( RADEON_AIC_PT_BASE, dev_priv->bus_pci_gart ); 1294 RADEON_WRITE(RADEON_AIC_PT_BASE, dev_priv->gart_info.bus_addr);
1256 1295
1257 /* set address range for PCI address translate 1296 /* set address range for PCI address translate
1258 */ 1297 */
1259 RADEON_WRITE( RADEON_AIC_LO_ADDR, dev_priv->gart_vm_start ); 1298 RADEON_WRITE(RADEON_AIC_LO_ADDR, dev_priv->gart_vm_start);
1260 RADEON_WRITE( RADEON_AIC_HI_ADDR, dev_priv->gart_vm_start 1299 RADEON_WRITE(RADEON_AIC_HI_ADDR, dev_priv->gart_vm_start
1261 + dev_priv->gart_size - 1); 1300 + dev_priv->gart_size - 1);
1262 1301
1263 /* Turn off AGP aperture -- is this required for PCI GART? 1302 /* Turn off AGP aperture -- is this required for PCI GART?
1264 */ 1303 */
1265 RADEON_WRITE( RADEON_MC_AGP_LOCATION, 0xffffffc0 ); /* ?? */ 1304 RADEON_WRITE(RADEON_MC_AGP_LOCATION, 0xffffffc0); /* ?? */
1266 RADEON_WRITE( RADEON_AGP_COMMAND, 0 ); /* clear AGP_COMMAND */ 1305 RADEON_WRITE(RADEON_AGP_COMMAND, 0); /* clear AGP_COMMAND */
1267 } else { 1306 } else {
1268 RADEON_WRITE( RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN ); 1307 RADEON_WRITE(RADEON_AIC_CNTL,
1308 tmp & ~RADEON_PCIGART_TRANSLATE_EN);
1269 } 1309 }
1270} 1310}
1271 1311
1272static int radeon_do_init_cp( drm_device_t *dev, drm_radeon_init_t *init ) 1312static int radeon_do_init_cp(drm_device_t * dev, drm_radeon_init_t * init)
1273{ 1313{
1274 drm_radeon_private_t *dev_priv = dev->dev_private;; 1314 drm_radeon_private_t *dev_priv = dev->dev_private;;
1275 DRM_DEBUG( "\n" ); 1315 DRM_DEBUG("\n");
1276 1316
1277 dev_priv->is_pci = init->is_pci; 1317 dev_priv->is_pci = init->is_pci;
1278 1318
1279 if ( dev_priv->is_pci && !dev->sg ) { 1319 if (dev_priv->is_pci && !dev->sg) {
1280 DRM_ERROR( "PCI GART memory not allocated!\n" ); 1320 DRM_ERROR("PCI GART memory not allocated!\n");
1281 dev->dev_private = (void *)dev_priv; 1321 dev->dev_private = (void *)dev_priv;
1282 radeon_do_cleanup_cp(dev); 1322 radeon_do_cleanup_cp(dev);
1283 return DRM_ERR(EINVAL); 1323 return DRM_ERR(EINVAL);
1284 } 1324 }
1285 1325
1286 dev_priv->usec_timeout = init->usec_timeout; 1326 dev_priv->usec_timeout = init->usec_timeout;
1287 if ( dev_priv->usec_timeout < 1 || 1327 if (dev_priv->usec_timeout < 1 ||
1288 dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT ) { 1328 dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT) {
1289 DRM_DEBUG( "TIMEOUT problem!\n" ); 1329 DRM_DEBUG("TIMEOUT problem!\n");
1290 dev->dev_private = (void *)dev_priv; 1330 dev->dev_private = (void *)dev_priv;
1291 radeon_do_cleanup_cp(dev); 1331 radeon_do_cleanup_cp(dev);
1292 return DRM_ERR(EINVAL); 1332 return DRM_ERR(EINVAL);
1293 } 1333 }
1294 1334
1295 switch(init->func) { 1335 switch (init->func) {
1296 case RADEON_INIT_R200_CP: 1336 case RADEON_INIT_R200_CP:
1297 dev_priv->microcode_version=UCODE_R200; 1337 dev_priv->microcode_version = UCODE_R200;
1298 break; 1338 break;
1299 case RADEON_INIT_R300_CP: 1339 case RADEON_INIT_R300_CP:
1300 dev_priv->microcode_version=UCODE_R300; 1340 dev_priv->microcode_version = UCODE_R300;
1301 break; 1341 break;
1302 default: 1342 default:
1303 dev_priv->microcode_version=UCODE_R100; 1343 dev_priv->microcode_version = UCODE_R100;
1304 } 1344 }
1305 1345
1306 dev_priv->do_boxes = 0; 1346 dev_priv->do_boxes = 0;
1307 dev_priv->cp_mode = init->cp_mode; 1347 dev_priv->cp_mode = init->cp_mode;
1308 1348
@@ -1310,15 +1350,15 @@ static int radeon_do_init_cp( drm_device_t *dev, drm_radeon_init_t *init )
1310 * but the ring can be in either AGP or PCI space for the ring 1350 * but the ring can be in either AGP or PCI space for the ring
1311 * read pointer. 1351 * read pointer.
1312 */ 1352 */
1313 if ( ( init->cp_mode != RADEON_CSQ_PRIBM_INDDIS ) && 1353 if ((init->cp_mode != RADEON_CSQ_PRIBM_INDDIS) &&
1314 ( init->cp_mode != RADEON_CSQ_PRIBM_INDBM ) ) { 1354 (init->cp_mode != RADEON_CSQ_PRIBM_INDBM)) {
1315 DRM_DEBUG( "BAD cp_mode (%x)!\n", init->cp_mode ); 1355 DRM_DEBUG("BAD cp_mode (%x)!\n", init->cp_mode);
1316 dev->dev_private = (void *)dev_priv; 1356 dev->dev_private = (void *)dev_priv;
1317 radeon_do_cleanup_cp(dev); 1357 radeon_do_cleanup_cp(dev);
1318 return DRM_ERR(EINVAL); 1358 return DRM_ERR(EINVAL);
1319 } 1359 }
1320 1360
1321 switch ( init->fb_bpp ) { 1361 switch (init->fb_bpp) {
1322 case 16: 1362 case 16:
1323 dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565; 1363 dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565;
1324 break; 1364 break;
@@ -1327,12 +1367,12 @@ static int radeon_do_init_cp( drm_device_t *dev, drm_radeon_init_t *init )
1327 dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888; 1367 dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888;
1328 break; 1368 break;
1329 } 1369 }
1330 dev_priv->front_offset = init->front_offset; 1370 dev_priv->front_offset = init->front_offset;
1331 dev_priv->front_pitch = init->front_pitch; 1371 dev_priv->front_pitch = init->front_pitch;
1332 dev_priv->back_offset = init->back_offset; 1372 dev_priv->back_offset = init->back_offset;
1333 dev_priv->back_pitch = init->back_pitch; 1373 dev_priv->back_pitch = init->back_pitch;
1334 1374
1335 switch ( init->depth_bpp ) { 1375 switch (init->depth_bpp) {
1336 case 16: 1376 case 16:
1337 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z; 1377 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z;
1338 break; 1378 break;
@@ -1341,8 +1381,8 @@ static int radeon_do_init_cp( drm_device_t *dev, drm_radeon_init_t *init )
1341 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z; 1381 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
1342 break; 1382 break;
1343 } 1383 }
1344 dev_priv->depth_offset = init->depth_offset; 1384 dev_priv->depth_offset = init->depth_offset;
1345 dev_priv->depth_pitch = init->depth_pitch; 1385 dev_priv->depth_pitch = init->depth_pitch;
1346 1386
1347 /* Hardware state for depth clears. Remove this if/when we no 1387 /* Hardware state for depth clears. Remove this if/when we no
1348 * longer clear the depth buffer with a 3D rectangle. Hard-code 1388 * longer clear the depth buffer with a 3D rectangle. Hard-code
@@ -1351,16 +1391,16 @@ static int radeon_do_init_cp( drm_device_t *dev, drm_radeon_init_t *init )
1351 */ 1391 */
1352 dev_priv->depth_clear.rb3d_cntl = (RADEON_PLANE_MASK_ENABLE | 1392 dev_priv->depth_clear.rb3d_cntl = (RADEON_PLANE_MASK_ENABLE |
1353 (dev_priv->color_fmt << 10) | 1393 (dev_priv->color_fmt << 10) |
1354 (dev_priv->microcode_version == UCODE_R100 ? RADEON_ZBLOCK16 : 0)); 1394 (dev_priv->microcode_version ==
1395 UCODE_R100 ? RADEON_ZBLOCK16 : 0));
1355 1396
1356 dev_priv->depth_clear.rb3d_zstencilcntl = 1397 dev_priv->depth_clear.rb3d_zstencilcntl =
1357 (dev_priv->depth_fmt | 1398 (dev_priv->depth_fmt |
1358 RADEON_Z_TEST_ALWAYS | 1399 RADEON_Z_TEST_ALWAYS |
1359 RADEON_STENCIL_TEST_ALWAYS | 1400 RADEON_STENCIL_TEST_ALWAYS |
1360 RADEON_STENCIL_S_FAIL_REPLACE | 1401 RADEON_STENCIL_S_FAIL_REPLACE |
1361 RADEON_STENCIL_ZPASS_REPLACE | 1402 RADEON_STENCIL_ZPASS_REPLACE |
1362 RADEON_STENCIL_ZFAIL_REPLACE | 1403 RADEON_STENCIL_ZFAIL_REPLACE | RADEON_Z_WRITE_ENABLE);
1363 RADEON_Z_WRITE_ENABLE);
1364 1404
1365 dev_priv->depth_clear.se_cntl = (RADEON_FFACE_CULL_CW | 1405 dev_priv->depth_clear.se_cntl = (RADEON_FFACE_CULL_CW |
1366 RADEON_BFACE_SOLID | 1406 RADEON_BFACE_SOLID |
@@ -1382,8 +1422,8 @@ static int radeon_do_init_cp( drm_device_t *dev, drm_radeon_init_t *init )
1382 dev_priv->ring_rptr_offset = init->ring_rptr_offset; 1422 dev_priv->ring_rptr_offset = init->ring_rptr_offset;
1383 dev_priv->buffers_offset = init->buffers_offset; 1423 dev_priv->buffers_offset = init->buffers_offset;
1384 dev_priv->gart_textures_offset = init->gart_textures_offset; 1424 dev_priv->gart_textures_offset = init->gart_textures_offset;
1385 1425
1386 if(!dev_priv->sarea) { 1426 if (!dev_priv->sarea) {
1387 DRM_ERROR("could not find sarea!\n"); 1427 DRM_ERROR("could not find sarea!\n");
1388 dev->dev_private = (void *)dev_priv; 1428 dev->dev_private = (void *)dev_priv;
1389 radeon_do_cleanup_cp(dev); 1429 radeon_do_cleanup_cp(dev);
@@ -1391,21 +1431,21 @@ static int radeon_do_init_cp( drm_device_t *dev, drm_radeon_init_t *init )
1391 } 1431 }
1392 1432
1393 dev_priv->mmio = drm_core_findmap(dev, init->mmio_offset); 1433 dev_priv->mmio = drm_core_findmap(dev, init->mmio_offset);
1394 if(!dev_priv->mmio) { 1434 if (!dev_priv->mmio) {
1395 DRM_ERROR("could not find mmio region!\n"); 1435 DRM_ERROR("could not find mmio region!\n");
1396 dev->dev_private = (void *)dev_priv; 1436 dev->dev_private = (void *)dev_priv;
1397 radeon_do_cleanup_cp(dev); 1437 radeon_do_cleanup_cp(dev);
1398 return DRM_ERR(EINVAL); 1438 return DRM_ERR(EINVAL);
1399 } 1439 }
1400 dev_priv->cp_ring = drm_core_findmap(dev, init->ring_offset); 1440 dev_priv->cp_ring = drm_core_findmap(dev, init->ring_offset);
1401 if(!dev_priv->cp_ring) { 1441 if (!dev_priv->cp_ring) {
1402 DRM_ERROR("could not find cp ring region!\n"); 1442 DRM_ERROR("could not find cp ring region!\n");
1403 dev->dev_private = (void *)dev_priv; 1443 dev->dev_private = (void *)dev_priv;
1404 radeon_do_cleanup_cp(dev); 1444 radeon_do_cleanup_cp(dev);
1405 return DRM_ERR(EINVAL); 1445 return DRM_ERR(EINVAL);
1406 } 1446 }
1407 dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset); 1447 dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset);
1408 if(!dev_priv->ring_rptr) { 1448 if (!dev_priv->ring_rptr) {
1409 DRM_ERROR("could not find ring read pointer!\n"); 1449 DRM_ERROR("could not find ring read pointer!\n");
1410 dev->dev_private = (void *)dev_priv; 1450 dev->dev_private = (void *)dev_priv;
1411 radeon_do_cleanup_cp(dev); 1451 radeon_do_cleanup_cp(dev);
@@ -1413,16 +1453,17 @@ static int radeon_do_init_cp( drm_device_t *dev, drm_radeon_init_t *init )
1413 } 1453 }
1414 dev->agp_buffer_token = init->buffers_offset; 1454 dev->agp_buffer_token = init->buffers_offset;
1415 dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset); 1455 dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset);
1416 if(!dev->agp_buffer_map) { 1456 if (!dev->agp_buffer_map) {
1417 DRM_ERROR("could not find dma buffer region!\n"); 1457 DRM_ERROR("could not find dma buffer region!\n");
1418 dev->dev_private = (void *)dev_priv; 1458 dev->dev_private = (void *)dev_priv;
1419 radeon_do_cleanup_cp(dev); 1459 radeon_do_cleanup_cp(dev);
1420 return DRM_ERR(EINVAL); 1460 return DRM_ERR(EINVAL);
1421 } 1461 }
1422 1462
1423 if ( init->gart_textures_offset ) { 1463 if (init->gart_textures_offset) {
1424 dev_priv->gart_textures = drm_core_findmap(dev, init->gart_textures_offset); 1464 dev_priv->gart_textures =
1425 if ( !dev_priv->gart_textures ) { 1465 drm_core_findmap(dev, init->gart_textures_offset);
1466 if (!dev_priv->gart_textures) {
1426 DRM_ERROR("could not find GART texture region!\n"); 1467 DRM_ERROR("could not find GART texture region!\n");
1427 dev->dev_private = (void *)dev_priv; 1468 dev->dev_private = (void *)dev_priv;
1428 radeon_do_cleanup_cp(dev); 1469 radeon_do_cleanup_cp(dev);
@@ -1431,17 +1472,17 @@ static int radeon_do_init_cp( drm_device_t *dev, drm_radeon_init_t *init )
1431 } 1472 }
1432 1473
1433 dev_priv->sarea_priv = 1474 dev_priv->sarea_priv =
1434 (drm_radeon_sarea_t *)((u8 *)dev_priv->sarea->handle + 1475 (drm_radeon_sarea_t *) ((u8 *) dev_priv->sarea->handle +
1435 init->sarea_priv_offset); 1476 init->sarea_priv_offset);
1436 1477
1437#if __OS_HAS_AGP 1478#if __OS_HAS_AGP
1438 if ( !dev_priv->is_pci ) { 1479 if (!dev_priv->is_pci) {
1439 drm_core_ioremap( dev_priv->cp_ring, dev ); 1480 drm_core_ioremap(dev_priv->cp_ring, dev);
1440 drm_core_ioremap( dev_priv->ring_rptr, dev ); 1481 drm_core_ioremap(dev_priv->ring_rptr, dev);
1441 drm_core_ioremap( dev->agp_buffer_map, dev ); 1482 drm_core_ioremap(dev->agp_buffer_map, dev);
1442 if(!dev_priv->cp_ring->handle || 1483 if (!dev_priv->cp_ring->handle ||
1443 !dev_priv->ring_rptr->handle || 1484 !dev_priv->ring_rptr->handle ||
1444 !dev->agp_buffer_map->handle) { 1485 !dev->agp_buffer_map->handle) {
1445 DRM_ERROR("could not find ioremap agp regions!\n"); 1486 DRM_ERROR("could not find ioremap agp regions!\n");
1446 dev->dev_private = (void *)dev_priv; 1487 dev->dev_private = (void *)dev_priv;
1447 radeon_do_cleanup_cp(dev); 1488 radeon_do_cleanup_cp(dev);
@@ -1450,220 +1491,251 @@ static int radeon_do_init_cp( drm_device_t *dev, drm_radeon_init_t *init )
1450 } else 1491 } else
1451#endif 1492#endif
1452 { 1493 {
1453 dev_priv->cp_ring->handle = 1494 dev_priv->cp_ring->handle = (void *)dev_priv->cp_ring->offset;
1454 (void *)dev_priv->cp_ring->offset;
1455 dev_priv->ring_rptr->handle = 1495 dev_priv->ring_rptr->handle =
1456 (void *)dev_priv->ring_rptr->offset; 1496 (void *)dev_priv->ring_rptr->offset;
1457 dev->agp_buffer_map->handle = (void *)dev->agp_buffer_map->offset; 1497 dev->agp_buffer_map->handle =
1458 1498 (void *)dev->agp_buffer_map->offset;
1459 DRM_DEBUG( "dev_priv->cp_ring->handle %p\n", 1499
1460 dev_priv->cp_ring->handle ); 1500 DRM_DEBUG("dev_priv->cp_ring->handle %p\n",
1461 DRM_DEBUG( "dev_priv->ring_rptr->handle %p\n", 1501 dev_priv->cp_ring->handle);
1462 dev_priv->ring_rptr->handle ); 1502 DRM_DEBUG("dev_priv->ring_rptr->handle %p\n",
1463 DRM_DEBUG( "dev->agp_buffer_map->handle %p\n", 1503 dev_priv->ring_rptr->handle);
1464 dev->agp_buffer_map->handle ); 1504 DRM_DEBUG("dev->agp_buffer_map->handle %p\n",
1505 dev->agp_buffer_map->handle);
1465 } 1506 }
1466 1507
1467 dev_priv->fb_location = ( RADEON_READ( RADEON_MC_FB_LOCATION ) 1508 dev_priv->fb_location = (RADEON_READ(RADEON_MC_FB_LOCATION)
1468 & 0xffff ) << 16; 1509 & 0xffff) << 16;
1469 1510
1470 dev_priv->front_pitch_offset = (((dev_priv->front_pitch/64) << 22) | 1511 dev_priv->front_pitch_offset = (((dev_priv->front_pitch / 64) << 22) |
1471 ( ( dev_priv->front_offset 1512 ((dev_priv->front_offset
1472 + dev_priv->fb_location ) >> 10 ) ); 1513 + dev_priv->fb_location) >> 10));
1473 1514
1474 dev_priv->back_pitch_offset = (((dev_priv->back_pitch/64) << 22) | 1515 dev_priv->back_pitch_offset = (((dev_priv->back_pitch / 64) << 22) |
1475 ( ( dev_priv->back_offset 1516 ((dev_priv->back_offset
1476 + dev_priv->fb_location ) >> 10 ) ); 1517 + dev_priv->fb_location) >> 10));
1477
1478 dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch/64) << 22) |
1479 ( ( dev_priv->depth_offset
1480 + dev_priv->fb_location ) >> 10 ) );
1481 1518
1519 dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch / 64) << 22) |
1520 ((dev_priv->depth_offset
1521 + dev_priv->fb_location) >> 10));
1482 1522
1483 dev_priv->gart_size = init->gart_size; 1523 dev_priv->gart_size = init->gart_size;
1484 dev_priv->gart_vm_start = dev_priv->fb_location 1524 dev_priv->gart_vm_start = dev_priv->fb_location
1485 + RADEON_READ( RADEON_CONFIG_APER_SIZE ); 1525 + RADEON_READ(RADEON_CONFIG_APER_SIZE);
1486 1526
1487#if __OS_HAS_AGP 1527#if __OS_HAS_AGP
1488 if ( !dev_priv->is_pci ) 1528 if (!dev_priv->is_pci)
1489 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset 1529 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1490 - dev->agp->base 1530 - dev->agp->base
1491 + dev_priv->gart_vm_start); 1531 + dev_priv->gart_vm_start);
1492 else 1532 else
1493#endif 1533#endif
1494 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset 1534 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1495 - (unsigned long)dev->sg->virtual 1535 - (unsigned long)dev->sg->virtual
1496 + dev_priv->gart_vm_start); 1536 + dev_priv->gart_vm_start);
1497 1537
1498 DRM_DEBUG( "dev_priv->gart_size %d\n", 1538 DRM_DEBUG("dev_priv->gart_size %d\n", dev_priv->gart_size);
1499 dev_priv->gart_size ); 1539 DRM_DEBUG("dev_priv->gart_vm_start 0x%x\n", dev_priv->gart_vm_start);
1500 DRM_DEBUG( "dev_priv->gart_vm_start 0x%x\n", 1540 DRM_DEBUG("dev_priv->gart_buffers_offset 0x%lx\n",
1501 dev_priv->gart_vm_start ); 1541 dev_priv->gart_buffers_offset);
1502 DRM_DEBUG( "dev_priv->gart_buffers_offset 0x%lx\n",
1503 dev_priv->gart_buffers_offset );
1504 1542
1505 dev_priv->ring.start = (u32 *)dev_priv->cp_ring->handle; 1543 dev_priv->ring.start = (u32 *) dev_priv->cp_ring->handle;
1506 dev_priv->ring.end = ((u32 *)dev_priv->cp_ring->handle 1544 dev_priv->ring.end = ((u32 *) dev_priv->cp_ring->handle
1507 + init->ring_size / sizeof(u32)); 1545 + init->ring_size / sizeof(u32));
1508 dev_priv->ring.size = init->ring_size; 1546 dev_priv->ring.size = init->ring_size;
1509 dev_priv->ring.size_l2qw = drm_order( init->ring_size / 8 ); 1547 dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8);
1510 1548
1511 dev_priv->ring.tail_mask = 1549 dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1;
1512 (dev_priv->ring.size / sizeof(u32)) - 1;
1513 1550
1514 dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK; 1551 dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK;
1515 1552
1516#if __OS_HAS_AGP 1553#if __OS_HAS_AGP
1517 if ( !dev_priv->is_pci ) { 1554 if (!dev_priv->is_pci) {
1518 /* Turn off PCI GART */ 1555 /* Turn off PCI GART */
1519 radeon_set_pcigart( dev_priv, 0 ); 1556 radeon_set_pcigart(dev_priv, 0);
1520 } else 1557 } else
1521#endif 1558#endif
1522 { 1559 {
1523 if (!drm_ati_pcigart_init( dev, &dev_priv->phys_pci_gart, 1560 /* if we have an offset set from userspace */
1524 &dev_priv->bus_pci_gart)) { 1561 if (dev_priv->pcigart_offset) {
1525 DRM_ERROR( "failed to init PCI GART!\n" ); 1562 dev_priv->gart_info.bus_addr =
1563 dev_priv->pcigart_offset + dev_priv->fb_location;
1564 dev_priv->gart_info.addr =
1565 (unsigned long)drm_ioremap(dev_priv->gart_info.
1566 bus_addr,
1567 RADEON_PCIGART_TABLE_SIZE,
1568 dev);
1569
1570 dev_priv->gart_info.is_pcie =
1571 !!(dev_priv->flags & CHIP_IS_PCIE);
1572 dev_priv->gart_info.gart_table_location =
1573 DRM_ATI_GART_FB;
1574
1575 DRM_DEBUG("Setting phys_pci_gart to %08lX %08lX\n",
1576 dev_priv->gart_info.addr,
1577 dev_priv->pcigart_offset);
1578 } else {
1579 dev_priv->gart_info.gart_table_location =
1580 DRM_ATI_GART_MAIN;
1581 dev_priv->gart_info.addr =
1582 dev_priv->gart_info.bus_addr = 0;
1583 if (dev_priv->flags & CHIP_IS_PCIE) {
1584 DRM_ERROR
1585 ("Cannot use PCI Express without GART in FB memory\n");
1586 radeon_do_cleanup_cp(dev);
1587 return DRM_ERR(EINVAL);
1588 }
1589 }
1590
1591 if (!drm_ati_pcigart_init(dev, &dev_priv->gart_info)) {
1592 DRM_ERROR("failed to init PCI GART!\n");
1526 dev->dev_private = (void *)dev_priv; 1593 dev->dev_private = (void *)dev_priv;
1527 radeon_do_cleanup_cp(dev); 1594 radeon_do_cleanup_cp(dev);
1528 return DRM_ERR(ENOMEM); 1595 return DRM_ERR(ENOMEM);
1529 } 1596 }
1530 1597
1531 /* Turn on PCI GART */ 1598 /* Turn on PCI GART */
1532 radeon_set_pcigart( dev_priv, 1 ); 1599 radeon_set_pcigart(dev_priv, 1);
1533 } 1600 }
1534 1601
1535 radeon_cp_load_microcode( dev_priv ); 1602 radeon_cp_load_microcode(dev_priv);
1536 radeon_cp_init_ring_buffer( dev, dev_priv ); 1603 radeon_cp_init_ring_buffer(dev, dev_priv);
1537 1604
1538 dev_priv->last_buf = 0; 1605 dev_priv->last_buf = 0;
1539 1606
1540 dev->dev_private = (void *)dev_priv; 1607 dev->dev_private = (void *)dev_priv;
1541 1608
1542 radeon_do_engine_reset( dev ); 1609 radeon_do_engine_reset(dev);
1543 1610
1544 return 0; 1611 return 0;
1545} 1612}
1546 1613
1547static int radeon_do_cleanup_cp( drm_device_t *dev ) 1614static int radeon_do_cleanup_cp(drm_device_t * dev)
1548{ 1615{
1549 drm_radeon_private_t *dev_priv = dev->dev_private; 1616 drm_radeon_private_t *dev_priv = dev->dev_private;
1550 DRM_DEBUG( "\n" ); 1617 DRM_DEBUG("\n");
1551 1618
1552 /* Make sure interrupts are disabled here because the uninstall ioctl 1619 /* Make sure interrupts are disabled here because the uninstall ioctl
1553 * may not have been called from userspace and after dev_private 1620 * may not have been called from userspace and after dev_private
1554 * is freed, it's too late. 1621 * is freed, it's too late.
1555 */ 1622 */
1556 if ( dev->irq_enabled ) drm_irq_uninstall(dev); 1623 if (dev->irq_enabled)
1624 drm_irq_uninstall(dev);
1557 1625
1558#if __OS_HAS_AGP 1626#if __OS_HAS_AGP
1559 if ( !dev_priv->is_pci ) { 1627 if (!dev_priv->is_pci) {
1560 if ( dev_priv->cp_ring != NULL ) 1628 if (dev_priv->cp_ring != NULL)
1561 drm_core_ioremapfree( dev_priv->cp_ring, dev ); 1629 drm_core_ioremapfree(dev_priv->cp_ring, dev);
1562 if ( dev_priv->ring_rptr != NULL ) 1630 if (dev_priv->ring_rptr != NULL)
1563 drm_core_ioremapfree( dev_priv->ring_rptr, dev ); 1631 drm_core_ioremapfree(dev_priv->ring_rptr, dev);
1564 if ( dev->agp_buffer_map != NULL ) 1632 if (dev->agp_buffer_map != NULL) {
1565 { 1633 drm_core_ioremapfree(dev->agp_buffer_map, dev);
1566 drm_core_ioremapfree( dev->agp_buffer_map, dev );
1567 dev->agp_buffer_map = NULL; 1634 dev->agp_buffer_map = NULL;
1568 } 1635 }
1569 } else 1636 } else
1570#endif 1637#endif
1571 { 1638 {
1572 if (!drm_ati_pcigart_cleanup( dev, 1639 if (dev_priv->gart_info.bus_addr)
1573 dev_priv->phys_pci_gart, 1640 if (!drm_ati_pcigart_cleanup(dev, &dev_priv->gart_info))
1574 dev_priv->bus_pci_gart )) 1641 DRM_ERROR("failed to cleanup PCI GART!\n");
1575 DRM_ERROR( "failed to cleanup PCI GART!\n" ); 1642
1643 if (dev_priv->gart_info.gart_table_location == DRM_ATI_GART_FB) {
1644 drm_ioremapfree((void *)dev_priv->gart_info.addr,
1645 RADEON_PCIGART_TABLE_SIZE, dev);
1646 dev_priv->gart_info.addr = 0;
1647 }
1576 } 1648 }
1577 1649
1578 /* only clear to the start of flags */ 1650 /* only clear to the start of flags */
1579 memset(dev_priv, 0, offsetof(drm_radeon_private_t, flags)); 1651 memset(dev_priv, 0, offsetof(drm_radeon_private_t, flags));
1580 1652
1581 return 0; 1653 return 0;
1582} 1654}
1583 1655
1584/* This code will reinit the Radeon CP hardware after a resume from disc. 1656/* This code will reinit the Radeon CP hardware after a resume from disc.
1585 * AFAIK, it would be very difficult to pickle the state at suspend time, so 1657 * AFAIK, it would be very difficult to pickle the state at suspend time, so
1586 * here we make sure that all Radeon hardware initialisation is re-done without 1658 * here we make sure that all Radeon hardware initialisation is re-done without
1587 * affecting running applications. 1659 * affecting running applications.
1588 * 1660 *
1589 * Charl P. Botha <http://cpbotha.net> 1661 * Charl P. Botha <http://cpbotha.net>
1590 */ 1662 */
1591static int radeon_do_resume_cp( drm_device_t *dev ) 1663static int radeon_do_resume_cp(drm_device_t * dev)
1592{ 1664{
1593 drm_radeon_private_t *dev_priv = dev->dev_private; 1665 drm_radeon_private_t *dev_priv = dev->dev_private;
1594 1666
1595 if ( !dev_priv ) { 1667 if (!dev_priv) {
1596 DRM_ERROR( "Called with no initialization\n" ); 1668 DRM_ERROR("Called with no initialization\n");
1597 return DRM_ERR( EINVAL ); 1669 return DRM_ERR(EINVAL);
1598 } 1670 }
1599 1671
1600 DRM_DEBUG("Starting radeon_do_resume_cp()\n"); 1672 DRM_DEBUG("Starting radeon_do_resume_cp()\n");
1601 1673
1602#if __OS_HAS_AGP 1674#if __OS_HAS_AGP
1603 if ( !dev_priv->is_pci ) { 1675 if (!dev_priv->is_pci) {
1604 /* Turn off PCI GART */ 1676 /* Turn off PCI GART */
1605 radeon_set_pcigart( dev_priv, 0 ); 1677 radeon_set_pcigart(dev_priv, 0);
1606 } else 1678 } else
1607#endif 1679#endif
1608 { 1680 {
1609 /* Turn on PCI GART */ 1681 /* Turn on PCI GART */
1610 radeon_set_pcigart( dev_priv, 1 ); 1682 radeon_set_pcigart(dev_priv, 1);
1611 } 1683 }
1612 1684
1613 radeon_cp_load_microcode( dev_priv ); 1685 radeon_cp_load_microcode(dev_priv);
1614 radeon_cp_init_ring_buffer( dev, dev_priv ); 1686 radeon_cp_init_ring_buffer(dev, dev_priv);
1615 1687
1616 radeon_do_engine_reset( dev ); 1688 radeon_do_engine_reset(dev);
1617 1689
1618 DRM_DEBUG("radeon_do_resume_cp() complete\n"); 1690 DRM_DEBUG("radeon_do_resume_cp() complete\n");
1619 1691
1620 return 0; 1692 return 0;
1621} 1693}
1622 1694
1623 1695int radeon_cp_init(DRM_IOCTL_ARGS)
1624int radeon_cp_init( DRM_IOCTL_ARGS )
1625{ 1696{
1626 DRM_DEVICE; 1697 DRM_DEVICE;
1627 drm_radeon_init_t init; 1698 drm_radeon_init_t init;
1628 1699
1629 LOCK_TEST_WITH_RETURN( dev, filp ); 1700 LOCK_TEST_WITH_RETURN(dev, filp);
1630 1701
1631 DRM_COPY_FROM_USER_IOCTL( init, (drm_radeon_init_t __user *)data, sizeof(init) ); 1702 DRM_COPY_FROM_USER_IOCTL(init, (drm_radeon_init_t __user *) data,
1703 sizeof(init));
1632 1704
1633 if(init.func == RADEON_INIT_R300_CP) 1705 if (init.func == RADEON_INIT_R300_CP)
1634 r300_init_reg_flags(); 1706 r300_init_reg_flags();
1635 1707
1636 switch ( init.func ) { 1708 switch (init.func) {
1637 case RADEON_INIT_CP: 1709 case RADEON_INIT_CP:
1638 case RADEON_INIT_R200_CP: 1710 case RADEON_INIT_R200_CP:
1639 case RADEON_INIT_R300_CP: 1711 case RADEON_INIT_R300_CP:
1640 return radeon_do_init_cp( dev, &init ); 1712 return radeon_do_init_cp(dev, &init);
1641 case RADEON_CLEANUP_CP: 1713 case RADEON_CLEANUP_CP:
1642 return radeon_do_cleanup_cp( dev ); 1714 return radeon_do_cleanup_cp(dev);
1643 } 1715 }
1644 1716
1645 return DRM_ERR(EINVAL); 1717 return DRM_ERR(EINVAL);
1646} 1718}
1647 1719
1648int radeon_cp_start( DRM_IOCTL_ARGS ) 1720int radeon_cp_start(DRM_IOCTL_ARGS)
1649{ 1721{
1650 DRM_DEVICE; 1722 DRM_DEVICE;
1651 drm_radeon_private_t *dev_priv = dev->dev_private; 1723 drm_radeon_private_t *dev_priv = dev->dev_private;
1652 DRM_DEBUG( "\n" ); 1724 DRM_DEBUG("\n");
1653 1725
1654 LOCK_TEST_WITH_RETURN( dev, filp ); 1726 LOCK_TEST_WITH_RETURN(dev, filp);
1655 1727
1656 if ( dev_priv->cp_running ) { 1728 if (dev_priv->cp_running) {
1657 DRM_DEBUG( "%s while CP running\n", __FUNCTION__ ); 1729 DRM_DEBUG("%s while CP running\n", __FUNCTION__);
1658 return 0; 1730 return 0;
1659 } 1731 }
1660 if ( dev_priv->cp_mode == RADEON_CSQ_PRIDIS_INDDIS ) { 1732 if (dev_priv->cp_mode == RADEON_CSQ_PRIDIS_INDDIS) {
1661 DRM_DEBUG( "%s called with bogus CP mode (%d)\n", 1733 DRM_DEBUG("%s called with bogus CP mode (%d)\n",
1662 __FUNCTION__, dev_priv->cp_mode ); 1734 __FUNCTION__, dev_priv->cp_mode);
1663 return 0; 1735 return 0;
1664 } 1736 }
1665 1737
1666 radeon_do_cp_start( dev_priv ); 1738 radeon_do_cp_start(dev_priv);
1667 1739
1668 return 0; 1740 return 0;
1669} 1741}
@@ -1671,17 +1743,18 @@ int radeon_cp_start( DRM_IOCTL_ARGS )
1671/* Stop the CP. The engine must have been idled before calling this 1743/* Stop the CP. The engine must have been idled before calling this
1672 * routine. 1744 * routine.
1673 */ 1745 */
1674int radeon_cp_stop( DRM_IOCTL_ARGS ) 1746int radeon_cp_stop(DRM_IOCTL_ARGS)
1675{ 1747{
1676 DRM_DEVICE; 1748 DRM_DEVICE;
1677 drm_radeon_private_t *dev_priv = dev->dev_private; 1749 drm_radeon_private_t *dev_priv = dev->dev_private;
1678 drm_radeon_cp_stop_t stop; 1750 drm_radeon_cp_stop_t stop;
1679 int ret; 1751 int ret;
1680 DRM_DEBUG( "\n" ); 1752 DRM_DEBUG("\n");
1681 1753
1682 LOCK_TEST_WITH_RETURN( dev, filp ); 1754 LOCK_TEST_WITH_RETURN(dev, filp);
1683 1755
1684 DRM_COPY_FROM_USER_IOCTL( stop, (drm_radeon_cp_stop_t __user *)data, sizeof(stop) ); 1756 DRM_COPY_FROM_USER_IOCTL(stop, (drm_radeon_cp_stop_t __user *) data,
1757 sizeof(stop));
1685 1758
1686 if (!dev_priv->cp_running) 1759 if (!dev_priv->cp_running)
1687 return 0; 1760 return 0;
@@ -1689,32 +1762,32 @@ int radeon_cp_stop( DRM_IOCTL_ARGS )
1689 /* Flush any pending CP commands. This ensures any outstanding 1762 /* Flush any pending CP commands. This ensures any outstanding
1690 * commands are exectuted by the engine before we turn it off. 1763 * commands are exectuted by the engine before we turn it off.
1691 */ 1764 */
1692 if ( stop.flush ) { 1765 if (stop.flush) {
1693 radeon_do_cp_flush( dev_priv ); 1766 radeon_do_cp_flush(dev_priv);
1694 } 1767 }
1695 1768
1696 /* If we fail to make the engine go idle, we return an error 1769 /* If we fail to make the engine go idle, we return an error
1697 * code so that the DRM ioctl wrapper can try again. 1770 * code so that the DRM ioctl wrapper can try again.
1698 */ 1771 */
1699 if ( stop.idle ) { 1772 if (stop.idle) {
1700 ret = radeon_do_cp_idle( dev_priv ); 1773 ret = radeon_do_cp_idle(dev_priv);
1701 if ( ret ) return ret; 1774 if (ret)
1775 return ret;
1702 } 1776 }
1703 1777
1704 /* Finally, we can turn off the CP. If the engine isn't idle, 1778 /* Finally, we can turn off the CP. If the engine isn't idle,
1705 * we will get some dropped triangles as they won't be fully 1779 * we will get some dropped triangles as they won't be fully
1706 * rendered before the CP is shut down. 1780 * rendered before the CP is shut down.
1707 */ 1781 */
1708 radeon_do_cp_stop( dev_priv ); 1782 radeon_do_cp_stop(dev_priv);
1709 1783
1710 /* Reset the engine */ 1784 /* Reset the engine */
1711 radeon_do_engine_reset( dev ); 1785 radeon_do_engine_reset(dev);
1712 1786
1713 return 0; 1787 return 0;
1714} 1788}
1715 1789
1716 1790void radeon_do_release(drm_device_t * dev)
1717void radeon_do_release( drm_device_t *dev )
1718{ 1791{
1719 drm_radeon_private_t *dev_priv = dev->dev_private; 1792 drm_radeon_private_t *dev_priv = dev->dev_private;
1720 int i, ret; 1793 int i, ret;
@@ -1722,7 +1795,7 @@ void radeon_do_release( drm_device_t *dev )
1722 if (dev_priv) { 1795 if (dev_priv) {
1723 if (dev_priv->cp_running) { 1796 if (dev_priv->cp_running) {
1724 /* Stop the cp */ 1797 /* Stop the cp */
1725 while ((ret = radeon_do_cp_idle( dev_priv )) != 0) { 1798 while ((ret = radeon_do_cp_idle(dev_priv)) != 0) {
1726 DRM_DEBUG("radeon_do_cp_idle %d\n", ret); 1799 DRM_DEBUG("radeon_do_cp_idle %d\n", ret);
1727#ifdef __linux__ 1800#ifdef __linux__
1728 schedule(); 1801 schedule();
@@ -1730,47 +1803,49 @@ void radeon_do_release( drm_device_t *dev )
1730 tsleep(&ret, PZERO, "rdnrel", 1); 1803 tsleep(&ret, PZERO, "rdnrel", 1);
1731#endif 1804#endif
1732 } 1805 }
1733 radeon_do_cp_stop( dev_priv ); 1806 radeon_do_cp_stop(dev_priv);
1734 radeon_do_engine_reset( dev ); 1807 radeon_do_engine_reset(dev);
1735 } 1808 }
1736 1809
1737 /* Disable *all* interrupts */ 1810 /* Disable *all* interrupts */
1738 if (dev_priv->mmio) /* remove this after permanent addmaps */ 1811 if (dev_priv->mmio) /* remove this after permanent addmaps */
1739 RADEON_WRITE( RADEON_GEN_INT_CNTL, 0 ); 1812 RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
1740 1813
1741 if (dev_priv->mmio) {/* remove all surfaces */ 1814 if (dev_priv->mmio) { /* remove all surfaces */
1742 for (i = 0; i < RADEON_MAX_SURFACES; i++) { 1815 for (i = 0; i < RADEON_MAX_SURFACES; i++) {
1743 RADEON_WRITE(RADEON_SURFACE0_INFO + 16*i, 0); 1816 RADEON_WRITE(RADEON_SURFACE0_INFO + 16 * i, 0);
1744 RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND + 16*i, 0); 1817 RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND +
1745 RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND + 16*i, 0); 1818 16 * i, 0);
1819 RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND +
1820 16 * i, 0);
1746 } 1821 }
1747 } 1822 }
1748 1823
1749 /* Free memory heap structures */ 1824 /* Free memory heap structures */
1750 radeon_mem_takedown( &(dev_priv->gart_heap) ); 1825 radeon_mem_takedown(&(dev_priv->gart_heap));
1751 radeon_mem_takedown( &(dev_priv->fb_heap) ); 1826 radeon_mem_takedown(&(dev_priv->fb_heap));
1752 1827
1753 /* deallocate kernel resources */ 1828 /* deallocate kernel resources */
1754 radeon_do_cleanup_cp( dev ); 1829 radeon_do_cleanup_cp(dev);
1755 } 1830 }
1756} 1831}
1757 1832
1758/* Just reset the CP ring. Called as part of an X Server engine reset. 1833/* Just reset the CP ring. Called as part of an X Server engine reset.
1759 */ 1834 */
1760int radeon_cp_reset( DRM_IOCTL_ARGS ) 1835int radeon_cp_reset(DRM_IOCTL_ARGS)
1761{ 1836{
1762 DRM_DEVICE; 1837 DRM_DEVICE;
1763 drm_radeon_private_t *dev_priv = dev->dev_private; 1838 drm_radeon_private_t *dev_priv = dev->dev_private;
1764 DRM_DEBUG( "\n" ); 1839 DRM_DEBUG("\n");
1765 1840
1766 LOCK_TEST_WITH_RETURN( dev, filp ); 1841 LOCK_TEST_WITH_RETURN(dev, filp);
1767 1842
1768 if ( !dev_priv ) { 1843 if (!dev_priv) {
1769 DRM_DEBUG( "%s called before init done\n", __FUNCTION__ ); 1844 DRM_DEBUG("%s called before init done\n", __FUNCTION__);
1770 return DRM_ERR(EINVAL); 1845 return DRM_ERR(EINVAL);
1771 } 1846 }
1772 1847
1773 radeon_do_cp_reset( dev_priv ); 1848 radeon_do_cp_reset(dev_priv);
1774 1849
1775 /* The CP is no longer running after an engine reset */ 1850 /* The CP is no longer running after an engine reset */
1776 dev_priv->cp_running = 0; 1851 dev_priv->cp_running = 0;
@@ -1778,50 +1853,47 @@ int radeon_cp_reset( DRM_IOCTL_ARGS )
1778 return 0; 1853 return 0;
1779} 1854}
1780 1855
1781int radeon_cp_idle( DRM_IOCTL_ARGS ) 1856int radeon_cp_idle(DRM_IOCTL_ARGS)
1782{ 1857{
1783 DRM_DEVICE; 1858 DRM_DEVICE;
1784 drm_radeon_private_t *dev_priv = dev->dev_private; 1859 drm_radeon_private_t *dev_priv = dev->dev_private;
1785 DRM_DEBUG( "\n" ); 1860 DRM_DEBUG("\n");
1786 1861
1787 LOCK_TEST_WITH_RETURN( dev, filp ); 1862 LOCK_TEST_WITH_RETURN(dev, filp);
1788 1863
1789 return radeon_do_cp_idle( dev_priv ); 1864 return radeon_do_cp_idle(dev_priv);
1790} 1865}
1791 1866
1792/* Added by Charl P. Botha to call radeon_do_resume_cp(). 1867/* Added by Charl P. Botha to call radeon_do_resume_cp().
1793 */ 1868 */
1794int radeon_cp_resume( DRM_IOCTL_ARGS ) 1869int radeon_cp_resume(DRM_IOCTL_ARGS)
1795{ 1870{
1796 DRM_DEVICE; 1871 DRM_DEVICE;
1797 1872
1798 return radeon_do_resume_cp(dev); 1873 return radeon_do_resume_cp(dev);
1799} 1874}
1800 1875
1801 1876int radeon_engine_reset(DRM_IOCTL_ARGS)
1802int radeon_engine_reset( DRM_IOCTL_ARGS )
1803{ 1877{
1804 DRM_DEVICE; 1878 DRM_DEVICE;
1805 DRM_DEBUG( "\n" ); 1879 DRM_DEBUG("\n");
1806 1880
1807 LOCK_TEST_WITH_RETURN( dev, filp ); 1881 LOCK_TEST_WITH_RETURN(dev, filp);
1808 1882
1809 return radeon_do_engine_reset( dev ); 1883 return radeon_do_engine_reset(dev);
1810} 1884}
1811 1885
1812
1813/* ================================================================ 1886/* ================================================================
1814 * Fullscreen mode 1887 * Fullscreen mode
1815 */ 1888 */
1816 1889
1817/* KW: Deprecated to say the least: 1890/* KW: Deprecated to say the least:
1818 */ 1891 */
1819int radeon_fullscreen( DRM_IOCTL_ARGS ) 1892int radeon_fullscreen(DRM_IOCTL_ARGS)
1820{ 1893{
1821 return 0; 1894 return 0;
1822} 1895}
1823 1896
1824
1825/* ================================================================ 1897/* ================================================================
1826 * Freelist management 1898 * Freelist management
1827 */ 1899 */
@@ -1830,20 +1902,20 @@ int radeon_fullscreen( DRM_IOCTL_ARGS )
1830 * bufs until freelist code is used. Note this hides a problem with 1902 * bufs until freelist code is used. Note this hides a problem with
1831 * the scratch register * (used to keep track of last buffer 1903 * the scratch register * (used to keep track of last buffer
1832 * completed) being written to before * the last buffer has actually 1904 * completed) being written to before * the last buffer has actually
1833 * completed rendering. 1905 * completed rendering.
1834 * 1906 *
1835 * KW: It's also a good way to find free buffers quickly. 1907 * KW: It's also a good way to find free buffers quickly.
1836 * 1908 *
1837 * KW: Ideally this loop wouldn't exist, and freelist_get wouldn't 1909 * KW: Ideally this loop wouldn't exist, and freelist_get wouldn't
1838 * sleep. However, bugs in older versions of radeon_accel.c mean that 1910 * sleep. However, bugs in older versions of radeon_accel.c mean that
1839 * we essentially have to do this, else old clients will break. 1911 * we essentially have to do this, else old clients will break.
1840 * 1912 *
1841 * However, it does leave open a potential deadlock where all the 1913 * However, it does leave open a potential deadlock where all the
1842 * buffers are held by other clients, which can't release them because 1914 * buffers are held by other clients, which can't release them because
1843 * they can't get the lock. 1915 * they can't get the lock.
1844 */ 1916 */
1845 1917
1846drm_buf_t *radeon_freelist_get( drm_device_t *dev ) 1918drm_buf_t *radeon_freelist_get(drm_device_t * dev)
1847{ 1919{
1848 drm_device_dma_t *dma = dev->dma; 1920 drm_device_dma_t *dma = dev->dma;
1849 drm_radeon_private_t *dev_priv = dev->dev_private; 1921 drm_radeon_private_t *dev_priv = dev->dev_private;
@@ -1852,19 +1924,19 @@ drm_buf_t *radeon_freelist_get( drm_device_t *dev )
1852 int i, t; 1924 int i, t;
1853 int start; 1925 int start;
1854 1926
1855 if ( ++dev_priv->last_buf >= dma->buf_count ) 1927 if (++dev_priv->last_buf >= dma->buf_count)
1856 dev_priv->last_buf = 0; 1928 dev_priv->last_buf = 0;
1857 1929
1858 start = dev_priv->last_buf; 1930 start = dev_priv->last_buf;
1859 1931
1860 for ( t = 0 ; t < dev_priv->usec_timeout ; t++ ) { 1932 for (t = 0; t < dev_priv->usec_timeout; t++) {
1861 u32 done_age = GET_SCRATCH( 1 ); 1933 u32 done_age = GET_SCRATCH(1);
1862 DRM_DEBUG("done_age = %d\n",done_age); 1934 DRM_DEBUG("done_age = %d\n", done_age);
1863 for ( i = start ; i < dma->buf_count ; i++ ) { 1935 for (i = start; i < dma->buf_count; i++) {
1864 buf = dma->buflist[i]; 1936 buf = dma->buflist[i];
1865 buf_priv = buf->dev_private; 1937 buf_priv = buf->dev_private;
1866 if ( buf->filp == 0 || (buf->pending && 1938 if (buf->filp == 0 || (buf->pending &&
1867 buf_priv->age <= done_age) ) { 1939 buf_priv->age <= done_age)) {
1868 dev_priv->stats.requested_bufs++; 1940 dev_priv->stats.requested_bufs++;
1869 buf->pending = 0; 1941 buf->pending = 0;
1870 return buf; 1942 return buf;
@@ -1873,16 +1945,17 @@ drm_buf_t *radeon_freelist_get( drm_device_t *dev )
1873 } 1945 }
1874 1946
1875 if (t) { 1947 if (t) {
1876 DRM_UDELAY( 1 ); 1948 DRM_UDELAY(1);
1877 dev_priv->stats.freelist_loops++; 1949 dev_priv->stats.freelist_loops++;
1878 } 1950 }
1879 } 1951 }
1880 1952
1881 DRM_DEBUG( "returning NULL!\n" ); 1953 DRM_DEBUG("returning NULL!\n");
1882 return NULL; 1954 return NULL;
1883} 1955}
1956
1884#if 0 1957#if 0
1885drm_buf_t *radeon_freelist_get( drm_device_t *dev ) 1958drm_buf_t *radeon_freelist_get(drm_device_t * dev)
1886{ 1959{
1887 drm_device_dma_t *dma = dev->dma; 1960 drm_device_dma_t *dma = dev->dma;
1888 drm_radeon_private_t *dev_priv = dev->dev_private; 1961 drm_radeon_private_t *dev_priv = dev->dev_private;
@@ -1892,18 +1965,18 @@ drm_buf_t *radeon_freelist_get( drm_device_t *dev )
1892 int start; 1965 int start;
1893 u32 done_age = DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1)); 1966 u32 done_age = DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1));
1894 1967
1895 if ( ++dev_priv->last_buf >= dma->buf_count ) 1968 if (++dev_priv->last_buf >= dma->buf_count)
1896 dev_priv->last_buf = 0; 1969 dev_priv->last_buf = 0;
1897 1970
1898 start = dev_priv->last_buf; 1971 start = dev_priv->last_buf;
1899 dev_priv->stats.freelist_loops++; 1972 dev_priv->stats.freelist_loops++;
1900 1973
1901 for ( t = 0 ; t < 2 ; t++ ) { 1974 for (t = 0; t < 2; t++) {
1902 for ( i = start ; i < dma->buf_count ; i++ ) { 1975 for (i = start; i < dma->buf_count; i++) {
1903 buf = dma->buflist[i]; 1976 buf = dma->buflist[i];
1904 buf_priv = buf->dev_private; 1977 buf_priv = buf->dev_private;
1905 if ( buf->filp == 0 || (buf->pending && 1978 if (buf->filp == 0 || (buf->pending &&
1906 buf_priv->age <= done_age) ) { 1979 buf_priv->age <= done_age)) {
1907 dev_priv->stats.requested_bufs++; 1980 dev_priv->stats.requested_bufs++;
1908 buf->pending = 0; 1981 buf->pending = 0;
1909 return buf; 1982 return buf;
@@ -1916,73 +1989,74 @@ drm_buf_t *radeon_freelist_get( drm_device_t *dev )
1916} 1989}
1917#endif 1990#endif
1918 1991
1919void radeon_freelist_reset( drm_device_t *dev ) 1992void radeon_freelist_reset(drm_device_t * dev)
1920{ 1993{
1921 drm_device_dma_t *dma = dev->dma; 1994 drm_device_dma_t *dma = dev->dma;
1922 drm_radeon_private_t *dev_priv = dev->dev_private; 1995 drm_radeon_private_t *dev_priv = dev->dev_private;
1923 int i; 1996 int i;
1924 1997
1925 dev_priv->last_buf = 0; 1998 dev_priv->last_buf = 0;
1926 for ( i = 0 ; i < dma->buf_count ; i++ ) { 1999 for (i = 0; i < dma->buf_count; i++) {
1927 drm_buf_t *buf = dma->buflist[i]; 2000 drm_buf_t *buf = dma->buflist[i];
1928 drm_radeon_buf_priv_t *buf_priv = buf->dev_private; 2001 drm_radeon_buf_priv_t *buf_priv = buf->dev_private;
1929 buf_priv->age = 0; 2002 buf_priv->age = 0;
1930 } 2003 }
1931} 2004}
1932 2005
1933
1934/* ================================================================ 2006/* ================================================================
1935 * CP command submission 2007 * CP command submission
1936 */ 2008 */
1937 2009
1938int radeon_wait_ring( drm_radeon_private_t *dev_priv, int n ) 2010int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n)
1939{ 2011{
1940 drm_radeon_ring_buffer_t *ring = &dev_priv->ring; 2012 drm_radeon_ring_buffer_t *ring = &dev_priv->ring;
1941 int i; 2013 int i;
1942 u32 last_head = GET_RING_HEAD( dev_priv ); 2014 u32 last_head = GET_RING_HEAD(dev_priv);
1943 2015
1944 for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) { 2016 for (i = 0; i < dev_priv->usec_timeout; i++) {
1945 u32 head = GET_RING_HEAD( dev_priv ); 2017 u32 head = GET_RING_HEAD(dev_priv);
1946 2018
1947 ring->space = (head - ring->tail) * sizeof(u32); 2019 ring->space = (head - ring->tail) * sizeof(u32);
1948 if ( ring->space <= 0 ) 2020 if (ring->space <= 0)
1949 ring->space += ring->size; 2021 ring->space += ring->size;
1950 if ( ring->space > n ) 2022 if (ring->space > n)
1951 return 0; 2023 return 0;
1952 2024
1953 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; 2025 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
1954 2026
1955 if (head != last_head) 2027 if (head != last_head)
1956 i = 0; 2028 i = 0;
1957 last_head = head; 2029 last_head = head;
1958 2030
1959 DRM_UDELAY( 1 ); 2031 DRM_UDELAY(1);
1960 } 2032 }
1961 2033
1962 /* FIXME: This return value is ignored in the BEGIN_RING macro! */ 2034 /* FIXME: This return value is ignored in the BEGIN_RING macro! */
1963#if RADEON_FIFO_DEBUG 2035#if RADEON_FIFO_DEBUG
1964 radeon_status( dev_priv ); 2036 radeon_status(dev_priv);
1965 DRM_ERROR( "failed!\n" ); 2037 DRM_ERROR("failed!\n");
1966#endif 2038#endif
1967 return DRM_ERR(EBUSY); 2039 return DRM_ERR(EBUSY);
1968} 2040}
1969 2041
1970static int radeon_cp_get_buffers( DRMFILE filp, drm_device_t *dev, drm_dma_t *d ) 2042static int radeon_cp_get_buffers(DRMFILE filp, drm_device_t * dev,
2043 drm_dma_t * d)
1971{ 2044{
1972 int i; 2045 int i;
1973 drm_buf_t *buf; 2046 drm_buf_t *buf;
1974 2047
1975 for ( i = d->granted_count ; i < d->request_count ; i++ ) { 2048 for (i = d->granted_count; i < d->request_count; i++) {
1976 buf = radeon_freelist_get( dev ); 2049 buf = radeon_freelist_get(dev);
1977 if ( !buf ) return DRM_ERR(EBUSY); /* NOTE: broken client */ 2050 if (!buf)
2051 return DRM_ERR(EBUSY); /* NOTE: broken client */
1978 2052
1979 buf->filp = filp; 2053 buf->filp = filp;
1980 2054
1981 if ( DRM_COPY_TO_USER( &d->request_indices[i], &buf->idx, 2055 if (DRM_COPY_TO_USER(&d->request_indices[i], &buf->idx,
1982 sizeof(buf->idx) ) ) 2056 sizeof(buf->idx)))
1983 return DRM_ERR(EFAULT); 2057 return DRM_ERR(EFAULT);
1984 if ( DRM_COPY_TO_USER( &d->request_sizes[i], &buf->total, 2058 if (DRM_COPY_TO_USER(&d->request_sizes[i], &buf->total,
1985 sizeof(buf->total) ) ) 2059 sizeof(buf->total)))
1986 return DRM_ERR(EFAULT); 2060 return DRM_ERR(EFAULT);
1987 2061
1988 d->granted_count++; 2062 d->granted_count++;
@@ -1990,7 +2064,7 @@ static int radeon_cp_get_buffers( DRMFILE filp, drm_device_t *dev, drm_dma_t *d
1990 return 0; 2064 return 0;
1991} 2065}
1992 2066
1993int radeon_cp_buffers( DRM_IOCTL_ARGS ) 2067int radeon_cp_buffers(DRM_IOCTL_ARGS)
1994{ 2068{
1995 DRM_DEVICE; 2069 DRM_DEVICE;
1996 drm_device_dma_t *dma = dev->dma; 2070 drm_device_dma_t *dma = dev->dma;
@@ -1998,33 +2072,33 @@ int radeon_cp_buffers( DRM_IOCTL_ARGS )
1998 drm_dma_t __user *argp = (void __user *)data; 2072 drm_dma_t __user *argp = (void __user *)data;
1999 drm_dma_t d; 2073 drm_dma_t d;
2000 2074
2001 LOCK_TEST_WITH_RETURN( dev, filp ); 2075 LOCK_TEST_WITH_RETURN(dev, filp);
2002 2076
2003 DRM_COPY_FROM_USER_IOCTL( d, argp, sizeof(d) ); 2077 DRM_COPY_FROM_USER_IOCTL(d, argp, sizeof(d));
2004 2078
2005 /* Please don't send us buffers. 2079 /* Please don't send us buffers.
2006 */ 2080 */
2007 if ( d.send_count != 0 ) { 2081 if (d.send_count != 0) {
2008 DRM_ERROR( "Process %d trying to send %d buffers via drmDMA\n", 2082 DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n",
2009 DRM_CURRENTPID, d.send_count ); 2083 DRM_CURRENTPID, d.send_count);
2010 return DRM_ERR(EINVAL); 2084 return DRM_ERR(EINVAL);
2011 } 2085 }
2012 2086
2013 /* We'll send you buffers. 2087 /* We'll send you buffers.
2014 */ 2088 */
2015 if ( d.request_count < 0 || d.request_count > dma->buf_count ) { 2089 if (d.request_count < 0 || d.request_count > dma->buf_count) {
2016 DRM_ERROR( "Process %d trying to get %d buffers (of %d max)\n", 2090 DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n",
2017 DRM_CURRENTPID, d.request_count, dma->buf_count ); 2091 DRM_CURRENTPID, d.request_count, dma->buf_count);
2018 return DRM_ERR(EINVAL); 2092 return DRM_ERR(EINVAL);
2019 } 2093 }
2020 2094
2021 d.granted_count = 0; 2095 d.granted_count = 0;
2022 2096
2023 if ( d.request_count ) { 2097 if (d.request_count) {
2024 ret = radeon_cp_get_buffers( filp, dev, &d ); 2098 ret = radeon_cp_get_buffers(filp, dev, &d);
2025 } 2099 }
2026 2100
2027 DRM_COPY_TO_USER_IOCTL( argp, d, sizeof(d) ); 2101 DRM_COPY_TO_USER_IOCTL(argp, d, sizeof(d));
2028 2102
2029 return ret; 2103 return ret;
2030} 2104}
@@ -2051,13 +2125,16 @@ int radeon_driver_preinit(struct drm_device *dev, unsigned long flags)
2051 dev_priv->flags |= CHIP_HAS_HIERZ; 2125 dev_priv->flags |= CHIP_HAS_HIERZ;
2052 break; 2126 break;
2053 default: 2127 default:
2054 /* all other chips have no hierarchical z buffer */ 2128 /* all other chips have no hierarchical z buffer */
2055 break; 2129 break;
2056 } 2130 }
2057 2131
2058 if (drm_device_is_agp(dev)) 2132 if (drm_device_is_agp(dev))
2059 dev_priv->flags |= CHIP_IS_AGP; 2133 dev_priv->flags |= CHIP_IS_AGP;
2060 2134
2135 if (drm_device_is_pcie(dev))
2136 dev_priv->flags |= CHIP_IS_PCIE;
2137
2061 DRM_DEBUG("%s card detected\n", 2138 DRM_DEBUG("%s card detected\n",
2062 ((dev_priv->flags & CHIP_IS_AGP) ? "AGP" : "PCI")); 2139 ((dev_priv->flags & CHIP_IS_AGP) ? "AGP" : "PCI"));
2063 return ret; 2140 return ret;
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-08 02:29:56 -0500