drm: add initial r500 drm support

This adds CP support for the r500 series of chips, and allows
accel 2D support on these chips with a new radeon driver.

Signed-off-by: Dave Airlie <airlied@redhat.com>

1 files changed, 90 insertions, 45 deletions

diff --git a/drivers/char/drm/radeon_cp.c b/drivers/char/drm/radeon_cp.c
index 020323bd1626..5dc799ab86b8 100644
--- a/drivers/char/drm/radeon_cp.c
+++ b/drivers/char/drm/radeon_cp.c
@@ -816,6 +816,46 @@ static const u32 R300_cp_microcode[][2] = {
         {0000000000, 0000000000},
 };
 
+static u32 RADEON_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
+{
+        u32 ret;
+        RADEON_WRITE(R520_MC_IND_INDEX, 0x7f0000 | (addr & 0xff));
+        ret = RADEON_READ(R520_MC_IND_DATA);
+        RADEON_WRITE(R520_MC_IND_INDEX, 0);
+        return ret;
+}
+
+u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv)
+{
+
+        if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
+                return RADEON_READ_MCIND(dev_priv, RV515_MC_FB_LOCATION);
+        else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
+                return RADEON_READ_MCIND(dev_priv, R520_MC_FB_LOCATION);
+        else
+                return RADEON_READ(RADEON_MC_FB_LOCATION);
+}
+
+static void radeon_write_fb_location(drm_radeon_private_t *dev_priv, u32 fb_loc)
+{
+        if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
+                RADEON_WRITE_MCIND(RV515_MC_FB_LOCATION, fb_loc);
+        else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
+                RADEON_WRITE_MCIND(R520_MC_FB_LOCATION, fb_loc);
+        else
+                RADEON_WRITE(RADEON_MC_FB_LOCATION, fb_loc);
+}
+
+static void radeon_write_agp_location(drm_radeon_private_t *dev_priv, u32 agp_loc)
+{
+        if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
+                RADEON_WRITE_MCIND(RV515_MC_AGP_LOCATION, agp_loc);
+        else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
+                RADEON_WRITE_MCIND(R520_MC_AGP_LOCATION, agp_loc);
+        else
+                RADEON_WRITE(RADEON_MC_AGP_LOCATION, agp_loc);
+}
+
 static int RADEON_READ_PLL(struct drm_device * dev, int addr)
 {
         drm_radeon_private_t *dev_priv = dev->dev_private;
@@ -824,7 +864,7 @@ static int RADEON_READ_PLL(struct drm_device * dev, int addr)
         return RADEON_READ(RADEON_CLOCK_CNTL_DATA);
 }
 
-static int RADEON_READ_PCIE(drm_radeon_private_t *dev_priv, int addr)
+static u32 RADEON_READ_PCIE(drm_radeon_private_t *dev_priv, int addr)
 {
         RADEON_WRITE8(RADEON_PCIE_INDEX, addr & 0xff);
         return RADEON_READ(RADEON_PCIE_DATA);
@@ -1074,41 +1114,43 @@ static int radeon_do_engine_reset(struct drm_device * dev)
 
         radeon_do_pixcache_flush(dev_priv);
 
-        clock_cntl_index = RADEON_READ(RADEON_CLOCK_CNTL_INDEX);
-        mclk_cntl = RADEON_READ_PLL(dev, RADEON_MCLK_CNTL);
-
-        RADEON_WRITE_PLL(RADEON_MCLK_CNTL, (mclk_cntl |
-                                            RADEON_FORCEON_MCLKA |
-                                            RADEON_FORCEON_MCLKB |
-                                            RADEON_FORCEON_YCLKA |
-                                            RADEON_FORCEON_YCLKB |
-                                            RADEON_FORCEON_MC |
-                                            RADEON_FORCEON_AIC));
-
-        rbbm_soft_reset = RADEON_READ(RADEON_RBBM_SOFT_RESET);
-
-        RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset |
-                                              RADEON_SOFT_RESET_CP |
-                                              RADEON_SOFT_RESET_HI |
-                                              RADEON_SOFT_RESET_SE |
-                                              RADEON_SOFT_RESET_RE |
-                                              RADEON_SOFT_RESET_PP |
-                                              RADEON_SOFT_RESET_E2 |
-                                              RADEON_SOFT_RESET_RB));
-        RADEON_READ(RADEON_RBBM_SOFT_RESET);
-        RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset &
-                                              ~(RADEON_SOFT_RESET_CP |
-                                                RADEON_SOFT_RESET_HI |
-                                                RADEON_SOFT_RESET_SE |
-                                                RADEON_SOFT_RESET_RE |
-                                                RADEON_SOFT_RESET_PP |
-                                                RADEON_SOFT_RESET_E2 |
-                                                RADEON_SOFT_RESET_RB)));
-        RADEON_READ(RADEON_RBBM_SOFT_RESET);
-
-        RADEON_WRITE_PLL(RADEON_MCLK_CNTL, mclk_cntl);
-        RADEON_WRITE(RADEON_CLOCK_CNTL_INDEX, clock_cntl_index);
-        RADEON_WRITE(RADEON_RBBM_SOFT_RESET, rbbm_soft_reset);
+        if ((dev_priv->flags & RADEON_FAMILY_MASK) < CHIP_RV515) {
+                clock_cntl_index = RADEON_READ(RADEON_CLOCK_CNTL_INDEX);
+                mclk_cntl = RADEON_READ_PLL(dev, RADEON_MCLK_CNTL);
+
+                RADEON_WRITE_PLL(RADEON_MCLK_CNTL, (mclk_cntl |
+                                                    RADEON_FORCEON_MCLKA |
+                                                    RADEON_FORCEON_MCLKB |
+                                                    RADEON_FORCEON_YCLKA |
+                                                    RADEON_FORCEON_YCLKB |
+                                                    RADEON_FORCEON_MC |
+                                                    RADEON_FORCEON_AIC));
+
+                rbbm_soft_reset = RADEON_READ(RADEON_RBBM_SOFT_RESET);
+
+                RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset |
+                                                      RADEON_SOFT_RESET_CP |
+                                                      RADEON_SOFT_RESET_HI |
+                                                      RADEON_SOFT_RESET_SE |
+                                                      RADEON_SOFT_RESET_RE |
+                                                      RADEON_SOFT_RESET_PP |
+                                                      RADEON_SOFT_RESET_E2 |
+                                                      RADEON_SOFT_RESET_RB));
+                RADEON_READ(RADEON_RBBM_SOFT_RESET);
+                RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset &
+                                                      ~(RADEON_SOFT_RESET_CP |
+                                                        RADEON_SOFT_RESET_HI |
+                                                        RADEON_SOFT_RESET_SE |
+                                                        RADEON_SOFT_RESET_RE |
+                                                        RADEON_SOFT_RESET_PP |
+                                                        RADEON_SOFT_RESET_E2 |
+                                                        RADEON_SOFT_RESET_RB)));
+                RADEON_READ(RADEON_RBBM_SOFT_RESET);
+
+                RADEON_WRITE_PLL(RADEON_MCLK_CNTL, mclk_cntl);
+                RADEON_WRITE(RADEON_CLOCK_CNTL_INDEX, clock_cntl_index);
+                RADEON_WRITE(RADEON_RBBM_SOFT_RESET, rbbm_soft_reset);
+        }
 
         /* Reset the CP ring */
         radeon_do_cp_reset(dev_priv);
@@ -1134,14 +1176,14 @@ static void radeon_cp_init_ring_buffer(struct drm_device * dev,
          * always appended to the fb which is not necessarily the case
          */
         if (!dev_priv->new_memmap)
-                RADEON_WRITE(RADEON_MC_FB_LOCATION,
+                radeon_write_fb_location(dev_priv,
                              ((dev_priv->gart_vm_start - 1) & 0xffff0000)
                              | (dev_priv->fb_location >> 16));
 
 #if __OS_HAS_AGP
         if (dev_priv->flags & RADEON_IS_AGP) {
                 RADEON_WRITE(RADEON_AGP_BASE, (unsigned int)dev->agp->base);
-                RADEON_WRITE(RADEON_MC_AGP_LOCATION,
+                radeon_write_agp_location(dev_priv,
                              (((dev_priv->gart_vm_start - 1 +
                                 dev_priv->gart_size) & 0xffff0000) |
                               (dev_priv->gart_vm_start >> 16)));
@@ -1305,7 +1347,7 @@ static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on)
 
                 RADEON_WRITE(RADEON_AGP_BASE, (unsigned int)dev_priv->gart_vm_start);
                 dev_priv->gart_size = 32*1024*1024;
-                RADEON_WRITE(RADEON_MC_AGP_LOCATION,
+                radeon_write_agp_location(dev_priv,
                              (((dev_priv->gart_vm_start - 1 +
                                dev_priv->gart_size) & 0xffff0000) |
                              (dev_priv->gart_vm_start >> 16)));
@@ -1339,7 +1381,7 @@ static void radeon_set_pciegart(drm_radeon_private_t * dev_priv, int on)
                                   dev_priv->gart_vm_start +
                                   dev_priv->gart_size - 1);
 
-                RADEON_WRITE(RADEON_MC_AGP_LOCATION, 0xffffffc0);       /* ?? */
+                radeon_write_agp_location(dev_priv, 0xffffffc0); /* ?? */
 
                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
                                   RADEON_PCIE_TX_GART_EN);
@@ -1382,7 +1424,7 @@ static void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on)
 
                 /* Turn off AGP aperture -- is this required for PCI GART?
                  */
-                RADEON_WRITE(RADEON_MC_AGP_LOCATION, 0xffffffc0);       /* ?? */
+                radeon_write_agp_location(dev_priv, 0xffffffc0);
                 RADEON_WRITE(RADEON_AGP_COMMAND, 0);    /* clear AGP_COMMAND */
         } else {
                 RADEON_WRITE(RADEON_AIC_CNTL,
@@ -1587,10 +1629,9 @@ static int radeon_do_init_cp(struct drm_device * dev, drm_radeon_init_t * init)
                           dev->agp_buffer_map->handle);
         }
 
-        dev_priv->fb_location = (RADEON_READ(RADEON_MC_FB_LOCATION)
-                                 & 0xffff) << 16;
+        dev_priv->fb_location = (radeon_read_fb_location(dev_priv) & 0xffff) << 16;
         dev_priv->fb_size =
-                ((RADEON_READ(RADEON_MC_FB_LOCATION) & 0xffff0000u) + 0x10000)
+                ((radeon_read_fb_location(dev_priv) & 0xffff0000u) + 0x10000)
                 - dev_priv->fb_location;
 
         dev_priv->front_pitch_offset = (((dev_priv->front_pitch / 64) << 22) |
@@ -1841,7 +1882,7 @@ int radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_pri
         LOCK_TEST_WITH_RETURN(dev, file_priv);
 
         if (init->func == RADEON_INIT_R300_CP)
-                r300_init_reg_flags();
+                r300_init_reg_flags(dev);
 
         switch (init->func) {
         case RADEON_INIT_CP:
@@ -2250,6 +2291,10 @@ int radeon_driver_load(struct drm_device *dev, unsigned long flags)
         case CHIP_R350:
         case CHIP_R420:
         case CHIP_RV410:
+        case CHIP_RV515:
+        case CHIP_R520:
+        case CHIP_RV570:
+        case CHIP_R580:
                 dev_priv->flags |= RADEON_HAS_HIERZ;
                 break;
         default: