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authorDave Airlie <airlied@starflyer.(none)>2005-09-25 00:28:13 -0400
committerDave Airlie <airlied@linux.ie>2005-09-25 00:28:13 -0400
commitb5e89ed53ed8d24f83ba1941c07382af00ed238e (patch)
tree747bae7a565f88a2e1d5974776eeb054a932c505 /drivers/char/drm/r128_state.c
parent99a2657a29e2d623c3568cd86b27cac13fb63140 (diff)
drm: lindent the drm directory.
I've been threatening this for a while, so no point hanging around. This lindents the DRM code which was always really bad in tabbing department. I've also fixed some misnamed files in comments and removed some trailing whitespace. Signed-off-by: Dave Airlie <airlied@linux.ie>
Diffstat (limited to 'drivers/char/drm/r128_state.c')
-rw-r--r--drivers/char/drm/r128_state.c1386
1 files changed, 681 insertions, 705 deletions
diff --git a/drivers/char/drm/r128_state.c b/drivers/char/drm/r128_state.c
index 426a71c049d9..14479cc08a57 100644
--- a/drivers/char/drm/r128_state.c
+++ b/drivers/char/drm/r128_state.c
@@ -32,235 +32,233 @@
32#include "r128_drm.h" 32#include "r128_drm.h"
33#include "r128_drv.h" 33#include "r128_drv.h"
34 34
35
36/* ================================================================ 35/* ================================================================
37 * CCE hardware state programming functions 36 * CCE hardware state programming functions
38 */ 37 */
39 38
40static void r128_emit_clip_rects( drm_r128_private_t *dev_priv, 39static void r128_emit_clip_rects(drm_r128_private_t * dev_priv,
41 drm_clip_rect_t *boxes, int count ) 40 drm_clip_rect_t * boxes, int count)
42{ 41{
43 u32 aux_sc_cntl = 0x00000000; 42 u32 aux_sc_cntl = 0x00000000;
44 RING_LOCALS; 43 RING_LOCALS;
45 DRM_DEBUG( " %s\n", __FUNCTION__ ); 44 DRM_DEBUG(" %s\n", __FUNCTION__);
46 45
47 BEGIN_RING( (count < 3? count: 3) * 5 + 2 ); 46 BEGIN_RING((count < 3 ? count : 3) * 5 + 2);
48 47
49 if ( count >= 1 ) { 48 if (count >= 1) {
50 OUT_RING( CCE_PACKET0( R128_AUX1_SC_LEFT, 3 ) ); 49 OUT_RING(CCE_PACKET0(R128_AUX1_SC_LEFT, 3));
51 OUT_RING( boxes[0].x1 ); 50 OUT_RING(boxes[0].x1);
52 OUT_RING( boxes[0].x2 - 1 ); 51 OUT_RING(boxes[0].x2 - 1);
53 OUT_RING( boxes[0].y1 ); 52 OUT_RING(boxes[0].y1);
54 OUT_RING( boxes[0].y2 - 1 ); 53 OUT_RING(boxes[0].y2 - 1);
55 54
56 aux_sc_cntl |= (R128_AUX1_SC_EN | R128_AUX1_SC_MODE_OR); 55 aux_sc_cntl |= (R128_AUX1_SC_EN | R128_AUX1_SC_MODE_OR);
57 } 56 }
58 if ( count >= 2 ) { 57 if (count >= 2) {
59 OUT_RING( CCE_PACKET0( R128_AUX2_SC_LEFT, 3 ) ); 58 OUT_RING(CCE_PACKET0(R128_AUX2_SC_LEFT, 3));
60 OUT_RING( boxes[1].x1 ); 59 OUT_RING(boxes[1].x1);
61 OUT_RING( boxes[1].x2 - 1 ); 60 OUT_RING(boxes[1].x2 - 1);
62 OUT_RING( boxes[1].y1 ); 61 OUT_RING(boxes[1].y1);
63 OUT_RING( boxes[1].y2 - 1 ); 62 OUT_RING(boxes[1].y2 - 1);
64 63
65 aux_sc_cntl |= (R128_AUX2_SC_EN | R128_AUX2_SC_MODE_OR); 64 aux_sc_cntl |= (R128_AUX2_SC_EN | R128_AUX2_SC_MODE_OR);
66 } 65 }
67 if ( count >= 3 ) { 66 if (count >= 3) {
68 OUT_RING( CCE_PACKET0( R128_AUX3_SC_LEFT, 3 ) ); 67 OUT_RING(CCE_PACKET0(R128_AUX3_SC_LEFT, 3));
69 OUT_RING( boxes[2].x1 ); 68 OUT_RING(boxes[2].x1);
70 OUT_RING( boxes[2].x2 - 1 ); 69 OUT_RING(boxes[2].x2 - 1);
71 OUT_RING( boxes[2].y1 ); 70 OUT_RING(boxes[2].y1);
72 OUT_RING( boxes[2].y2 - 1 ); 71 OUT_RING(boxes[2].y2 - 1);
73 72
74 aux_sc_cntl |= (R128_AUX3_SC_EN | R128_AUX3_SC_MODE_OR); 73 aux_sc_cntl |= (R128_AUX3_SC_EN | R128_AUX3_SC_MODE_OR);
75 } 74 }
76 75
77 OUT_RING( CCE_PACKET0( R128_AUX_SC_CNTL, 0 ) ); 76 OUT_RING(CCE_PACKET0(R128_AUX_SC_CNTL, 0));
78 OUT_RING( aux_sc_cntl ); 77 OUT_RING(aux_sc_cntl);
79 78
80 ADVANCE_RING(); 79 ADVANCE_RING();
81} 80}
82 81
83static __inline__ void r128_emit_core( drm_r128_private_t *dev_priv ) 82static __inline__ void r128_emit_core(drm_r128_private_t * dev_priv)
84{ 83{
85 drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; 84 drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
86 drm_r128_context_regs_t *ctx = &sarea_priv->context_state; 85 drm_r128_context_regs_t *ctx = &sarea_priv->context_state;
87 RING_LOCALS; 86 RING_LOCALS;
88 DRM_DEBUG( " %s\n", __FUNCTION__ ); 87 DRM_DEBUG(" %s\n", __FUNCTION__);
89 88
90 BEGIN_RING( 2 ); 89 BEGIN_RING(2);
91 90
92 OUT_RING( CCE_PACKET0( R128_SCALE_3D_CNTL, 0 ) ); 91 OUT_RING(CCE_PACKET0(R128_SCALE_3D_CNTL, 0));
93 OUT_RING( ctx->scale_3d_cntl ); 92 OUT_RING(ctx->scale_3d_cntl);
94 93
95 ADVANCE_RING(); 94 ADVANCE_RING();
96} 95}
97 96
98static __inline__ void r128_emit_context( drm_r128_private_t *dev_priv ) 97static __inline__ void r128_emit_context(drm_r128_private_t * dev_priv)
99{ 98{
100 drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; 99 drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
101 drm_r128_context_regs_t *ctx = &sarea_priv->context_state; 100 drm_r128_context_regs_t *ctx = &sarea_priv->context_state;
102 RING_LOCALS; 101 RING_LOCALS;
103 DRM_DEBUG( " %s\n", __FUNCTION__ ); 102 DRM_DEBUG(" %s\n", __FUNCTION__);
104 103
105 BEGIN_RING( 13 ); 104 BEGIN_RING(13);
106 105
107 OUT_RING( CCE_PACKET0( R128_DST_PITCH_OFFSET_C, 11 ) ); 106 OUT_RING(CCE_PACKET0(R128_DST_PITCH_OFFSET_C, 11));
108 OUT_RING( ctx->dst_pitch_offset_c ); 107 OUT_RING(ctx->dst_pitch_offset_c);
109 OUT_RING( ctx->dp_gui_master_cntl_c ); 108 OUT_RING(ctx->dp_gui_master_cntl_c);
110 OUT_RING( ctx->sc_top_left_c ); 109 OUT_RING(ctx->sc_top_left_c);
111 OUT_RING( ctx->sc_bottom_right_c ); 110 OUT_RING(ctx->sc_bottom_right_c);
112 OUT_RING( ctx->z_offset_c ); 111 OUT_RING(ctx->z_offset_c);
113 OUT_RING( ctx->z_pitch_c ); 112 OUT_RING(ctx->z_pitch_c);
114 OUT_RING( ctx->z_sten_cntl_c ); 113 OUT_RING(ctx->z_sten_cntl_c);
115 OUT_RING( ctx->tex_cntl_c ); 114 OUT_RING(ctx->tex_cntl_c);
116 OUT_RING( ctx->misc_3d_state_cntl_reg ); 115 OUT_RING(ctx->misc_3d_state_cntl_reg);
117 OUT_RING( ctx->texture_clr_cmp_clr_c ); 116 OUT_RING(ctx->texture_clr_cmp_clr_c);
118 OUT_RING( ctx->texture_clr_cmp_msk_c ); 117 OUT_RING(ctx->texture_clr_cmp_msk_c);
119 OUT_RING( ctx->fog_color_c ); 118 OUT_RING(ctx->fog_color_c);
120 119
121 ADVANCE_RING(); 120 ADVANCE_RING();
122} 121}
123 122
124static __inline__ void r128_emit_setup( drm_r128_private_t *dev_priv ) 123static __inline__ void r128_emit_setup(drm_r128_private_t * dev_priv)
125{ 124{
126 drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; 125 drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
127 drm_r128_context_regs_t *ctx = &sarea_priv->context_state; 126 drm_r128_context_regs_t *ctx = &sarea_priv->context_state;
128 RING_LOCALS; 127 RING_LOCALS;
129 DRM_DEBUG( " %s\n", __FUNCTION__ ); 128 DRM_DEBUG(" %s\n", __FUNCTION__);
130 129
131 BEGIN_RING( 3 ); 130 BEGIN_RING(3);
132 131
133 OUT_RING( CCE_PACKET1( R128_SETUP_CNTL, R128_PM4_VC_FPU_SETUP ) ); 132 OUT_RING(CCE_PACKET1(R128_SETUP_CNTL, R128_PM4_VC_FPU_SETUP));
134 OUT_RING( ctx->setup_cntl ); 133 OUT_RING(ctx->setup_cntl);
135 OUT_RING( ctx->pm4_vc_fpu_setup ); 134 OUT_RING(ctx->pm4_vc_fpu_setup);
136 135
137 ADVANCE_RING(); 136 ADVANCE_RING();
138} 137}
139 138
140static __inline__ void r128_emit_masks( drm_r128_private_t *dev_priv ) 139static __inline__ void r128_emit_masks(drm_r128_private_t * dev_priv)
141{ 140{
142 drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; 141 drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
143 drm_r128_context_regs_t *ctx = &sarea_priv->context_state; 142 drm_r128_context_regs_t *ctx = &sarea_priv->context_state;
144 RING_LOCALS; 143 RING_LOCALS;
145 DRM_DEBUG( " %s\n", __FUNCTION__ ); 144 DRM_DEBUG(" %s\n", __FUNCTION__);
146 145
147 BEGIN_RING( 5 ); 146 BEGIN_RING(5);
148 147
149 OUT_RING( CCE_PACKET0( R128_DP_WRITE_MASK, 0 ) ); 148 OUT_RING(CCE_PACKET0(R128_DP_WRITE_MASK, 0));
150 OUT_RING( ctx->dp_write_mask ); 149 OUT_RING(ctx->dp_write_mask);
151 150
152 OUT_RING( CCE_PACKET0( R128_STEN_REF_MASK_C, 1 ) ); 151 OUT_RING(CCE_PACKET0(R128_STEN_REF_MASK_C, 1));
153 OUT_RING( ctx->sten_ref_mask_c ); 152 OUT_RING(ctx->sten_ref_mask_c);
154 OUT_RING( ctx->plane_3d_mask_c ); 153 OUT_RING(ctx->plane_3d_mask_c);
155 154
156 ADVANCE_RING(); 155 ADVANCE_RING();
157} 156}
158 157
159static __inline__ void r128_emit_window( drm_r128_private_t *dev_priv ) 158static __inline__ void r128_emit_window(drm_r128_private_t * dev_priv)
160{ 159{
161 drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; 160 drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
162 drm_r128_context_regs_t *ctx = &sarea_priv->context_state; 161 drm_r128_context_regs_t *ctx = &sarea_priv->context_state;
163 RING_LOCALS; 162 RING_LOCALS;
164 DRM_DEBUG( " %s\n", __FUNCTION__ ); 163 DRM_DEBUG(" %s\n", __FUNCTION__);
165 164
166 BEGIN_RING( 2 ); 165 BEGIN_RING(2);
167 166
168 OUT_RING( CCE_PACKET0( R128_WINDOW_XY_OFFSET, 0 ) ); 167 OUT_RING(CCE_PACKET0(R128_WINDOW_XY_OFFSET, 0));
169 OUT_RING( ctx->window_xy_offset ); 168 OUT_RING(ctx->window_xy_offset);
170 169
171 ADVANCE_RING(); 170 ADVANCE_RING();
172} 171}
173 172
174static __inline__ void r128_emit_tex0( drm_r128_private_t *dev_priv ) 173static __inline__ void r128_emit_tex0(drm_r128_private_t * dev_priv)
175{ 174{
176 drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; 175 drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
177 drm_r128_context_regs_t *ctx = &sarea_priv->context_state; 176 drm_r128_context_regs_t *ctx = &sarea_priv->context_state;
178 drm_r128_texture_regs_t *tex = &sarea_priv->tex_state[0]; 177 drm_r128_texture_regs_t *tex = &sarea_priv->tex_state[0];
179 int i; 178 int i;
180 RING_LOCALS; 179 RING_LOCALS;
181 DRM_DEBUG( " %s\n", __FUNCTION__ ); 180 DRM_DEBUG(" %s\n", __FUNCTION__);
182 181
183 BEGIN_RING( 7 + R128_MAX_TEXTURE_LEVELS ); 182 BEGIN_RING(7 + R128_MAX_TEXTURE_LEVELS);
184 183
185 OUT_RING( CCE_PACKET0( R128_PRIM_TEX_CNTL_C, 184 OUT_RING(CCE_PACKET0(R128_PRIM_TEX_CNTL_C,
186 2 + R128_MAX_TEXTURE_LEVELS ) ); 185 2 + R128_MAX_TEXTURE_LEVELS));
187 OUT_RING( tex->tex_cntl ); 186 OUT_RING(tex->tex_cntl);
188 OUT_RING( tex->tex_combine_cntl ); 187 OUT_RING(tex->tex_combine_cntl);
189 OUT_RING( ctx->tex_size_pitch_c ); 188 OUT_RING(ctx->tex_size_pitch_c);
190 for ( i = 0 ; i < R128_MAX_TEXTURE_LEVELS ; i++ ) { 189 for (i = 0; i < R128_MAX_TEXTURE_LEVELS; i++) {
191 OUT_RING( tex->tex_offset[i] ); 190 OUT_RING(tex->tex_offset[i]);
192 } 191 }
193 192
194 OUT_RING( CCE_PACKET0( R128_CONSTANT_COLOR_C, 1 ) ); 193 OUT_RING(CCE_PACKET0(R128_CONSTANT_COLOR_C, 1));
195 OUT_RING( ctx->constant_color_c ); 194 OUT_RING(ctx->constant_color_c);
196 OUT_RING( tex->tex_border_color ); 195 OUT_RING(tex->tex_border_color);
197 196
198 ADVANCE_RING(); 197 ADVANCE_RING();
199} 198}
200 199
201static __inline__ void r128_emit_tex1( drm_r128_private_t *dev_priv ) 200static __inline__ void r128_emit_tex1(drm_r128_private_t * dev_priv)
202{ 201{
203 drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; 202 drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
204 drm_r128_texture_regs_t *tex = &sarea_priv->tex_state[1]; 203 drm_r128_texture_regs_t *tex = &sarea_priv->tex_state[1];
205 int i; 204 int i;
206 RING_LOCALS; 205 RING_LOCALS;
207 DRM_DEBUG( " %s\n", __FUNCTION__ ); 206 DRM_DEBUG(" %s\n", __FUNCTION__);
208 207
209 BEGIN_RING( 5 + R128_MAX_TEXTURE_LEVELS ); 208 BEGIN_RING(5 + R128_MAX_TEXTURE_LEVELS);
210 209
211 OUT_RING( CCE_PACKET0( R128_SEC_TEX_CNTL_C, 210 OUT_RING(CCE_PACKET0(R128_SEC_TEX_CNTL_C, 1 + R128_MAX_TEXTURE_LEVELS));
212 1 + R128_MAX_TEXTURE_LEVELS ) ); 211 OUT_RING(tex->tex_cntl);
213 OUT_RING( tex->tex_cntl ); 212 OUT_RING(tex->tex_combine_cntl);
214 OUT_RING( tex->tex_combine_cntl ); 213 for (i = 0; i < R128_MAX_TEXTURE_LEVELS; i++) {
215 for ( i = 0 ; i < R128_MAX_TEXTURE_LEVELS ; i++ ) { 214 OUT_RING(tex->tex_offset[i]);
216 OUT_RING( tex->tex_offset[i] );
217 } 215 }
218 216
219 OUT_RING( CCE_PACKET0( R128_SEC_TEXTURE_BORDER_COLOR_C, 0 ) ); 217 OUT_RING(CCE_PACKET0(R128_SEC_TEXTURE_BORDER_COLOR_C, 0));
220 OUT_RING( tex->tex_border_color ); 218 OUT_RING(tex->tex_border_color);
221 219
222 ADVANCE_RING(); 220 ADVANCE_RING();
223} 221}
224 222
225static __inline__ void r128_emit_state( drm_r128_private_t *dev_priv ) 223static __inline__ void r128_emit_state(drm_r128_private_t * dev_priv)
226{ 224{
227 drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; 225 drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
228 unsigned int dirty = sarea_priv->dirty; 226 unsigned int dirty = sarea_priv->dirty;
229 227
230 DRM_DEBUG( "%s: dirty=0x%08x\n", __FUNCTION__, dirty ); 228 DRM_DEBUG("%s: dirty=0x%08x\n", __FUNCTION__, dirty);
231 229
232 if ( dirty & R128_UPLOAD_CORE ) { 230 if (dirty & R128_UPLOAD_CORE) {
233 r128_emit_core( dev_priv ); 231 r128_emit_core(dev_priv);
234 sarea_priv->dirty &= ~R128_UPLOAD_CORE; 232 sarea_priv->dirty &= ~R128_UPLOAD_CORE;
235 } 233 }
236 234
237 if ( dirty & R128_UPLOAD_CONTEXT ) { 235 if (dirty & R128_UPLOAD_CONTEXT) {
238 r128_emit_context( dev_priv ); 236 r128_emit_context(dev_priv);
239 sarea_priv->dirty &= ~R128_UPLOAD_CONTEXT; 237 sarea_priv->dirty &= ~R128_UPLOAD_CONTEXT;
240 } 238 }
241 239
242 if ( dirty & R128_UPLOAD_SETUP ) { 240 if (dirty & R128_UPLOAD_SETUP) {
243 r128_emit_setup( dev_priv ); 241 r128_emit_setup(dev_priv);
244 sarea_priv->dirty &= ~R128_UPLOAD_SETUP; 242 sarea_priv->dirty &= ~R128_UPLOAD_SETUP;
245 } 243 }
246 244
247 if ( dirty & R128_UPLOAD_MASKS ) { 245 if (dirty & R128_UPLOAD_MASKS) {
248 r128_emit_masks( dev_priv ); 246 r128_emit_masks(dev_priv);
249 sarea_priv->dirty &= ~R128_UPLOAD_MASKS; 247 sarea_priv->dirty &= ~R128_UPLOAD_MASKS;
250 } 248 }
251 249
252 if ( dirty & R128_UPLOAD_WINDOW ) { 250 if (dirty & R128_UPLOAD_WINDOW) {
253 r128_emit_window( dev_priv ); 251 r128_emit_window(dev_priv);
254 sarea_priv->dirty &= ~R128_UPLOAD_WINDOW; 252 sarea_priv->dirty &= ~R128_UPLOAD_WINDOW;
255 } 253 }
256 254
257 if ( dirty & R128_UPLOAD_TEX0 ) { 255 if (dirty & R128_UPLOAD_TEX0) {
258 r128_emit_tex0( dev_priv ); 256 r128_emit_tex0(dev_priv);
259 sarea_priv->dirty &= ~R128_UPLOAD_TEX0; 257 sarea_priv->dirty &= ~R128_UPLOAD_TEX0;
260 } 258 }
261 259
262 if ( dirty & R128_UPLOAD_TEX1 ) { 260 if (dirty & R128_UPLOAD_TEX1) {
263 r128_emit_tex1( dev_priv ); 261 r128_emit_tex1(dev_priv);
264 sarea_priv->dirty &= ~R128_UPLOAD_TEX1; 262 sarea_priv->dirty &= ~R128_UPLOAD_TEX1;
265 } 263 }
266 264
@@ -270,26 +268,23 @@ static __inline__ void r128_emit_state( drm_r128_private_t *dev_priv )
270 sarea_priv->dirty &= ~R128_REQUIRE_QUIESCENCE; 268 sarea_priv->dirty &= ~R128_REQUIRE_QUIESCENCE;
271} 269}
272 270
273
274#if R128_PERFORMANCE_BOXES 271#if R128_PERFORMANCE_BOXES
275/* ================================================================ 272/* ================================================================
276 * Performance monitoring functions 273 * Performance monitoring functions
277 */ 274 */
278 275
279static void r128_clear_box( drm_r128_private_t *dev_priv, 276static void r128_clear_box(drm_r128_private_t * dev_priv,
280 int x, int y, int w, int h, 277 int x, int y, int w, int h, int r, int g, int b)
281 int r, int g, int b )
282{ 278{
283 u32 pitch, offset; 279 u32 pitch, offset;
284 u32 fb_bpp, color; 280 u32 fb_bpp, color;
285 RING_LOCALS; 281 RING_LOCALS;
286 282
287 switch ( dev_priv->fb_bpp ) { 283 switch (dev_priv->fb_bpp) {
288 case 16: 284 case 16:
289 fb_bpp = R128_GMC_DST_16BPP; 285 fb_bpp = R128_GMC_DST_16BPP;
290 color = (((r & 0xf8) << 8) | 286 color = (((r & 0xf8) << 8) |
291 ((g & 0xfc) << 3) | 287 ((g & 0xfc) << 3) | ((b & 0xf8) >> 3));
292 ((b & 0xf8) >> 3));
293 break; 288 break;
294 case 24: 289 case 24:
295 fb_bpp = R128_GMC_DST_24BPP; 290 fb_bpp = R128_GMC_DST_24BPP;
@@ -297,7 +292,7 @@ static void r128_clear_box( drm_r128_private_t *dev_priv,
297 break; 292 break;
298 case 32: 293 case 32:
299 fb_bpp = R128_GMC_DST_32BPP; 294 fb_bpp = R128_GMC_DST_32BPP;
300 color = (((0xff) << 24) | (r << 16) | (g << 8) | b); 295 color = (((0xff) << 24) | (r << 16) | (g << 8) | b);
301 break; 296 break;
302 default: 297 default:
303 return; 298 return;
@@ -306,60 +301,58 @@ static void r128_clear_box( drm_r128_private_t *dev_priv,
306 offset = dev_priv->back_offset; 301 offset = dev_priv->back_offset;
307 pitch = dev_priv->back_pitch >> 3; 302 pitch = dev_priv->back_pitch >> 3;
308 303
309 BEGIN_RING( 6 ); 304 BEGIN_RING(6);
310 305
311 OUT_RING( CCE_PACKET3( R128_CNTL_PAINT_MULTI, 4 ) ); 306 OUT_RING(CCE_PACKET3(R128_CNTL_PAINT_MULTI, 4));
312 OUT_RING( R128_GMC_DST_PITCH_OFFSET_CNTL | 307 OUT_RING(R128_GMC_DST_PITCH_OFFSET_CNTL |
313 R128_GMC_BRUSH_SOLID_COLOR | 308 R128_GMC_BRUSH_SOLID_COLOR |
314 fb_bpp | 309 fb_bpp |
315 R128_GMC_SRC_DATATYPE_COLOR | 310 R128_GMC_SRC_DATATYPE_COLOR |
316 R128_ROP3_P | 311 R128_ROP3_P |
317 R128_GMC_CLR_CMP_CNTL_DIS | 312 R128_GMC_CLR_CMP_CNTL_DIS | R128_GMC_AUX_CLIP_DIS);
318 R128_GMC_AUX_CLIP_DIS );
319 313
320 OUT_RING( (pitch << 21) | (offset >> 5) ); 314 OUT_RING((pitch << 21) | (offset >> 5));
321 OUT_RING( color ); 315 OUT_RING(color);
322 316
323 OUT_RING( (x << 16) | y ); 317 OUT_RING((x << 16) | y);
324 OUT_RING( (w << 16) | h ); 318 OUT_RING((w << 16) | h);
325 319
326 ADVANCE_RING(); 320 ADVANCE_RING();
327} 321}
328 322
329static void r128_cce_performance_boxes( drm_r128_private_t *dev_priv ) 323static void r128_cce_performance_boxes(drm_r128_private_t * dev_priv)
330{ 324{
331 if ( atomic_read( &dev_priv->idle_count ) == 0 ) { 325 if (atomic_read(&dev_priv->idle_count) == 0) {
332 r128_clear_box( dev_priv, 64, 4, 8, 8, 0, 255, 0 ); 326 r128_clear_box(dev_priv, 64, 4, 8, 8, 0, 255, 0);
333 } else { 327 } else {
334 atomic_set( &dev_priv->idle_count, 0 ); 328 atomic_set(&dev_priv->idle_count, 0);
335 } 329 }
336} 330}
337 331
338#endif 332#endif
339 333
340
341/* ================================================================ 334/* ================================================================
342 * CCE command dispatch functions 335 * CCE command dispatch functions
343 */ 336 */
344 337
345static void r128_print_dirty( const char *msg, unsigned int flags ) 338static void r128_print_dirty(const char *msg, unsigned int flags)
346{ 339{
347 DRM_INFO( "%s: (0x%x) %s%s%s%s%s%s%s%s%s\n", 340 DRM_INFO("%s: (0x%x) %s%s%s%s%s%s%s%s%s\n",
348 msg, 341 msg,
349 flags, 342 flags,
350 (flags & R128_UPLOAD_CORE) ? "core, " : "", 343 (flags & R128_UPLOAD_CORE) ? "core, " : "",
351 (flags & R128_UPLOAD_CONTEXT) ? "context, " : "", 344 (flags & R128_UPLOAD_CONTEXT) ? "context, " : "",
352 (flags & R128_UPLOAD_SETUP) ? "setup, " : "", 345 (flags & R128_UPLOAD_SETUP) ? "setup, " : "",
353 (flags & R128_UPLOAD_TEX0) ? "tex0, " : "", 346 (flags & R128_UPLOAD_TEX0) ? "tex0, " : "",
354 (flags & R128_UPLOAD_TEX1) ? "tex1, " : "", 347 (flags & R128_UPLOAD_TEX1) ? "tex1, " : "",
355 (flags & R128_UPLOAD_MASKS) ? "masks, " : "", 348 (flags & R128_UPLOAD_MASKS) ? "masks, " : "",
356 (flags & R128_UPLOAD_WINDOW) ? "window, " : "", 349 (flags & R128_UPLOAD_WINDOW) ? "window, " : "",
357 (flags & R128_UPLOAD_CLIPRECTS) ? "cliprects, " : "", 350 (flags & R128_UPLOAD_CLIPRECTS) ? "cliprects, " : "",
358 (flags & R128_REQUIRE_QUIESCENCE) ? "quiescence, " : "" ); 351 (flags & R128_REQUIRE_QUIESCENCE) ? "quiescence, " : "");
359} 352}
360 353
361static void r128_cce_dispatch_clear( drm_device_t *dev, 354static void r128_cce_dispatch_clear(drm_device_t * dev,
362 drm_r128_clear_t *clear ) 355 drm_r128_clear_t * clear)
363{ 356{
364 drm_r128_private_t *dev_priv = dev->dev_private; 357 drm_r128_private_t *dev_priv = dev->dev_private;
365 drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; 358 drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
@@ -368,102 +361,103 @@ static void r128_cce_dispatch_clear( drm_device_t *dev,
368 unsigned int flags = clear->flags; 361 unsigned int flags = clear->flags;
369 int i; 362 int i;
370 RING_LOCALS; 363 RING_LOCALS;
371 DRM_DEBUG( "%s\n", __FUNCTION__ ); 364 DRM_DEBUG("%s\n", __FUNCTION__);
372 365
373 if ( dev_priv->page_flipping && dev_priv->current_page == 1 ) { 366 if (dev_priv->page_flipping && dev_priv->current_page == 1) {
374 unsigned int tmp = flags; 367 unsigned int tmp = flags;
375 368
376 flags &= ~(R128_FRONT | R128_BACK); 369 flags &= ~(R128_FRONT | R128_BACK);
377 if ( tmp & R128_FRONT ) flags |= R128_BACK; 370 if (tmp & R128_FRONT)
378 if ( tmp & R128_BACK ) flags |= R128_FRONT; 371 flags |= R128_BACK;
372 if (tmp & R128_BACK)
373 flags |= R128_FRONT;
379 } 374 }
380 375
381 for ( i = 0 ; i < nbox ; i++ ) { 376 for (i = 0; i < nbox; i++) {
382 int x = pbox[i].x1; 377 int x = pbox[i].x1;
383 int y = pbox[i].y1; 378 int y = pbox[i].y1;
384 int w = pbox[i].x2 - x; 379 int w = pbox[i].x2 - x;
385 int h = pbox[i].y2 - y; 380 int h = pbox[i].y2 - y;
386 381
387 DRM_DEBUG( "dispatch clear %d,%d-%d,%d flags 0x%x\n", 382 DRM_DEBUG("dispatch clear %d,%d-%d,%d flags 0x%x\n",
388 pbox[i].x1, pbox[i].y1, pbox[i].x2, 383 pbox[i].x1, pbox[i].y1, pbox[i].x2,
389 pbox[i].y2, flags ); 384 pbox[i].y2, flags);
390 385
391 if ( flags & (R128_FRONT | R128_BACK) ) { 386 if (flags & (R128_FRONT | R128_BACK)) {
392 BEGIN_RING( 2 ); 387 BEGIN_RING(2);
393 388
394 OUT_RING( CCE_PACKET0( R128_DP_WRITE_MASK, 0 ) ); 389 OUT_RING(CCE_PACKET0(R128_DP_WRITE_MASK, 0));
395 OUT_RING( clear->color_mask ); 390 OUT_RING(clear->color_mask);
396 391
397 ADVANCE_RING(); 392 ADVANCE_RING();
398 } 393 }
399 394
400 if ( flags & R128_FRONT ) { 395 if (flags & R128_FRONT) {
401 BEGIN_RING( 6 ); 396 BEGIN_RING(6);
402 397
403 OUT_RING( CCE_PACKET3( R128_CNTL_PAINT_MULTI, 4 ) ); 398 OUT_RING(CCE_PACKET3(R128_CNTL_PAINT_MULTI, 4));
404 OUT_RING( R128_GMC_DST_PITCH_OFFSET_CNTL | 399 OUT_RING(R128_GMC_DST_PITCH_OFFSET_CNTL |
405 R128_GMC_BRUSH_SOLID_COLOR | 400 R128_GMC_BRUSH_SOLID_COLOR |
406 (dev_priv->color_fmt << 8) | 401 (dev_priv->color_fmt << 8) |
407 R128_GMC_SRC_DATATYPE_COLOR | 402 R128_GMC_SRC_DATATYPE_COLOR |
408 R128_ROP3_P | 403 R128_ROP3_P |
409 R128_GMC_CLR_CMP_CNTL_DIS | 404 R128_GMC_CLR_CMP_CNTL_DIS |
410 R128_GMC_AUX_CLIP_DIS ); 405 R128_GMC_AUX_CLIP_DIS);
411 406
412 OUT_RING( dev_priv->front_pitch_offset_c ); 407 OUT_RING(dev_priv->front_pitch_offset_c);
413 OUT_RING( clear->clear_color ); 408 OUT_RING(clear->clear_color);
414 409
415 OUT_RING( (x << 16) | y ); 410 OUT_RING((x << 16) | y);
416 OUT_RING( (w << 16) | h ); 411 OUT_RING((w << 16) | h);
417 412
418 ADVANCE_RING(); 413 ADVANCE_RING();
419 } 414 }
420 415
421 if ( flags & R128_BACK ) { 416 if (flags & R128_BACK) {
422 BEGIN_RING( 6 ); 417 BEGIN_RING(6);
423 418
424 OUT_RING( CCE_PACKET3( R128_CNTL_PAINT_MULTI, 4 ) ); 419 OUT_RING(CCE_PACKET3(R128_CNTL_PAINT_MULTI, 4));
425 OUT_RING( R128_GMC_DST_PITCH_OFFSET_CNTL | 420 OUT_RING(R128_GMC_DST_PITCH_OFFSET_CNTL |
426 R128_GMC_BRUSH_SOLID_COLOR | 421 R128_GMC_BRUSH_SOLID_COLOR |
427 (dev_priv->color_fmt << 8) | 422 (dev_priv->color_fmt << 8) |
428 R128_GMC_SRC_DATATYPE_COLOR | 423 R128_GMC_SRC_DATATYPE_COLOR |
429 R128_ROP3_P | 424 R128_ROP3_P |
430 R128_GMC_CLR_CMP_CNTL_DIS | 425 R128_GMC_CLR_CMP_CNTL_DIS |
431 R128_GMC_AUX_CLIP_DIS ); 426 R128_GMC_AUX_CLIP_DIS);
432 427
433 OUT_RING( dev_priv->back_pitch_offset_c ); 428 OUT_RING(dev_priv->back_pitch_offset_c);
434 OUT_RING( clear->clear_color ); 429 OUT_RING(clear->clear_color);
435 430
436 OUT_RING( (x << 16) | y ); 431 OUT_RING((x << 16) | y);
437 OUT_RING( (w << 16) | h ); 432 OUT_RING((w << 16) | h);
438 433
439 ADVANCE_RING(); 434 ADVANCE_RING();
440 } 435 }
441 436
442 if ( flags & R128_DEPTH ) { 437 if (flags & R128_DEPTH) {
443 BEGIN_RING( 6 ); 438 BEGIN_RING(6);
444 439
445 OUT_RING( CCE_PACKET3( R128_CNTL_PAINT_MULTI, 4 ) ); 440 OUT_RING(CCE_PACKET3(R128_CNTL_PAINT_MULTI, 4));
446 OUT_RING( R128_GMC_DST_PITCH_OFFSET_CNTL | 441 OUT_RING(R128_GMC_DST_PITCH_OFFSET_CNTL |
447 R128_GMC_BRUSH_SOLID_COLOR | 442 R128_GMC_BRUSH_SOLID_COLOR |
448 (dev_priv->depth_fmt << 8) | 443 (dev_priv->depth_fmt << 8) |
449 R128_GMC_SRC_DATATYPE_COLOR | 444 R128_GMC_SRC_DATATYPE_COLOR |
450 R128_ROP3_P | 445 R128_ROP3_P |
451 R128_GMC_CLR_CMP_CNTL_DIS | 446 R128_GMC_CLR_CMP_CNTL_DIS |
452 R128_GMC_AUX_CLIP_DIS | 447 R128_GMC_AUX_CLIP_DIS | R128_GMC_WR_MSK_DIS);
453 R128_GMC_WR_MSK_DIS );
454 448
455 OUT_RING( dev_priv->depth_pitch_offset_c ); 449 OUT_RING(dev_priv->depth_pitch_offset_c);
456 OUT_RING( clear->clear_depth ); 450 OUT_RING(clear->clear_depth);
457 451
458 OUT_RING( (x << 16) | y ); 452 OUT_RING((x << 16) | y);
459 OUT_RING( (w << 16) | h ); 453 OUT_RING((w << 16) | h);
460 454
461 ADVANCE_RING(); 455 ADVANCE_RING();
462 } 456 }
463 } 457 }
464} 458}
465 459
466static void r128_cce_dispatch_swap( drm_device_t *dev ) 460static void r128_cce_dispatch_swap(drm_device_t * dev)
467{ 461{
468 drm_r128_private_t *dev_priv = dev->dev_private; 462 drm_r128_private_t *dev_priv = dev->dev_private;
469 drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; 463 drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
@@ -471,48 +465,46 @@ static void r128_cce_dispatch_swap( drm_device_t *dev )
471 drm_clip_rect_t *pbox = sarea_priv->boxes; 465 drm_clip_rect_t *pbox = sarea_priv->boxes;
472 int i; 466 int i;
473 RING_LOCALS; 467 RING_LOCALS;
474 DRM_DEBUG( "%s\n", __FUNCTION__ ); 468 DRM_DEBUG("%s\n", __FUNCTION__);
475 469
476#if R128_PERFORMANCE_BOXES 470#if R128_PERFORMANCE_BOXES
477 /* Do some trivial performance monitoring... 471 /* Do some trivial performance monitoring...
478 */ 472 */
479 r128_cce_performance_boxes( dev_priv ); 473 r128_cce_performance_boxes(dev_priv);
480#endif 474#endif
481 475
482 for ( i = 0 ; i < nbox ; i++ ) { 476 for (i = 0; i < nbox; i++) {
483 int x = pbox[i].x1; 477 int x = pbox[i].x1;
484 int y = pbox[i].y1; 478 int y = pbox[i].y1;
485 int w = pbox[i].x2 - x; 479 int w = pbox[i].x2 - x;
486 int h = pbox[i].y2 - y; 480 int h = pbox[i].y2 - y;
487 481
488 BEGIN_RING( 7 ); 482 BEGIN_RING(7);
489 483
490 OUT_RING( CCE_PACKET3( R128_CNTL_BITBLT_MULTI, 5 ) ); 484 OUT_RING(CCE_PACKET3(R128_CNTL_BITBLT_MULTI, 5));
491 OUT_RING( R128_GMC_SRC_PITCH_OFFSET_CNTL | 485 OUT_RING(R128_GMC_SRC_PITCH_OFFSET_CNTL |
492 R128_GMC_DST_PITCH_OFFSET_CNTL | 486 R128_GMC_DST_PITCH_OFFSET_CNTL |
493 R128_GMC_BRUSH_NONE | 487 R128_GMC_BRUSH_NONE |
494 (dev_priv->color_fmt << 8) | 488 (dev_priv->color_fmt << 8) |
495 R128_GMC_SRC_DATATYPE_COLOR | 489 R128_GMC_SRC_DATATYPE_COLOR |
496 R128_ROP3_S | 490 R128_ROP3_S |
497 R128_DP_SRC_SOURCE_MEMORY | 491 R128_DP_SRC_SOURCE_MEMORY |
498 R128_GMC_CLR_CMP_CNTL_DIS | 492 R128_GMC_CLR_CMP_CNTL_DIS |
499 R128_GMC_AUX_CLIP_DIS | 493 R128_GMC_AUX_CLIP_DIS | R128_GMC_WR_MSK_DIS);
500 R128_GMC_WR_MSK_DIS );
501 494
502 /* Make this work even if front & back are flipped: 495 /* Make this work even if front & back are flipped:
503 */ 496 */
504 if (dev_priv->current_page == 0) { 497 if (dev_priv->current_page == 0) {
505 OUT_RING( dev_priv->back_pitch_offset_c ); 498 OUT_RING(dev_priv->back_pitch_offset_c);
506 OUT_RING( dev_priv->front_pitch_offset_c ); 499 OUT_RING(dev_priv->front_pitch_offset_c);
507 } 500 } else {
508 else { 501 OUT_RING(dev_priv->front_pitch_offset_c);
509 OUT_RING( dev_priv->front_pitch_offset_c ); 502 OUT_RING(dev_priv->back_pitch_offset_c);
510 OUT_RING( dev_priv->back_pitch_offset_c );
511 } 503 }
512 504
513 OUT_RING( (x << 16) | y ); 505 OUT_RING((x << 16) | y);
514 OUT_RING( (x << 16) | y ); 506 OUT_RING((x << 16) | y);
515 OUT_RING( (w << 16) | h ); 507 OUT_RING((w << 16) | h);
516 508
517 ADVANCE_RING(); 509 ADVANCE_RING();
518 } 510 }
@@ -523,38 +515,37 @@ static void r128_cce_dispatch_swap( drm_device_t *dev )
523 */ 515 */
524 dev_priv->sarea_priv->last_frame++; 516 dev_priv->sarea_priv->last_frame++;
525 517
526 BEGIN_RING( 2 ); 518 BEGIN_RING(2);
527 519
528 OUT_RING( CCE_PACKET0( R128_LAST_FRAME_REG, 0 ) ); 520 OUT_RING(CCE_PACKET0(R128_LAST_FRAME_REG, 0));
529 OUT_RING( dev_priv->sarea_priv->last_frame ); 521 OUT_RING(dev_priv->sarea_priv->last_frame);
530 522
531 ADVANCE_RING(); 523 ADVANCE_RING();
532} 524}
533 525
534static void r128_cce_dispatch_flip( drm_device_t *dev ) 526static void r128_cce_dispatch_flip(drm_device_t * dev)
535{ 527{
536 drm_r128_private_t *dev_priv = dev->dev_private; 528 drm_r128_private_t *dev_priv = dev->dev_private;
537 RING_LOCALS; 529 RING_LOCALS;
538 DRM_DEBUG("%s: page=%d pfCurrentPage=%d\n", 530 DRM_DEBUG("%s: page=%d pfCurrentPage=%d\n",
539 __FUNCTION__, 531 __FUNCTION__,
540 dev_priv->current_page, 532 dev_priv->current_page, dev_priv->sarea_priv->pfCurrentPage);
541 dev_priv->sarea_priv->pfCurrentPage);
542 533
543#if R128_PERFORMANCE_BOXES 534#if R128_PERFORMANCE_BOXES
544 /* Do some trivial performance monitoring... 535 /* Do some trivial performance monitoring...
545 */ 536 */
546 r128_cce_performance_boxes( dev_priv ); 537 r128_cce_performance_boxes(dev_priv);
547#endif 538#endif
548 539
549 BEGIN_RING( 4 ); 540 BEGIN_RING(4);
550 541
551 R128_WAIT_UNTIL_PAGE_FLIPPED(); 542 R128_WAIT_UNTIL_PAGE_FLIPPED();
552 OUT_RING( CCE_PACKET0( R128_CRTC_OFFSET, 0 ) ); 543 OUT_RING(CCE_PACKET0(R128_CRTC_OFFSET, 0));
553 544
554 if ( dev_priv->current_page == 0 ) { 545 if (dev_priv->current_page == 0) {
555 OUT_RING( dev_priv->back_offset ); 546 OUT_RING(dev_priv->back_offset);
556 } else { 547 } else {
557 OUT_RING( dev_priv->front_offset ); 548 OUT_RING(dev_priv->front_offset);
558 } 549 }
559 550
560 ADVANCE_RING(); 551 ADVANCE_RING();
@@ -565,18 +556,17 @@ static void r128_cce_dispatch_flip( drm_device_t *dev )
565 */ 556 */
566 dev_priv->sarea_priv->last_frame++; 557 dev_priv->sarea_priv->last_frame++;
567 dev_priv->sarea_priv->pfCurrentPage = dev_priv->current_page = 558 dev_priv->sarea_priv->pfCurrentPage = dev_priv->current_page =
568 1 - dev_priv->current_page; 559 1 - dev_priv->current_page;
569 560
570 BEGIN_RING( 2 ); 561 BEGIN_RING(2);
571 562
572 OUT_RING( CCE_PACKET0( R128_LAST_FRAME_REG, 0 ) ); 563 OUT_RING(CCE_PACKET0(R128_LAST_FRAME_REG, 0));
573 OUT_RING( dev_priv->sarea_priv->last_frame ); 564 OUT_RING(dev_priv->sarea_priv->last_frame);
574 565
575 ADVANCE_RING(); 566 ADVANCE_RING();
576} 567}
577 568
578static void r128_cce_dispatch_vertex( drm_device_t *dev, 569static void r128_cce_dispatch_vertex(drm_device_t * dev, drm_buf_t * buf)
579 drm_buf_t *buf )
580{ 570{
581 drm_r128_private_t *dev_priv = dev->dev_private; 571 drm_r128_private_t *dev_priv = dev->dev_private;
582 drm_r128_buf_priv_t *buf_priv = buf->dev_private; 572 drm_r128_buf_priv_t *buf_priv = buf->dev_private;
@@ -587,50 +577,50 @@ static void r128_cce_dispatch_vertex( drm_device_t *dev,
587 int prim = buf_priv->prim; 577 int prim = buf_priv->prim;
588 int i = 0; 578 int i = 0;
589 RING_LOCALS; 579 RING_LOCALS;
590 DRM_DEBUG( "buf=%d nbox=%d\n", buf->idx, sarea_priv->nbox ); 580 DRM_DEBUG("buf=%d nbox=%d\n", buf->idx, sarea_priv->nbox);
591 581
592 if ( 0 ) 582 if (0)
593 r128_print_dirty( "dispatch_vertex", sarea_priv->dirty ); 583 r128_print_dirty("dispatch_vertex", sarea_priv->dirty);
594 584
595 if ( buf->used ) { 585 if (buf->used) {
596 buf_priv->dispatched = 1; 586 buf_priv->dispatched = 1;
597 587
598 if ( sarea_priv->dirty & ~R128_UPLOAD_CLIPRECTS ) { 588 if (sarea_priv->dirty & ~R128_UPLOAD_CLIPRECTS) {
599 r128_emit_state( dev_priv ); 589 r128_emit_state(dev_priv);
600 } 590 }
601 591
602 do { 592 do {
603 /* Emit the next set of up to three cliprects */ 593 /* Emit the next set of up to three cliprects */
604 if ( i < sarea_priv->nbox ) { 594 if (i < sarea_priv->nbox) {
605 r128_emit_clip_rects( dev_priv, 595 r128_emit_clip_rects(dev_priv,
606 &sarea_priv->boxes[i], 596 &sarea_priv->boxes[i],
607 sarea_priv->nbox - i ); 597 sarea_priv->nbox - i);
608 } 598 }
609 599
610 /* Emit the vertex buffer rendering commands */ 600 /* Emit the vertex buffer rendering commands */
611 BEGIN_RING( 5 ); 601 BEGIN_RING(5);
612 602
613 OUT_RING( CCE_PACKET3( R128_3D_RNDR_GEN_INDX_PRIM, 3 ) ); 603 OUT_RING(CCE_PACKET3(R128_3D_RNDR_GEN_INDX_PRIM, 3));
614 OUT_RING( offset ); 604 OUT_RING(offset);
615 OUT_RING( size ); 605 OUT_RING(size);
616 OUT_RING( format ); 606 OUT_RING(format);
617 OUT_RING( prim | R128_CCE_VC_CNTL_PRIM_WALK_LIST | 607 OUT_RING(prim | R128_CCE_VC_CNTL_PRIM_WALK_LIST |
618 (size << R128_CCE_VC_CNTL_NUM_SHIFT) ); 608 (size << R128_CCE_VC_CNTL_NUM_SHIFT));
619 609
620 ADVANCE_RING(); 610 ADVANCE_RING();
621 611
622 i += 3; 612 i += 3;
623 } while ( i < sarea_priv->nbox ); 613 } while (i < sarea_priv->nbox);
624 } 614 }
625 615
626 if ( buf_priv->discard ) { 616 if (buf_priv->discard) {
627 buf_priv->age = dev_priv->sarea_priv->last_dispatch; 617 buf_priv->age = dev_priv->sarea_priv->last_dispatch;
628 618
629 /* Emit the vertex buffer age */ 619 /* Emit the vertex buffer age */
630 BEGIN_RING( 2 ); 620 BEGIN_RING(2);
631 621
632 OUT_RING( CCE_PACKET0( R128_LAST_DISPATCH_REG, 0 ) ); 622 OUT_RING(CCE_PACKET0(R128_LAST_DISPATCH_REG, 0));
633 OUT_RING( buf_priv->age ); 623 OUT_RING(buf_priv->age);
634 624
635 ADVANCE_RING(); 625 ADVANCE_RING();
636 626
@@ -646,17 +636,15 @@ static void r128_cce_dispatch_vertex( drm_device_t *dev,
646 sarea_priv->nbox = 0; 636 sarea_priv->nbox = 0;
647} 637}
648 638
649static void r128_cce_dispatch_indirect( drm_device_t *dev, 639static void r128_cce_dispatch_indirect(drm_device_t * dev,
650 drm_buf_t *buf, 640 drm_buf_t * buf, int start, int end)
651 int start, int end )
652{ 641{
653 drm_r128_private_t *dev_priv = dev->dev_private; 642 drm_r128_private_t *dev_priv = dev->dev_private;
654 drm_r128_buf_priv_t *buf_priv = buf->dev_private; 643 drm_r128_buf_priv_t *buf_priv = buf->dev_private;
655 RING_LOCALS; 644 RING_LOCALS;
656 DRM_DEBUG( "indirect: buf=%d s=0x%x e=0x%x\n", 645 DRM_DEBUG("indirect: buf=%d s=0x%x e=0x%x\n", buf->idx, start, end);
657 buf->idx, start, end );
658 646
659 if ( start != end ) { 647 if (start != end) {
660 int offset = buf->bus_address + start; 648 int offset = buf->bus_address + start;
661 int dwords = (end - start + 3) / sizeof(u32); 649 int dwords = (end - start + 3) / sizeof(u32);
662 650
@@ -664,33 +652,33 @@ static void r128_cce_dispatch_indirect( drm_device_t *dev,
664 * dwords, so if we've been given an odd number we must 652 * dwords, so if we've been given an odd number we must
665 * pad the data with a Type-2 CCE packet. 653 * pad the data with a Type-2 CCE packet.
666 */ 654 */
667 if ( dwords & 1 ) { 655 if (dwords & 1) {
668 u32 *data = (u32 *) 656 u32 *data = (u32 *)
669 ((char *)dev->agp_buffer_map->handle 657 ((char *)dev->agp_buffer_map->handle
670 + buf->offset + start); 658 + buf->offset + start);
671 data[dwords++] = cpu_to_le32( R128_CCE_PACKET2 ); 659 data[dwords++] = cpu_to_le32(R128_CCE_PACKET2);
672 } 660 }
673 661
674 buf_priv->dispatched = 1; 662 buf_priv->dispatched = 1;
675 663
676 /* Fire off the indirect buffer */ 664 /* Fire off the indirect buffer */
677 BEGIN_RING( 3 ); 665 BEGIN_RING(3);
678 666
679 OUT_RING( CCE_PACKET0( R128_PM4_IW_INDOFF, 1 ) ); 667 OUT_RING(CCE_PACKET0(R128_PM4_IW_INDOFF, 1));
680 OUT_RING( offset ); 668 OUT_RING(offset);
681 OUT_RING( dwords ); 669 OUT_RING(dwords);
682 670
683 ADVANCE_RING(); 671 ADVANCE_RING();
684 } 672 }
685 673
686 if ( buf_priv->discard ) { 674 if (buf_priv->discard) {
687 buf_priv->age = dev_priv->sarea_priv->last_dispatch; 675 buf_priv->age = dev_priv->sarea_priv->last_dispatch;
688 676
689 /* Emit the indirect buffer age */ 677 /* Emit the indirect buffer age */
690 BEGIN_RING( 2 ); 678 BEGIN_RING(2);
691 679
692 OUT_RING( CCE_PACKET0( R128_LAST_DISPATCH_REG, 0 ) ); 680 OUT_RING(CCE_PACKET0(R128_LAST_DISPATCH_REG, 0));
693 OUT_RING( buf_priv->age ); 681 OUT_RING(buf_priv->age);
694 682
695 ADVANCE_RING(); 683 ADVANCE_RING();
696 684
@@ -703,10 +691,9 @@ static void r128_cce_dispatch_indirect( drm_device_t *dev,
703 dev_priv->sarea_priv->last_dispatch++; 691 dev_priv->sarea_priv->last_dispatch++;
704} 692}
705 693
706static void r128_cce_dispatch_indices( drm_device_t *dev, 694static void r128_cce_dispatch_indices(drm_device_t * dev,
707 drm_buf_t *buf, 695 drm_buf_t * buf,
708 int start, int end, 696 int start, int end, int count)
709 int count )
710{ 697{
711 drm_r128_private_t *dev_priv = dev->dev_private; 698 drm_r128_private_t *dev_priv = dev->dev_private;
712 drm_r128_buf_priv_t *buf_priv = buf->dev_private; 699 drm_r128_buf_priv_t *buf_priv = buf->dev_private;
@@ -718,62 +705,62 @@ static void r128_cce_dispatch_indices( drm_device_t *dev,
718 int dwords; 705 int dwords;
719 int i = 0; 706 int i = 0;
720 RING_LOCALS; 707 RING_LOCALS;
721 DRM_DEBUG( "indices: s=%d e=%d c=%d\n", start, end, count ); 708 DRM_DEBUG("indices: s=%d e=%d c=%d\n", start, end, count);
722 709
723 if ( 0 ) 710 if (0)
724 r128_print_dirty( "dispatch_indices", sarea_priv->dirty ); 711 r128_print_dirty("dispatch_indices", sarea_priv->dirty);
725 712
726 if ( start != end ) { 713 if (start != end) {
727 buf_priv->dispatched = 1; 714 buf_priv->dispatched = 1;
728 715
729 if ( sarea_priv->dirty & ~R128_UPLOAD_CLIPRECTS ) { 716 if (sarea_priv->dirty & ~R128_UPLOAD_CLIPRECTS) {
730 r128_emit_state( dev_priv ); 717 r128_emit_state(dev_priv);
731 } 718 }
732 719
733 dwords = (end - start + 3) / sizeof(u32); 720 dwords = (end - start + 3) / sizeof(u32);
734 721
735 data = (u32 *)((char *)dev->agp_buffer_map->handle 722 data = (u32 *) ((char *)dev->agp_buffer_map->handle
736 + buf->offset + start); 723 + buf->offset + start);
737 724
738 data[0] = cpu_to_le32( CCE_PACKET3( R128_3D_RNDR_GEN_INDX_PRIM, 725 data[0] = cpu_to_le32(CCE_PACKET3(R128_3D_RNDR_GEN_INDX_PRIM,
739 dwords-2 ) ); 726 dwords - 2));
740 727
741 data[1] = cpu_to_le32( offset ); 728 data[1] = cpu_to_le32(offset);
742 data[2] = cpu_to_le32( R128_MAX_VB_VERTS ); 729 data[2] = cpu_to_le32(R128_MAX_VB_VERTS);
743 data[3] = cpu_to_le32( format ); 730 data[3] = cpu_to_le32(format);
744 data[4] = cpu_to_le32( (prim | R128_CCE_VC_CNTL_PRIM_WALK_IND | 731 data[4] = cpu_to_le32((prim | R128_CCE_VC_CNTL_PRIM_WALK_IND |
745 (count << 16)) ); 732 (count << 16)));
746 733
747 if ( count & 0x1 ) { 734 if (count & 0x1) {
748#ifdef __LITTLE_ENDIAN 735#ifdef __LITTLE_ENDIAN
749 data[dwords-1] &= 0x0000ffff; 736 data[dwords - 1] &= 0x0000ffff;
750#else 737#else
751 data[dwords-1] &= 0xffff0000; 738 data[dwords - 1] &= 0xffff0000;
752#endif 739#endif
753 } 740 }
754 741
755 do { 742 do {
756 /* Emit the next set of up to three cliprects */ 743 /* Emit the next set of up to three cliprects */
757 if ( i < sarea_priv->nbox ) { 744 if (i < sarea_priv->nbox) {
758 r128_emit_clip_rects( dev_priv, 745 r128_emit_clip_rects(dev_priv,
759 &sarea_priv->boxes[i], 746 &sarea_priv->boxes[i],
760 sarea_priv->nbox - i ); 747 sarea_priv->nbox - i);
761 } 748 }
762 749
763 r128_cce_dispatch_indirect( dev, buf, start, end ); 750 r128_cce_dispatch_indirect(dev, buf, start, end);
764 751
765 i += 3; 752 i += 3;
766 } while ( i < sarea_priv->nbox ); 753 } while (i < sarea_priv->nbox);
767 } 754 }
768 755
769 if ( buf_priv->discard ) { 756 if (buf_priv->discard) {
770 buf_priv->age = dev_priv->sarea_priv->last_dispatch; 757 buf_priv->age = dev_priv->sarea_priv->last_dispatch;
771 758
772 /* Emit the vertex buffer age */ 759 /* Emit the vertex buffer age */
773 BEGIN_RING( 2 ); 760 BEGIN_RING(2);
774 761
775 OUT_RING( CCE_PACKET0( R128_LAST_DISPATCH_REG, 0 ) ); 762 OUT_RING(CCE_PACKET0(R128_LAST_DISPATCH_REG, 0));
776 OUT_RING( buf_priv->age ); 763 OUT_RING(buf_priv->age);
777 764
778 ADVANCE_RING(); 765 ADVANCE_RING();
779 766
@@ -788,9 +775,8 @@ static void r128_cce_dispatch_indices( drm_device_t *dev,
788 sarea_priv->nbox = 0; 775 sarea_priv->nbox = 0;
789} 776}
790 777
791static int r128_cce_dispatch_blit( DRMFILE filp, 778static int r128_cce_dispatch_blit(DRMFILE filp,
792 drm_device_t *dev, 779 drm_device_t * dev, drm_r128_blit_t * blit)
793 drm_r128_blit_t *blit )
794{ 780{
795 drm_r128_private_t *dev_priv = dev->dev_private; 781 drm_r128_private_t *dev_priv = dev->dev_private;
796 drm_device_dma_t *dma = dev->dma; 782 drm_device_dma_t *dma = dev->dma;
@@ -799,13 +785,13 @@ static int r128_cce_dispatch_blit( DRMFILE filp,
799 u32 *data; 785 u32 *data;
800 int dword_shift, dwords; 786 int dword_shift, dwords;
801 RING_LOCALS; 787 RING_LOCALS;
802 DRM_DEBUG( "\n" ); 788 DRM_DEBUG("\n");
803 789
804 /* The compiler won't optimize away a division by a variable, 790 /* The compiler won't optimize away a division by a variable,
805 * even if the only legal values are powers of two. Thus, we'll 791 * even if the only legal values are powers of two. Thus, we'll
806 * use a shift instead. 792 * use a shift instead.
807 */ 793 */
808 switch ( blit->format ) { 794 switch (blit->format) {
809 case R128_DATATYPE_ARGB8888: 795 case R128_DATATYPE_ARGB8888:
810 dword_shift = 0; 796 dword_shift = 0;
811 break; 797 break;
@@ -821,7 +807,7 @@ static int r128_cce_dispatch_blit( DRMFILE filp,
821 dword_shift = 2; 807 dword_shift = 2;
822 break; 808 break;
823 default: 809 default:
824 DRM_ERROR( "invalid blit format %d\n", blit->format ); 810 DRM_ERROR("invalid blit format %d\n", blit->format);
825 return DRM_ERR(EINVAL); 811 return DRM_ERR(EINVAL);
826 } 812 }
827 813
@@ -830,10 +816,10 @@ static int r128_cce_dispatch_blit( DRMFILE filp,
830 * data from the host data blit, otherwise part of the texture 816 * data from the host data blit, otherwise part of the texture
831 * image may be corrupted. 817 * image may be corrupted.
832 */ 818 */
833 BEGIN_RING( 2 ); 819 BEGIN_RING(2);
834 820
835 OUT_RING( CCE_PACKET0( R128_PC_GUI_CTLSTAT, 0 ) ); 821 OUT_RING(CCE_PACKET0(R128_PC_GUI_CTLSTAT, 0));
836 OUT_RING( R128_PC_RI_GUI | R128_PC_FLUSH_GUI ); 822 OUT_RING(R128_PC_RI_GUI | R128_PC_FLUSH_GUI);
837 823
838 ADVANCE_RING(); 824 ADVANCE_RING();
839 825
@@ -842,13 +828,13 @@ static int r128_cce_dispatch_blit( DRMFILE filp,
842 buf = dma->buflist[blit->idx]; 828 buf = dma->buflist[blit->idx];
843 buf_priv = buf->dev_private; 829 buf_priv = buf->dev_private;
844 830
845 if ( buf->filp != filp ) { 831 if (buf->filp != filp) {
846 DRM_ERROR( "process %d using buffer owned by %p\n", 832 DRM_ERROR("process %d using buffer owned by %p\n",
847 DRM_CURRENTPID, buf->filp ); 833 DRM_CURRENTPID, buf->filp);
848 return DRM_ERR(EINVAL); 834 return DRM_ERR(EINVAL);
849 } 835 }
850 if ( buf->pending ) { 836 if (buf->pending) {
851 DRM_ERROR( "sending pending buffer %d\n", blit->idx ); 837 DRM_ERROR("sending pending buffer %d\n", blit->idx);
852 return DRM_ERR(EINVAL); 838 return DRM_ERR(EINVAL);
853 } 839 }
854 840
@@ -856,45 +842,43 @@ static int r128_cce_dispatch_blit( DRMFILE filp,
856 842
857 dwords = (blit->width * blit->height) >> dword_shift; 843 dwords = (blit->width * blit->height) >> dword_shift;
858 844
859 data = (u32 *)((char *)dev->agp_buffer_map->handle + buf->offset); 845 data = (u32 *) ((char *)dev->agp_buffer_map->handle + buf->offset);
860 846
861 data[0] = cpu_to_le32( CCE_PACKET3( R128_CNTL_HOSTDATA_BLT, dwords + 6 ) ); 847 data[0] = cpu_to_le32(CCE_PACKET3(R128_CNTL_HOSTDATA_BLT, dwords + 6));
862 data[1] = cpu_to_le32( (R128_GMC_DST_PITCH_OFFSET_CNTL | 848 data[1] = cpu_to_le32((R128_GMC_DST_PITCH_OFFSET_CNTL |
863 R128_GMC_BRUSH_NONE | 849 R128_GMC_BRUSH_NONE |
864 (blit->format << 8) | 850 (blit->format << 8) |
865 R128_GMC_SRC_DATATYPE_COLOR | 851 R128_GMC_SRC_DATATYPE_COLOR |
866 R128_ROP3_S | 852 R128_ROP3_S |
867 R128_DP_SRC_SOURCE_HOST_DATA | 853 R128_DP_SRC_SOURCE_HOST_DATA |
868 R128_GMC_CLR_CMP_CNTL_DIS | 854 R128_GMC_CLR_CMP_CNTL_DIS |
869 R128_GMC_AUX_CLIP_DIS | 855 R128_GMC_AUX_CLIP_DIS | R128_GMC_WR_MSK_DIS));
870 R128_GMC_WR_MSK_DIS) ); 856
871 857 data[2] = cpu_to_le32((blit->pitch << 21) | (blit->offset >> 5));
872 data[2] = cpu_to_le32( (blit->pitch << 21) | (blit->offset >> 5) ); 858 data[3] = cpu_to_le32(0xffffffff);
873 data[3] = cpu_to_le32( 0xffffffff ); 859 data[4] = cpu_to_le32(0xffffffff);
874 data[4] = cpu_to_le32( 0xffffffff ); 860 data[5] = cpu_to_le32((blit->y << 16) | blit->x);
875 data[5] = cpu_to_le32( (blit->y << 16) | blit->x ); 861 data[6] = cpu_to_le32((blit->height << 16) | blit->width);
876 data[6] = cpu_to_le32( (blit->height << 16) | blit->width ); 862 data[7] = cpu_to_le32(dwords);
877 data[7] = cpu_to_le32( dwords );
878 863
879 buf->used = (dwords + 8) * sizeof(u32); 864 buf->used = (dwords + 8) * sizeof(u32);
880 865
881 r128_cce_dispatch_indirect( dev, buf, 0, buf->used ); 866 r128_cce_dispatch_indirect(dev, buf, 0, buf->used);
882 867
883 /* Flush the pixel cache after the blit completes. This ensures 868 /* Flush the pixel cache after the blit completes. This ensures
884 * the texture data is written out to memory before rendering 869 * the texture data is written out to memory before rendering
885 * continues. 870 * continues.
886 */ 871 */
887 BEGIN_RING( 2 ); 872 BEGIN_RING(2);
888 873
889 OUT_RING( CCE_PACKET0( R128_PC_GUI_CTLSTAT, 0 ) ); 874 OUT_RING(CCE_PACKET0(R128_PC_GUI_CTLSTAT, 0));
890 OUT_RING( R128_PC_FLUSH_GUI ); 875 OUT_RING(R128_PC_FLUSH_GUI);
891 876
892 ADVANCE_RING(); 877 ADVANCE_RING();
893 878
894 return 0; 879 return 0;
895} 880}
896 881
897
898/* ================================================================ 882/* ================================================================
899 * Tiled depth buffer management 883 * Tiled depth buffer management
900 * 884 *
@@ -902,8 +886,8 @@ static int r128_cce_dispatch_blit( DRMFILE filp,
902 * have hardware stencil support. 886 * have hardware stencil support.
903 */ 887 */
904 888
905static int r128_cce_dispatch_write_span( drm_device_t *dev, 889static int r128_cce_dispatch_write_span(drm_device_t * dev,
906 drm_r128_depth_t *depth ) 890 drm_r128_depth_t * depth)
907{ 891{
908 drm_r128_private_t *dev_priv = dev->dev_private; 892 drm_r128_private_t *dev_priv = dev->dev_private;
909 int count, x, y; 893 int count, x, y;
@@ -911,95 +895,95 @@ static int r128_cce_dispatch_write_span( drm_device_t *dev,
911 u8 *mask; 895 u8 *mask;
912 int i, buffer_size, mask_size; 896 int i, buffer_size, mask_size;
913 RING_LOCALS; 897 RING_LOCALS;
914 DRM_DEBUG( "\n" ); 898 DRM_DEBUG("\n");
915 899
916 count = depth->n; 900 count = depth->n;
917 if (count > 4096 || count <= 0) 901 if (count > 4096 || count <= 0)
918 return DRM_ERR(EMSGSIZE); 902 return DRM_ERR(EMSGSIZE);
919 903
920 if ( DRM_COPY_FROM_USER( &x, depth->x, sizeof(x) ) ) { 904 if (DRM_COPY_FROM_USER(&x, depth->x, sizeof(x))) {
921 return DRM_ERR(EFAULT); 905 return DRM_ERR(EFAULT);
922 } 906 }
923 if ( DRM_COPY_FROM_USER( &y, depth->y, sizeof(y) ) ) { 907 if (DRM_COPY_FROM_USER(&y, depth->y, sizeof(y))) {
924 return DRM_ERR(EFAULT); 908 return DRM_ERR(EFAULT);
925 } 909 }
926 910
927 buffer_size = depth->n * sizeof(u32); 911 buffer_size = depth->n * sizeof(u32);
928 buffer = drm_alloc( buffer_size, DRM_MEM_BUFS ); 912 buffer = drm_alloc(buffer_size, DRM_MEM_BUFS);
929 if ( buffer == NULL ) 913 if (buffer == NULL)
930 return DRM_ERR(ENOMEM); 914 return DRM_ERR(ENOMEM);
931 if ( DRM_COPY_FROM_USER( buffer, depth->buffer, buffer_size ) ) { 915 if (DRM_COPY_FROM_USER(buffer, depth->buffer, buffer_size)) {
932 drm_free( buffer, buffer_size, DRM_MEM_BUFS); 916 drm_free(buffer, buffer_size, DRM_MEM_BUFS);
933 return DRM_ERR(EFAULT); 917 return DRM_ERR(EFAULT);
934 } 918 }
935 919
936 mask_size = depth->n * sizeof(u8); 920 mask_size = depth->n * sizeof(u8);
937 if ( depth->mask ) { 921 if (depth->mask) {
938 mask = drm_alloc( mask_size, DRM_MEM_BUFS ); 922 mask = drm_alloc(mask_size, DRM_MEM_BUFS);
939 if ( mask == NULL ) { 923 if (mask == NULL) {
940 drm_free( buffer, buffer_size, DRM_MEM_BUFS ); 924 drm_free(buffer, buffer_size, DRM_MEM_BUFS);
941 return DRM_ERR(ENOMEM); 925 return DRM_ERR(ENOMEM);
942 } 926 }
943 if ( DRM_COPY_FROM_USER( mask, depth->mask, mask_size ) ) { 927 if (DRM_COPY_FROM_USER(mask, depth->mask, mask_size)) {
944 drm_free( buffer, buffer_size, DRM_MEM_BUFS ); 928 drm_free(buffer, buffer_size, DRM_MEM_BUFS);
945 drm_free( mask, mask_size, DRM_MEM_BUFS ); 929 drm_free(mask, mask_size, DRM_MEM_BUFS);
946 return DRM_ERR(EFAULT); 930 return DRM_ERR(EFAULT);
947 } 931 }
948 932
949 for ( i = 0 ; i < count ; i++, x++ ) { 933 for (i = 0; i < count; i++, x++) {
950 if ( mask[i] ) { 934 if (mask[i]) {
951 BEGIN_RING( 6 ); 935 BEGIN_RING(6);
952 936
953 OUT_RING( CCE_PACKET3( R128_CNTL_PAINT_MULTI, 4 ) ); 937 OUT_RING(CCE_PACKET3(R128_CNTL_PAINT_MULTI, 4));
954 OUT_RING( R128_GMC_DST_PITCH_OFFSET_CNTL | 938 OUT_RING(R128_GMC_DST_PITCH_OFFSET_CNTL |
955 R128_GMC_BRUSH_SOLID_COLOR | 939 R128_GMC_BRUSH_SOLID_COLOR |
956 (dev_priv->depth_fmt << 8) | 940 (dev_priv->depth_fmt << 8) |
957 R128_GMC_SRC_DATATYPE_COLOR | 941 R128_GMC_SRC_DATATYPE_COLOR |
958 R128_ROP3_P | 942 R128_ROP3_P |
959 R128_GMC_CLR_CMP_CNTL_DIS | 943 R128_GMC_CLR_CMP_CNTL_DIS |
960 R128_GMC_WR_MSK_DIS ); 944 R128_GMC_WR_MSK_DIS);
961 945
962 OUT_RING( dev_priv->depth_pitch_offset_c ); 946 OUT_RING(dev_priv->depth_pitch_offset_c);
963 OUT_RING( buffer[i] ); 947 OUT_RING(buffer[i]);
964 948
965 OUT_RING( (x << 16) | y ); 949 OUT_RING((x << 16) | y);
966 OUT_RING( (1 << 16) | 1 ); 950 OUT_RING((1 << 16) | 1);
967 951
968 ADVANCE_RING(); 952 ADVANCE_RING();
969 } 953 }
970 } 954 }
971 955
972 drm_free( mask, mask_size, DRM_MEM_BUFS ); 956 drm_free(mask, mask_size, DRM_MEM_BUFS);
973 } else { 957 } else {
974 for ( i = 0 ; i < count ; i++, x++ ) { 958 for (i = 0; i < count; i++, x++) {
975 BEGIN_RING( 6 ); 959 BEGIN_RING(6);
976 960
977 OUT_RING( CCE_PACKET3( R128_CNTL_PAINT_MULTI, 4 ) ); 961 OUT_RING(CCE_PACKET3(R128_CNTL_PAINT_MULTI, 4));
978 OUT_RING( R128_GMC_DST_PITCH_OFFSET_CNTL | 962 OUT_RING(R128_GMC_DST_PITCH_OFFSET_CNTL |
979 R128_GMC_BRUSH_SOLID_COLOR | 963 R128_GMC_BRUSH_SOLID_COLOR |
980 (dev_priv->depth_fmt << 8) | 964 (dev_priv->depth_fmt << 8) |
981 R128_GMC_SRC_DATATYPE_COLOR | 965 R128_GMC_SRC_DATATYPE_COLOR |
982 R128_ROP3_P | 966 R128_ROP3_P |
983 R128_GMC_CLR_CMP_CNTL_DIS | 967 R128_GMC_CLR_CMP_CNTL_DIS |
984 R128_GMC_WR_MSK_DIS ); 968 R128_GMC_WR_MSK_DIS);
985 969
986 OUT_RING( dev_priv->depth_pitch_offset_c ); 970 OUT_RING(dev_priv->depth_pitch_offset_c);
987 OUT_RING( buffer[i] ); 971 OUT_RING(buffer[i]);
988 972
989 OUT_RING( (x << 16) | y ); 973 OUT_RING((x << 16) | y);
990 OUT_RING( (1 << 16) | 1 ); 974 OUT_RING((1 << 16) | 1);
991 975
992 ADVANCE_RING(); 976 ADVANCE_RING();
993 } 977 }
994 } 978 }
995 979
996 drm_free( buffer, buffer_size, DRM_MEM_BUFS ); 980 drm_free(buffer, buffer_size, DRM_MEM_BUFS);
997 981
998 return 0; 982 return 0;
999} 983}
1000 984
1001static int r128_cce_dispatch_write_pixels( drm_device_t *dev, 985static int r128_cce_dispatch_write_pixels(drm_device_t * dev,
1002 drm_r128_depth_t *depth ) 986 drm_r128_depth_t * depth)
1003{ 987{
1004 drm_r128_private_t *dev_priv = dev->dev_private; 988 drm_r128_private_t *dev_priv = dev->dev_private;
1005 int count, *x, *y; 989 int count, *x, *y;
@@ -1007,7 +991,7 @@ static int r128_cce_dispatch_write_pixels( drm_device_t *dev,
1007 u8 *mask; 991 u8 *mask;
1008 int i, xbuf_size, ybuf_size, buffer_size, mask_size; 992 int i, xbuf_size, ybuf_size, buffer_size, mask_size;
1009 RING_LOCALS; 993 RING_LOCALS;
1010 DRM_DEBUG( "\n" ); 994 DRM_DEBUG("\n");
1011 995
1012 count = depth->n; 996 count = depth->n;
1013 if (count > 4096 || count <= 0) 997 if (count > 4096 || count <= 0)
@@ -1015,270 +999,266 @@ static int r128_cce_dispatch_write_pixels( drm_device_t *dev,
1015 999
1016 xbuf_size = count * sizeof(*x); 1000 xbuf_size = count * sizeof(*x);
1017 ybuf_size = count * sizeof(*y); 1001 ybuf_size = count * sizeof(*y);
1018 x = drm_alloc( xbuf_size, DRM_MEM_BUFS ); 1002 x = drm_alloc(xbuf_size, DRM_MEM_BUFS);
1019 if ( x == NULL ) { 1003 if (x == NULL) {
1020 return DRM_ERR(ENOMEM); 1004 return DRM_ERR(ENOMEM);
1021 } 1005 }
1022 y = drm_alloc( ybuf_size, DRM_MEM_BUFS ); 1006 y = drm_alloc(ybuf_size, DRM_MEM_BUFS);
1023 if ( y == NULL ) { 1007 if (y == NULL) {
1024 drm_free( x, xbuf_size, DRM_MEM_BUFS ); 1008 drm_free(x, xbuf_size, DRM_MEM_BUFS);
1025 return DRM_ERR(ENOMEM); 1009 return DRM_ERR(ENOMEM);
1026 } 1010 }
1027 if ( DRM_COPY_FROM_USER( x, depth->x, xbuf_size ) ) { 1011 if (DRM_COPY_FROM_USER(x, depth->x, xbuf_size)) {
1028 drm_free( x, xbuf_size, DRM_MEM_BUFS ); 1012 drm_free(x, xbuf_size, DRM_MEM_BUFS);
1029 drm_free( y, ybuf_size, DRM_MEM_BUFS ); 1013 drm_free(y, ybuf_size, DRM_MEM_BUFS);
1030 return DRM_ERR(EFAULT); 1014 return DRM_ERR(EFAULT);
1031 } 1015 }
1032 if ( DRM_COPY_FROM_USER( y, depth->y, xbuf_size ) ) { 1016 if (DRM_COPY_FROM_USER(y, depth->y, xbuf_size)) {
1033 drm_free( x, xbuf_size, DRM_MEM_BUFS ); 1017 drm_free(x, xbuf_size, DRM_MEM_BUFS);
1034 drm_free( y, ybuf_size, DRM_MEM_BUFS ); 1018 drm_free(y, ybuf_size, DRM_MEM_BUFS);
1035 return DRM_ERR(EFAULT); 1019 return DRM_ERR(EFAULT);
1036 } 1020 }
1037 1021
1038 buffer_size = depth->n * sizeof(u32); 1022 buffer_size = depth->n * sizeof(u32);
1039 buffer = drm_alloc( buffer_size, DRM_MEM_BUFS ); 1023 buffer = drm_alloc(buffer_size, DRM_MEM_BUFS);
1040 if ( buffer == NULL ) { 1024 if (buffer == NULL) {
1041 drm_free( x, xbuf_size, DRM_MEM_BUFS ); 1025 drm_free(x, xbuf_size, DRM_MEM_BUFS);
1042 drm_free( y, ybuf_size, DRM_MEM_BUFS ); 1026 drm_free(y, ybuf_size, DRM_MEM_BUFS);
1043 return DRM_ERR(ENOMEM); 1027 return DRM_ERR(ENOMEM);
1044 } 1028 }
1045 if ( DRM_COPY_FROM_USER( buffer, depth->buffer, buffer_size ) ) { 1029 if (DRM_COPY_FROM_USER(buffer, depth->buffer, buffer_size)) {
1046 drm_free( x, xbuf_size, DRM_MEM_BUFS ); 1030 drm_free(x, xbuf_size, DRM_MEM_BUFS);
1047 drm_free( y, ybuf_size, DRM_MEM_BUFS ); 1031 drm_free(y, ybuf_size, DRM_MEM_BUFS);
1048 drm_free( buffer, buffer_size, DRM_MEM_BUFS ); 1032 drm_free(buffer, buffer_size, DRM_MEM_BUFS);
1049 return DRM_ERR(EFAULT); 1033 return DRM_ERR(EFAULT);
1050 } 1034 }
1051 1035
1052 if ( depth->mask ) { 1036 if (depth->mask) {
1053 mask_size = depth->n * sizeof(u8); 1037 mask_size = depth->n * sizeof(u8);
1054 mask = drm_alloc( mask_size, DRM_MEM_BUFS ); 1038 mask = drm_alloc(mask_size, DRM_MEM_BUFS);
1055 if ( mask == NULL ) { 1039 if (mask == NULL) {
1056 drm_free( x, xbuf_size, DRM_MEM_BUFS ); 1040 drm_free(x, xbuf_size, DRM_MEM_BUFS);
1057 drm_free( y, ybuf_size, DRM_MEM_BUFS ); 1041 drm_free(y, ybuf_size, DRM_MEM_BUFS);
1058 drm_free( buffer, buffer_size, DRM_MEM_BUFS ); 1042 drm_free(buffer, buffer_size, DRM_MEM_BUFS);
1059 return DRM_ERR(ENOMEM); 1043 return DRM_ERR(ENOMEM);
1060 } 1044 }
1061 if ( DRM_COPY_FROM_USER( mask, depth->mask, mask_size ) ) { 1045 if (DRM_COPY_FROM_USER(mask, depth->mask, mask_size)) {
1062 drm_free( x, xbuf_size, DRM_MEM_BUFS ); 1046 drm_free(x, xbuf_size, DRM_MEM_BUFS);
1063 drm_free( y, ybuf_size, DRM_MEM_BUFS ); 1047 drm_free(y, ybuf_size, DRM_MEM_BUFS);
1064 drm_free( buffer, buffer_size, DRM_MEM_BUFS ); 1048 drm_free(buffer, buffer_size, DRM_MEM_BUFS);
1065 drm_free( mask, mask_size, DRM_MEM_BUFS ); 1049 drm_free(mask, mask_size, DRM_MEM_BUFS);
1066 return DRM_ERR(EFAULT); 1050 return DRM_ERR(EFAULT);
1067 } 1051 }
1068 1052
1069 for ( i = 0 ; i < count ; i++ ) { 1053 for (i = 0; i < count; i++) {
1070 if ( mask[i] ) { 1054 if (mask[i]) {
1071 BEGIN_RING( 6 ); 1055 BEGIN_RING(6);
1072 1056
1073 OUT_RING( CCE_PACKET3( R128_CNTL_PAINT_MULTI, 4 ) ); 1057 OUT_RING(CCE_PACKET3(R128_CNTL_PAINT_MULTI, 4));
1074 OUT_RING( R128_GMC_DST_PITCH_OFFSET_CNTL | 1058 OUT_RING(R128_GMC_DST_PITCH_OFFSET_CNTL |
1075 R128_GMC_BRUSH_SOLID_COLOR | 1059 R128_GMC_BRUSH_SOLID_COLOR |
1076 (dev_priv->depth_fmt << 8) | 1060 (dev_priv->depth_fmt << 8) |
1077 R128_GMC_SRC_DATATYPE_COLOR | 1061 R128_GMC_SRC_DATATYPE_COLOR |
1078 R128_ROP3_P | 1062 R128_ROP3_P |
1079 R128_GMC_CLR_CMP_CNTL_DIS | 1063 R128_GMC_CLR_CMP_CNTL_DIS |
1080 R128_GMC_WR_MSK_DIS ); 1064 R128_GMC_WR_MSK_DIS);
1081 1065
1082 OUT_RING( dev_priv->depth_pitch_offset_c ); 1066 OUT_RING(dev_priv->depth_pitch_offset_c);
1083 OUT_RING( buffer[i] ); 1067 OUT_RING(buffer[i]);
1084 1068
1085 OUT_RING( (x[i] << 16) | y[i] ); 1069 OUT_RING((x[i] << 16) | y[i]);
1086 OUT_RING( (1 << 16) | 1 ); 1070 OUT_RING((1 << 16) | 1);
1087 1071
1088 ADVANCE_RING(); 1072 ADVANCE_RING();
1089 } 1073 }
1090 } 1074 }
1091 1075
1092 drm_free( mask, mask_size, DRM_MEM_BUFS ); 1076 drm_free(mask, mask_size, DRM_MEM_BUFS);
1093 } else { 1077 } else {
1094 for ( i = 0 ; i < count ; i++ ) { 1078 for (i = 0; i < count; i++) {
1095 BEGIN_RING( 6 ); 1079 BEGIN_RING(6);
1096 1080
1097 OUT_RING( CCE_PACKET3( R128_CNTL_PAINT_MULTI, 4 ) ); 1081 OUT_RING(CCE_PACKET3(R128_CNTL_PAINT_MULTI, 4));
1098 OUT_RING( R128_GMC_DST_PITCH_OFFSET_CNTL | 1082 OUT_RING(R128_GMC_DST_PITCH_OFFSET_CNTL |
1099 R128_GMC_BRUSH_SOLID_COLOR | 1083 R128_GMC_BRUSH_SOLID_COLOR |
1100 (dev_priv->depth_fmt << 8) | 1084 (dev_priv->depth_fmt << 8) |
1101 R128_GMC_SRC_DATATYPE_COLOR | 1085 R128_GMC_SRC_DATATYPE_COLOR |
1102 R128_ROP3_P | 1086 R128_ROP3_P |
1103 R128_GMC_CLR_CMP_CNTL_DIS | 1087 R128_GMC_CLR_CMP_CNTL_DIS |
1104 R128_GMC_WR_MSK_DIS ); 1088 R128_GMC_WR_MSK_DIS);
1105 1089
1106 OUT_RING( dev_priv->depth_pitch_offset_c ); 1090 OUT_RING(dev_priv->depth_pitch_offset_c);
1107 OUT_RING( buffer[i] ); 1091 OUT_RING(buffer[i]);
1108 1092
1109 OUT_RING( (x[i] << 16) | y[i] ); 1093 OUT_RING((x[i] << 16) | y[i]);
1110 OUT_RING( (1 << 16) | 1 ); 1094 OUT_RING((1 << 16) | 1);
1111 1095
1112 ADVANCE_RING(); 1096 ADVANCE_RING();
1113 } 1097 }
1114 } 1098 }
1115 1099
1116 drm_free( x, xbuf_size, DRM_MEM_BUFS ); 1100 drm_free(x, xbuf_size, DRM_MEM_BUFS);
1117 drm_free( y, ybuf_size, DRM_MEM_BUFS ); 1101 drm_free(y, ybuf_size, DRM_MEM_BUFS);
1118 drm_free( buffer, buffer_size, DRM_MEM_BUFS ); 1102 drm_free(buffer, buffer_size, DRM_MEM_BUFS);
1119 1103
1120 return 0; 1104 return 0;
1121} 1105}
1122 1106
1123static int r128_cce_dispatch_read_span( drm_device_t *dev, 1107static int r128_cce_dispatch_read_span(drm_device_t * dev,
1124 drm_r128_depth_t *depth ) 1108 drm_r128_depth_t * depth)
1125{ 1109{
1126 drm_r128_private_t *dev_priv = dev->dev_private; 1110 drm_r128_private_t *dev_priv = dev->dev_private;
1127 int count, x, y; 1111 int count, x, y;
1128 RING_LOCALS; 1112 RING_LOCALS;
1129 DRM_DEBUG( "\n" ); 1113 DRM_DEBUG("\n");
1130 1114
1131 count = depth->n; 1115 count = depth->n;
1132 if (count > 4096 || count <= 0) 1116 if (count > 4096 || count <= 0)
1133 return DRM_ERR(EMSGSIZE); 1117 return DRM_ERR(EMSGSIZE);
1134 1118
1135 if ( DRM_COPY_FROM_USER( &x, depth->x, sizeof(x) ) ) { 1119 if (DRM_COPY_FROM_USER(&x, depth->x, sizeof(x))) {
1136 return DRM_ERR(EFAULT); 1120 return DRM_ERR(EFAULT);
1137 } 1121 }
1138 if ( DRM_COPY_FROM_USER( &y, depth->y, sizeof(y) ) ) { 1122 if (DRM_COPY_FROM_USER(&y, depth->y, sizeof(y))) {
1139 return DRM_ERR(EFAULT); 1123 return DRM_ERR(EFAULT);
1140 } 1124 }
1141 1125
1142 BEGIN_RING( 7 ); 1126 BEGIN_RING(7);
1143 1127
1144 OUT_RING( CCE_PACKET3( R128_CNTL_BITBLT_MULTI, 5 ) ); 1128 OUT_RING(CCE_PACKET3(R128_CNTL_BITBLT_MULTI, 5));
1145 OUT_RING( R128_GMC_SRC_PITCH_OFFSET_CNTL | 1129 OUT_RING(R128_GMC_SRC_PITCH_OFFSET_CNTL |
1146 R128_GMC_DST_PITCH_OFFSET_CNTL | 1130 R128_GMC_DST_PITCH_OFFSET_CNTL |
1147 R128_GMC_BRUSH_NONE | 1131 R128_GMC_BRUSH_NONE |
1148 (dev_priv->depth_fmt << 8) | 1132 (dev_priv->depth_fmt << 8) |
1149 R128_GMC_SRC_DATATYPE_COLOR | 1133 R128_GMC_SRC_DATATYPE_COLOR |
1150 R128_ROP3_S | 1134 R128_ROP3_S |
1151 R128_DP_SRC_SOURCE_MEMORY | 1135 R128_DP_SRC_SOURCE_MEMORY |
1152 R128_GMC_CLR_CMP_CNTL_DIS | 1136 R128_GMC_CLR_CMP_CNTL_DIS | R128_GMC_WR_MSK_DIS);
1153 R128_GMC_WR_MSK_DIS );
1154 1137
1155 OUT_RING( dev_priv->depth_pitch_offset_c ); 1138 OUT_RING(dev_priv->depth_pitch_offset_c);
1156 OUT_RING( dev_priv->span_pitch_offset_c ); 1139 OUT_RING(dev_priv->span_pitch_offset_c);
1157 1140
1158 OUT_RING( (x << 16) | y ); 1141 OUT_RING((x << 16) | y);
1159 OUT_RING( (0 << 16) | 0 ); 1142 OUT_RING((0 << 16) | 0);
1160 OUT_RING( (count << 16) | 1 ); 1143 OUT_RING((count << 16) | 1);
1161 1144
1162 ADVANCE_RING(); 1145 ADVANCE_RING();
1163 1146
1164 return 0; 1147 return 0;
1165} 1148}
1166 1149
1167static int r128_cce_dispatch_read_pixels( drm_device_t *dev, 1150static int r128_cce_dispatch_read_pixels(drm_device_t * dev,
1168 drm_r128_depth_t *depth ) 1151 drm_r128_depth_t * depth)
1169{ 1152{
1170 drm_r128_private_t *dev_priv = dev->dev_private; 1153 drm_r128_private_t *dev_priv = dev->dev_private;
1171 int count, *x, *y; 1154 int count, *x, *y;
1172 int i, xbuf_size, ybuf_size; 1155 int i, xbuf_size, ybuf_size;
1173 RING_LOCALS; 1156 RING_LOCALS;
1174 DRM_DEBUG( "%s\n", __FUNCTION__ ); 1157 DRM_DEBUG("%s\n", __FUNCTION__);
1175 1158
1176 count = depth->n; 1159 count = depth->n;
1177 if (count > 4096 || count <= 0) 1160 if (count > 4096 || count <= 0)
1178 return DRM_ERR(EMSGSIZE); 1161 return DRM_ERR(EMSGSIZE);
1179 1162
1180 if ( count > dev_priv->depth_pitch ) { 1163 if (count > dev_priv->depth_pitch) {
1181 count = dev_priv->depth_pitch; 1164 count = dev_priv->depth_pitch;
1182 } 1165 }
1183 1166
1184 xbuf_size = count * sizeof(*x); 1167 xbuf_size = count * sizeof(*x);
1185 ybuf_size = count * sizeof(*y); 1168 ybuf_size = count * sizeof(*y);
1186 x = drm_alloc( xbuf_size, DRM_MEM_BUFS ); 1169 x = drm_alloc(xbuf_size, DRM_MEM_BUFS);
1187 if ( x == NULL ) { 1170 if (x == NULL) {
1188 return DRM_ERR(ENOMEM); 1171 return DRM_ERR(ENOMEM);
1189 } 1172 }
1190 y = drm_alloc( ybuf_size, DRM_MEM_BUFS ); 1173 y = drm_alloc(ybuf_size, DRM_MEM_BUFS);
1191 if ( y == NULL ) { 1174 if (y == NULL) {
1192 drm_free( x, xbuf_size, DRM_MEM_BUFS ); 1175 drm_free(x, xbuf_size, DRM_MEM_BUFS);
1193 return DRM_ERR(ENOMEM); 1176 return DRM_ERR(ENOMEM);
1194 } 1177 }
1195 if ( DRM_COPY_FROM_USER( x, depth->x, xbuf_size ) ) { 1178 if (DRM_COPY_FROM_USER(x, depth->x, xbuf_size)) {
1196 drm_free( x, xbuf_size, DRM_MEM_BUFS ); 1179 drm_free(x, xbuf_size, DRM_MEM_BUFS);
1197 drm_free( y, ybuf_size, DRM_MEM_BUFS ); 1180 drm_free(y, ybuf_size, DRM_MEM_BUFS);
1198 return DRM_ERR(EFAULT); 1181 return DRM_ERR(EFAULT);
1199 } 1182 }
1200 if ( DRM_COPY_FROM_USER( y, depth->y, ybuf_size ) ) { 1183 if (DRM_COPY_FROM_USER(y, depth->y, ybuf_size)) {
1201 drm_free( x, xbuf_size, DRM_MEM_BUFS ); 1184 drm_free(x, xbuf_size, DRM_MEM_BUFS);
1202 drm_free( y, ybuf_size, DRM_MEM_BUFS ); 1185 drm_free(y, ybuf_size, DRM_MEM_BUFS);
1203 return DRM_ERR(EFAULT); 1186 return DRM_ERR(EFAULT);
1204 } 1187 }
1205 1188
1206 for ( i = 0 ; i < count ; i++ ) { 1189 for (i = 0; i < count; i++) {
1207 BEGIN_RING( 7 ); 1190 BEGIN_RING(7);
1208 1191
1209 OUT_RING( CCE_PACKET3( R128_CNTL_BITBLT_MULTI, 5 ) ); 1192 OUT_RING(CCE_PACKET3(R128_CNTL_BITBLT_MULTI, 5));
1210 OUT_RING( R128_GMC_SRC_PITCH_OFFSET_CNTL | 1193 OUT_RING(R128_GMC_SRC_PITCH_OFFSET_CNTL |
1211 R128_GMC_DST_PITCH_OFFSET_CNTL | 1194 R128_GMC_DST_PITCH_OFFSET_CNTL |
1212 R128_GMC_BRUSH_NONE | 1195 R128_GMC_BRUSH_NONE |
1213 (dev_priv->depth_fmt << 8) | 1196 (dev_priv->depth_fmt << 8) |
1214 R128_GMC_SRC_DATATYPE_COLOR | 1197 R128_GMC_SRC_DATATYPE_COLOR |
1215 R128_ROP3_S | 1198 R128_ROP3_S |
1216 R128_DP_SRC_SOURCE_MEMORY | 1199 R128_DP_SRC_SOURCE_MEMORY |
1217 R128_GMC_CLR_CMP_CNTL_DIS | 1200 R128_GMC_CLR_CMP_CNTL_DIS | R128_GMC_WR_MSK_DIS);
1218 R128_GMC_WR_MSK_DIS );
1219 1201
1220 OUT_RING( dev_priv->depth_pitch_offset_c ); 1202 OUT_RING(dev_priv->depth_pitch_offset_c);
1221 OUT_RING( dev_priv->span_pitch_offset_c ); 1203 OUT_RING(dev_priv->span_pitch_offset_c);
1222 1204
1223 OUT_RING( (x[i] << 16) | y[i] ); 1205 OUT_RING((x[i] << 16) | y[i]);
1224 OUT_RING( (i << 16) | 0 ); 1206 OUT_RING((i << 16) | 0);
1225 OUT_RING( (1 << 16) | 1 ); 1207 OUT_RING((1 << 16) | 1);
1226 1208
1227 ADVANCE_RING(); 1209 ADVANCE_RING();
1228 } 1210 }
1229 1211
1230 drm_free( x, xbuf_size, DRM_MEM_BUFS ); 1212 drm_free(x, xbuf_size, DRM_MEM_BUFS);
1231 drm_free( y, ybuf_size, DRM_MEM_BUFS ); 1213 drm_free(y, ybuf_size, DRM_MEM_BUFS);
1232 1214
1233 return 0; 1215 return 0;
1234} 1216}
1235 1217
1236
1237/* ================================================================ 1218/* ================================================================
1238 * Polygon stipple 1219 * Polygon stipple
1239 */ 1220 */
1240 1221
1241static void r128_cce_dispatch_stipple( drm_device_t *dev, u32 *stipple ) 1222static void r128_cce_dispatch_stipple(drm_device_t * dev, u32 * stipple)
1242{ 1223{
1243 drm_r128_private_t *dev_priv = dev->dev_private; 1224 drm_r128_private_t *dev_priv = dev->dev_private;
1244 int i; 1225 int i;
1245 RING_LOCALS; 1226 RING_LOCALS;
1246 DRM_DEBUG( "%s\n", __FUNCTION__ ); 1227 DRM_DEBUG("%s\n", __FUNCTION__);
1247 1228
1248 BEGIN_RING( 33 ); 1229 BEGIN_RING(33);
1249 1230
1250 OUT_RING( CCE_PACKET0( R128_BRUSH_DATA0, 31 ) ); 1231 OUT_RING(CCE_PACKET0(R128_BRUSH_DATA0, 31));
1251 for ( i = 0 ; i < 32 ; i++ ) { 1232 for (i = 0; i < 32; i++) {
1252 OUT_RING( stipple[i] ); 1233 OUT_RING(stipple[i]);
1253 } 1234 }
1254 1235
1255 ADVANCE_RING(); 1236 ADVANCE_RING();
1256} 1237}
1257 1238
1258
1259/* ================================================================ 1239/* ================================================================
1260 * IOCTL functions 1240 * IOCTL functions
1261 */ 1241 */
1262 1242
1263static int r128_cce_clear( DRM_IOCTL_ARGS ) 1243static int r128_cce_clear(DRM_IOCTL_ARGS)
1264{ 1244{
1265 DRM_DEVICE; 1245 DRM_DEVICE;
1266 drm_r128_private_t *dev_priv = dev->dev_private; 1246 drm_r128_private_t *dev_priv = dev->dev_private;
1267 drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; 1247 drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
1268 drm_r128_clear_t clear; 1248 drm_r128_clear_t clear;
1269 DRM_DEBUG( "\n" ); 1249 DRM_DEBUG("\n");
1270 1250
1271 LOCK_TEST_WITH_RETURN( dev, filp ); 1251 LOCK_TEST_WITH_RETURN(dev, filp);
1272 1252
1273 DRM_COPY_FROM_USER_IOCTL( clear, (drm_r128_clear_t __user *) data, 1253 DRM_COPY_FROM_USER_IOCTL(clear, (drm_r128_clear_t __user *) data,
1274 sizeof(clear) ); 1254 sizeof(clear));
1275 1255
1276 RING_SPACE_TEST_WITH_RETURN( dev_priv ); 1256 RING_SPACE_TEST_WITH_RETURN(dev_priv);
1277 1257
1278 if ( sarea_priv->nbox > R128_NR_SAREA_CLIPRECTS ) 1258 if (sarea_priv->nbox > R128_NR_SAREA_CLIPRECTS)
1279 sarea_priv->nbox = R128_NR_SAREA_CLIPRECTS; 1259 sarea_priv->nbox = R128_NR_SAREA_CLIPRECTS;
1280 1260
1281 r128_cce_dispatch_clear( dev, &clear ); 1261 r128_cce_dispatch_clear(dev, &clear);
1282 COMMIT_RING(); 1262 COMMIT_RING();
1283 1263
1284 /* Make sure we restore the 3D state next time. 1264 /* Make sure we restore the 3D state next time.
@@ -1288,17 +1268,17 @@ static int r128_cce_clear( DRM_IOCTL_ARGS )
1288 return 0; 1268 return 0;
1289} 1269}
1290 1270
1291static int r128_do_init_pageflip( drm_device_t *dev ) 1271static int r128_do_init_pageflip(drm_device_t * dev)
1292{ 1272{
1293 drm_r128_private_t *dev_priv = dev->dev_private; 1273 drm_r128_private_t *dev_priv = dev->dev_private;
1294 DRM_DEBUG( "\n" ); 1274 DRM_DEBUG("\n");
1295 1275
1296 dev_priv->crtc_offset = R128_READ( R128_CRTC_OFFSET ); 1276 dev_priv->crtc_offset = R128_READ(R128_CRTC_OFFSET);
1297 dev_priv->crtc_offset_cntl = R128_READ( R128_CRTC_OFFSET_CNTL ); 1277 dev_priv->crtc_offset_cntl = R128_READ(R128_CRTC_OFFSET_CNTL);
1298 1278
1299 R128_WRITE( R128_CRTC_OFFSET, dev_priv->front_offset ); 1279 R128_WRITE(R128_CRTC_OFFSET, dev_priv->front_offset);
1300 R128_WRITE( R128_CRTC_OFFSET_CNTL, 1280 R128_WRITE(R128_CRTC_OFFSET_CNTL,
1301 dev_priv->crtc_offset_cntl | R128_CRTC_OFFSET_FLIP_CNTL ); 1281 dev_priv->crtc_offset_cntl | R128_CRTC_OFFSET_FLIP_CNTL);
1302 1282
1303 dev_priv->page_flipping = 1; 1283 dev_priv->page_flipping = 1;
1304 dev_priv->current_page = 0; 1284 dev_priv->current_page = 0;
@@ -1307,16 +1287,16 @@ static int r128_do_init_pageflip( drm_device_t *dev )
1307 return 0; 1287 return 0;
1308} 1288}
1309 1289
1310static int r128_do_cleanup_pageflip( drm_device_t *dev ) 1290static int r128_do_cleanup_pageflip(drm_device_t * dev)
1311{ 1291{
1312 drm_r128_private_t *dev_priv = dev->dev_private; 1292 drm_r128_private_t *dev_priv = dev->dev_private;
1313 DRM_DEBUG( "\n" ); 1293 DRM_DEBUG("\n");
1314 1294
1315 R128_WRITE( R128_CRTC_OFFSET, dev_priv->crtc_offset ); 1295 R128_WRITE(R128_CRTC_OFFSET, dev_priv->crtc_offset);
1316 R128_WRITE( R128_CRTC_OFFSET_CNTL, dev_priv->crtc_offset_cntl ); 1296 R128_WRITE(R128_CRTC_OFFSET_CNTL, dev_priv->crtc_offset_cntl);
1317 1297
1318 if (dev_priv->current_page != 0) { 1298 if (dev_priv->current_page != 0) {
1319 r128_cce_dispatch_flip( dev ); 1299 r128_cce_dispatch_flip(dev);
1320 COMMIT_RING(); 1300 COMMIT_RING();
1321 } 1301 }
1322 1302
@@ -1325,43 +1305,43 @@ static int r128_do_cleanup_pageflip( drm_device_t *dev )
1325} 1305}
1326 1306
1327/* Swapping and flipping are different operations, need different ioctls. 1307/* Swapping and flipping are different operations, need different ioctls.
1328 * They can & should be intermixed to support multiple 3d windows. 1308 * They can & should be intermixed to support multiple 3d windows.
1329 */ 1309 */
1330 1310
1331static int r128_cce_flip( DRM_IOCTL_ARGS ) 1311static int r128_cce_flip(DRM_IOCTL_ARGS)
1332{ 1312{
1333 DRM_DEVICE; 1313 DRM_DEVICE;
1334 drm_r128_private_t *dev_priv = dev->dev_private; 1314 drm_r128_private_t *dev_priv = dev->dev_private;
1335 DRM_DEBUG( "%s\n", __FUNCTION__ ); 1315 DRM_DEBUG("%s\n", __FUNCTION__);
1336 1316
1337 LOCK_TEST_WITH_RETURN( dev, filp ); 1317 LOCK_TEST_WITH_RETURN(dev, filp);
1338 1318
1339 RING_SPACE_TEST_WITH_RETURN( dev_priv ); 1319 RING_SPACE_TEST_WITH_RETURN(dev_priv);
1340 1320
1341 if (!dev_priv->page_flipping) 1321 if (!dev_priv->page_flipping)
1342 r128_do_init_pageflip( dev ); 1322 r128_do_init_pageflip(dev);
1343 1323
1344 r128_cce_dispatch_flip( dev ); 1324 r128_cce_dispatch_flip(dev);
1345 1325
1346 COMMIT_RING(); 1326 COMMIT_RING();
1347 return 0; 1327 return 0;
1348} 1328}
1349 1329
1350static int r128_cce_swap( DRM_IOCTL_ARGS ) 1330static int r128_cce_swap(DRM_IOCTL_ARGS)
1351{ 1331{
1352 DRM_DEVICE; 1332 DRM_DEVICE;
1353 drm_r128_private_t *dev_priv = dev->dev_private; 1333 drm_r128_private_t *dev_priv = dev->dev_private;
1354 drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; 1334 drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
1355 DRM_DEBUG( "%s\n", __FUNCTION__ ); 1335 DRM_DEBUG("%s\n", __FUNCTION__);
1356 1336
1357 LOCK_TEST_WITH_RETURN( dev, filp ); 1337 LOCK_TEST_WITH_RETURN(dev, filp);
1358 1338
1359 RING_SPACE_TEST_WITH_RETURN( dev_priv ); 1339 RING_SPACE_TEST_WITH_RETURN(dev_priv);
1360 1340
1361 if ( sarea_priv->nbox > R128_NR_SAREA_CLIPRECTS ) 1341 if (sarea_priv->nbox > R128_NR_SAREA_CLIPRECTS)
1362 sarea_priv->nbox = R128_NR_SAREA_CLIPRECTS; 1342 sarea_priv->nbox = R128_NR_SAREA_CLIPRECTS;
1363 1343
1364 r128_cce_dispatch_swap( dev ); 1344 r128_cce_dispatch_swap(dev);
1365 dev_priv->sarea_priv->dirty |= (R128_UPLOAD_CONTEXT | 1345 dev_priv->sarea_priv->dirty |= (R128_UPLOAD_CONTEXT |
1366 R128_UPLOAD_MASKS); 1346 R128_UPLOAD_MASKS);
1367 1347
@@ -1369,7 +1349,7 @@ static int r128_cce_swap( DRM_IOCTL_ARGS )
1369 return 0; 1349 return 0;
1370} 1350}
1371 1351
1372static int r128_cce_vertex( DRM_IOCTL_ARGS ) 1352static int r128_cce_vertex(DRM_IOCTL_ARGS)
1373{ 1353{
1374 DRM_DEVICE; 1354 DRM_DEVICE;
1375 drm_r128_private_t *dev_priv = dev->dev_private; 1355 drm_r128_private_t *dev_priv = dev->dev_private;
@@ -1378,44 +1358,43 @@ static int r128_cce_vertex( DRM_IOCTL_ARGS )
1378 drm_r128_buf_priv_t *buf_priv; 1358 drm_r128_buf_priv_t *buf_priv;
1379 drm_r128_vertex_t vertex; 1359 drm_r128_vertex_t vertex;
1380 1360
1381 LOCK_TEST_WITH_RETURN( dev, filp ); 1361 LOCK_TEST_WITH_RETURN(dev, filp);
1382 1362
1383 if ( !dev_priv ) { 1363 if (!dev_priv) {
1384 DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ); 1364 DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
1385 return DRM_ERR(EINVAL); 1365 return DRM_ERR(EINVAL);
1386 } 1366 }
1387 1367
1388 DRM_COPY_FROM_USER_IOCTL( vertex, (drm_r128_vertex_t __user *) data, 1368 DRM_COPY_FROM_USER_IOCTL(vertex, (drm_r128_vertex_t __user *) data,
1389 sizeof(vertex) ); 1369 sizeof(vertex));
1390 1370
1391 DRM_DEBUG( "pid=%d index=%d count=%d discard=%d\n", 1371 DRM_DEBUG("pid=%d index=%d count=%d discard=%d\n",
1392 DRM_CURRENTPID, 1372 DRM_CURRENTPID, vertex.idx, vertex.count, vertex.discard);
1393 vertex.idx, vertex.count, vertex.discard );
1394 1373
1395 if ( vertex.idx < 0 || vertex.idx >= dma->buf_count ) { 1374 if (vertex.idx < 0 || vertex.idx >= dma->buf_count) {
1396 DRM_ERROR( "buffer index %d (of %d max)\n", 1375 DRM_ERROR("buffer index %d (of %d max)\n",
1397 vertex.idx, dma->buf_count - 1 ); 1376 vertex.idx, dma->buf_count - 1);
1398 return DRM_ERR(EINVAL); 1377 return DRM_ERR(EINVAL);
1399 } 1378 }
1400 if ( vertex.prim < 0 || 1379 if (vertex.prim < 0 ||
1401 vertex.prim > R128_CCE_VC_CNTL_PRIM_TYPE_TRI_TYPE2 ) { 1380 vertex.prim > R128_CCE_VC_CNTL_PRIM_TYPE_TRI_TYPE2) {
1402 DRM_ERROR( "buffer prim %d\n", vertex.prim ); 1381 DRM_ERROR("buffer prim %d\n", vertex.prim);
1403 return DRM_ERR(EINVAL); 1382 return DRM_ERR(EINVAL);
1404 } 1383 }
1405 1384
1406 RING_SPACE_TEST_WITH_RETURN( dev_priv ); 1385 RING_SPACE_TEST_WITH_RETURN(dev_priv);
1407 VB_AGE_TEST_WITH_RETURN( dev_priv ); 1386 VB_AGE_TEST_WITH_RETURN(dev_priv);
1408 1387
1409 buf = dma->buflist[vertex.idx]; 1388 buf = dma->buflist[vertex.idx];
1410 buf_priv = buf->dev_private; 1389 buf_priv = buf->dev_private;
1411 1390
1412 if ( buf->filp != filp ) { 1391 if (buf->filp != filp) {
1413 DRM_ERROR( "process %d using buffer owned by %p\n", 1392 DRM_ERROR("process %d using buffer owned by %p\n",
1414 DRM_CURRENTPID, buf->filp ); 1393 DRM_CURRENTPID, buf->filp);
1415 return DRM_ERR(EINVAL); 1394 return DRM_ERR(EINVAL);
1416 } 1395 }
1417 if ( buf->pending ) { 1396 if (buf->pending) {
1418 DRM_ERROR( "sending pending buffer %d\n", vertex.idx ); 1397 DRM_ERROR("sending pending buffer %d\n", vertex.idx);
1419 return DRM_ERR(EINVAL); 1398 return DRM_ERR(EINVAL);
1420 } 1399 }
1421 1400
@@ -1423,13 +1402,13 @@ static int r128_cce_vertex( DRM_IOCTL_ARGS )
1423 buf_priv->prim = vertex.prim; 1402 buf_priv->prim = vertex.prim;
1424 buf_priv->discard = vertex.discard; 1403 buf_priv->discard = vertex.discard;
1425 1404
1426 r128_cce_dispatch_vertex( dev, buf ); 1405 r128_cce_dispatch_vertex(dev, buf);
1427 1406
1428 COMMIT_RING(); 1407 COMMIT_RING();
1429 return 0; 1408 return 0;
1430} 1409}
1431 1410
1432static int r128_cce_indices( DRM_IOCTL_ARGS ) 1411static int r128_cce_indices(DRM_IOCTL_ARGS)
1433{ 1412{
1434 DRM_DEVICE; 1413 DRM_DEVICE;
1435 drm_r128_private_t *dev_priv = dev->dev_private; 1414 drm_r128_private_t *dev_priv = dev->dev_private;
@@ -1439,55 +1418,54 @@ static int r128_cce_indices( DRM_IOCTL_ARGS )
1439 drm_r128_indices_t elts; 1418 drm_r128_indices_t elts;
1440 int count; 1419 int count;
1441 1420
1442 LOCK_TEST_WITH_RETURN( dev, filp ); 1421 LOCK_TEST_WITH_RETURN(dev, filp);
1443 1422
1444 if ( !dev_priv ) { 1423 if (!dev_priv) {
1445 DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ); 1424 DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
1446 return DRM_ERR(EINVAL); 1425 return DRM_ERR(EINVAL);
1447 } 1426 }
1448 1427
1449 DRM_COPY_FROM_USER_IOCTL( elts, (drm_r128_indices_t __user *) data, 1428 DRM_COPY_FROM_USER_IOCTL(elts, (drm_r128_indices_t __user *) data,
1450 sizeof(elts) ); 1429 sizeof(elts));
1451 1430
1452 DRM_DEBUG( "pid=%d buf=%d s=%d e=%d d=%d\n", DRM_CURRENTPID, 1431 DRM_DEBUG("pid=%d buf=%d s=%d e=%d d=%d\n", DRM_CURRENTPID,
1453 elts.idx, elts.start, elts.end, elts.discard ); 1432 elts.idx, elts.start, elts.end, elts.discard);
1454 1433
1455 if ( elts.idx < 0 || elts.idx >= dma->buf_count ) { 1434 if (elts.idx < 0 || elts.idx >= dma->buf_count) {
1456 DRM_ERROR( "buffer index %d (of %d max)\n", 1435 DRM_ERROR("buffer index %d (of %d max)\n",
1457 elts.idx, dma->buf_count - 1 ); 1436 elts.idx, dma->buf_count - 1);
1458 return DRM_ERR(EINVAL); 1437 return DRM_ERR(EINVAL);
1459 } 1438 }
1460 if ( elts.prim < 0 || 1439 if (elts.prim < 0 || elts.prim > R128_CCE_VC_CNTL_PRIM_TYPE_TRI_TYPE2) {
1461 elts.prim > R128_CCE_VC_CNTL_PRIM_TYPE_TRI_TYPE2 ) { 1440 DRM_ERROR("buffer prim %d\n", elts.prim);
1462 DRM_ERROR( "buffer prim %d\n", elts.prim );
1463 return DRM_ERR(EINVAL); 1441 return DRM_ERR(EINVAL);
1464 } 1442 }
1465 1443
1466 RING_SPACE_TEST_WITH_RETURN( dev_priv ); 1444 RING_SPACE_TEST_WITH_RETURN(dev_priv);
1467 VB_AGE_TEST_WITH_RETURN( dev_priv ); 1445 VB_AGE_TEST_WITH_RETURN(dev_priv);
1468 1446
1469 buf = dma->buflist[elts.idx]; 1447 buf = dma->buflist[elts.idx];
1470 buf_priv = buf->dev_private; 1448 buf_priv = buf->dev_private;
1471 1449
1472 if ( buf->filp != filp ) { 1450 if (buf->filp != filp) {
1473 DRM_ERROR( "process %d using buffer owned by %p\n", 1451 DRM_ERROR("process %d using buffer owned by %p\n",
1474 DRM_CURRENTPID, buf->filp ); 1452 DRM_CURRENTPID, buf->filp);
1475 return DRM_ERR(EINVAL); 1453 return DRM_ERR(EINVAL);
1476 } 1454 }
1477 if ( buf->pending ) { 1455 if (buf->pending) {
1478 DRM_ERROR( "sending pending buffer %d\n", elts.idx ); 1456 DRM_ERROR("sending pending buffer %d\n", elts.idx);
1479 return DRM_ERR(EINVAL); 1457 return DRM_ERR(EINVAL);
1480 } 1458 }
1481 1459
1482 count = (elts.end - elts.start) / sizeof(u16); 1460 count = (elts.end - elts.start) / sizeof(u16);
1483 elts.start -= R128_INDEX_PRIM_OFFSET; 1461 elts.start -= R128_INDEX_PRIM_OFFSET;
1484 1462
1485 if ( elts.start & 0x7 ) { 1463 if (elts.start & 0x7) {
1486 DRM_ERROR( "misaligned buffer 0x%x\n", elts.start ); 1464 DRM_ERROR("misaligned buffer 0x%x\n", elts.start);
1487 return DRM_ERR(EINVAL); 1465 return DRM_ERR(EINVAL);
1488 } 1466 }
1489 if ( elts.start < buf->used ) { 1467 if (elts.start < buf->used) {
1490 DRM_ERROR( "no header 0x%x - 0x%x\n", elts.start, buf->used ); 1468 DRM_ERROR("no header 0x%x - 0x%x\n", elts.start, buf->used);
1491 return DRM_ERR(EINVAL); 1469 return DRM_ERR(EINVAL);
1492 } 1470 }
1493 1471
@@ -1495,13 +1473,13 @@ static int r128_cce_indices( DRM_IOCTL_ARGS )
1495 buf_priv->prim = elts.prim; 1473 buf_priv->prim = elts.prim;
1496 buf_priv->discard = elts.discard; 1474 buf_priv->discard = elts.discard;
1497 1475
1498 r128_cce_dispatch_indices( dev, buf, elts.start, elts.end, count ); 1476 r128_cce_dispatch_indices(dev, buf, elts.start, elts.end, count);
1499 1477
1500 COMMIT_RING(); 1478 COMMIT_RING();
1501 return 0; 1479 return 0;
1502} 1480}
1503 1481
1504static int r128_cce_blit( DRM_IOCTL_ARGS ) 1482static int r128_cce_blit(DRM_IOCTL_ARGS)
1505{ 1483{
1506 DRM_DEVICE; 1484 DRM_DEVICE;
1507 drm_device_dma_t *dma = dev->dma; 1485 drm_device_dma_t *dma = dev->dma;
@@ -1509,55 +1487,55 @@ static int r128_cce_blit( DRM_IOCTL_ARGS )
1509 drm_r128_blit_t blit; 1487 drm_r128_blit_t blit;
1510 int ret; 1488 int ret;
1511 1489
1512 LOCK_TEST_WITH_RETURN( dev, filp ); 1490 LOCK_TEST_WITH_RETURN(dev, filp);
1513 1491
1514 DRM_COPY_FROM_USER_IOCTL( blit, (drm_r128_blit_t __user *) data, 1492 DRM_COPY_FROM_USER_IOCTL(blit, (drm_r128_blit_t __user *) data,
1515 sizeof(blit) ); 1493 sizeof(blit));
1516 1494
1517 DRM_DEBUG( "pid=%d index=%d\n", DRM_CURRENTPID, blit.idx ); 1495 DRM_DEBUG("pid=%d index=%d\n", DRM_CURRENTPID, blit.idx);
1518 1496
1519 if ( blit.idx < 0 || blit.idx >= dma->buf_count ) { 1497 if (blit.idx < 0 || blit.idx >= dma->buf_count) {
1520 DRM_ERROR( "buffer index %d (of %d max)\n", 1498 DRM_ERROR("buffer index %d (of %d max)\n",
1521 blit.idx, dma->buf_count - 1 ); 1499 blit.idx, dma->buf_count - 1);
1522 return DRM_ERR(EINVAL); 1500 return DRM_ERR(EINVAL);
1523 } 1501 }
1524 1502
1525 RING_SPACE_TEST_WITH_RETURN( dev_priv ); 1503 RING_SPACE_TEST_WITH_RETURN(dev_priv);
1526 VB_AGE_TEST_WITH_RETURN( dev_priv ); 1504 VB_AGE_TEST_WITH_RETURN(dev_priv);
1527 1505
1528 ret = r128_cce_dispatch_blit( filp, dev, &blit ); 1506 ret = r128_cce_dispatch_blit(filp, dev, &blit);
1529 1507
1530 COMMIT_RING(); 1508 COMMIT_RING();
1531 return ret; 1509 return ret;
1532} 1510}
1533 1511
1534static int r128_cce_depth( DRM_IOCTL_ARGS ) 1512static int r128_cce_depth(DRM_IOCTL_ARGS)
1535{ 1513{
1536 DRM_DEVICE; 1514 DRM_DEVICE;
1537 drm_r128_private_t *dev_priv = dev->dev_private; 1515 drm_r128_private_t *dev_priv = dev->dev_private;
1538 drm_r128_depth_t depth; 1516 drm_r128_depth_t depth;
1539 int ret; 1517 int ret;
1540 1518
1541 LOCK_TEST_WITH_RETURN( dev, filp ); 1519 LOCK_TEST_WITH_RETURN(dev, filp);
1542 1520
1543 DRM_COPY_FROM_USER_IOCTL( depth, (drm_r128_depth_t __user *) data, 1521 DRM_COPY_FROM_USER_IOCTL(depth, (drm_r128_depth_t __user *) data,
1544 sizeof(depth) ); 1522 sizeof(depth));
1545 1523
1546 RING_SPACE_TEST_WITH_RETURN( dev_priv ); 1524 RING_SPACE_TEST_WITH_RETURN(dev_priv);
1547 1525
1548 ret = DRM_ERR(EINVAL); 1526 ret = DRM_ERR(EINVAL);
1549 switch ( depth.func ) { 1527 switch (depth.func) {
1550 case R128_WRITE_SPAN: 1528 case R128_WRITE_SPAN:
1551 ret = r128_cce_dispatch_write_span( dev, &depth ); 1529 ret = r128_cce_dispatch_write_span(dev, &depth);
1552 break; 1530 break;
1553 case R128_WRITE_PIXELS: 1531 case R128_WRITE_PIXELS:
1554 ret = r128_cce_dispatch_write_pixels( dev, &depth ); 1532 ret = r128_cce_dispatch_write_pixels(dev, &depth);
1555 break; 1533 break;
1556 case R128_READ_SPAN: 1534 case R128_READ_SPAN:
1557 ret = r128_cce_dispatch_read_span( dev, &depth ); 1535 ret = r128_cce_dispatch_read_span(dev, &depth);
1558 break; 1536 break;
1559 case R128_READ_PIXELS: 1537 case R128_READ_PIXELS:
1560 ret = r128_cce_dispatch_read_pixels( dev, &depth ); 1538 ret = r128_cce_dispatch_read_pixels(dev, &depth);
1561 break; 1539 break;
1562 } 1540 }
1563 1541
@@ -1565,31 +1543,30 @@ static int r128_cce_depth( DRM_IOCTL_ARGS )
1565 return ret; 1543 return ret;
1566} 1544}
1567 1545
1568static int r128_cce_stipple( DRM_IOCTL_ARGS ) 1546static int r128_cce_stipple(DRM_IOCTL_ARGS)
1569{ 1547{
1570 DRM_DEVICE; 1548 DRM_DEVICE;
1571 drm_r128_private_t *dev_priv = dev->dev_private; 1549 drm_r128_private_t *dev_priv = dev->dev_private;
1572 drm_r128_stipple_t stipple; 1550 drm_r128_stipple_t stipple;
1573 u32 mask[32]; 1551 u32 mask[32];
1574 1552
1575 LOCK_TEST_WITH_RETURN( dev, filp ); 1553 LOCK_TEST_WITH_RETURN(dev, filp);
1576 1554
1577 DRM_COPY_FROM_USER_IOCTL( stipple, (drm_r128_stipple_t __user *) data, 1555 DRM_COPY_FROM_USER_IOCTL(stipple, (drm_r128_stipple_t __user *) data,
1578 sizeof(stipple) ); 1556 sizeof(stipple));
1579 1557
1580 if ( DRM_COPY_FROM_USER( &mask, stipple.mask, 1558 if (DRM_COPY_FROM_USER(&mask, stipple.mask, 32 * sizeof(u32)))
1581 32 * sizeof(u32) ) ) 1559 return DRM_ERR(EFAULT);
1582 return DRM_ERR( EFAULT );
1583 1560
1584 RING_SPACE_TEST_WITH_RETURN( dev_priv ); 1561 RING_SPACE_TEST_WITH_RETURN(dev_priv);
1585 1562
1586 r128_cce_dispatch_stipple( dev, mask ); 1563 r128_cce_dispatch_stipple(dev, mask);
1587 1564
1588 COMMIT_RING(); 1565 COMMIT_RING();
1589 return 0; 1566 return 0;
1590} 1567}
1591 1568
1592static int r128_cce_indirect( DRM_IOCTL_ARGS ) 1569static int r128_cce_indirect(DRM_IOCTL_ARGS)
1593{ 1570{
1594 DRM_DEVICE; 1571 DRM_DEVICE;
1595 drm_r128_private_t *dev_priv = dev->dev_private; 1572 drm_r128_private_t *dev_priv = dev->dev_private;
@@ -1601,47 +1578,46 @@ static int r128_cce_indirect( DRM_IOCTL_ARGS )
1601 RING_LOCALS; 1578 RING_LOCALS;
1602#endif 1579#endif
1603 1580
1604 LOCK_TEST_WITH_RETURN( dev, filp ); 1581 LOCK_TEST_WITH_RETURN(dev, filp);
1605 1582
1606 if ( !dev_priv ) { 1583 if (!dev_priv) {
1607 DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ); 1584 DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
1608 return DRM_ERR(EINVAL); 1585 return DRM_ERR(EINVAL);
1609 } 1586 }
1610 1587
1611 DRM_COPY_FROM_USER_IOCTL( indirect, (drm_r128_indirect_t __user *) data, 1588 DRM_COPY_FROM_USER_IOCTL(indirect, (drm_r128_indirect_t __user *) data,
1612 sizeof(indirect) ); 1589 sizeof(indirect));
1613 1590
1614 DRM_DEBUG( "indirect: idx=%d s=%d e=%d d=%d\n", 1591 DRM_DEBUG("indirect: idx=%d s=%d e=%d d=%d\n",
1615 indirect.idx, indirect.start, 1592 indirect.idx, indirect.start, indirect.end, indirect.discard);
1616 indirect.end, indirect.discard );
1617 1593
1618 if ( indirect.idx < 0 || indirect.idx >= dma->buf_count ) { 1594 if (indirect.idx < 0 || indirect.idx >= dma->buf_count) {
1619 DRM_ERROR( "buffer index %d (of %d max)\n", 1595 DRM_ERROR("buffer index %d (of %d max)\n",
1620 indirect.idx, dma->buf_count - 1 ); 1596 indirect.idx, dma->buf_count - 1);
1621 return DRM_ERR(EINVAL); 1597 return DRM_ERR(EINVAL);
1622 } 1598 }
1623 1599
1624 buf = dma->buflist[indirect.idx]; 1600 buf = dma->buflist[indirect.idx];
1625 buf_priv = buf->dev_private; 1601 buf_priv = buf->dev_private;
1626 1602
1627 if ( buf->filp != filp ) { 1603 if (buf->filp != filp) {
1628 DRM_ERROR( "process %d using buffer owned by %p\n", 1604 DRM_ERROR("process %d using buffer owned by %p\n",
1629 DRM_CURRENTPID, buf->filp ); 1605 DRM_CURRENTPID, buf->filp);
1630 return DRM_ERR(EINVAL); 1606 return DRM_ERR(EINVAL);
1631 } 1607 }
1632 if ( buf->pending ) { 1608 if (buf->pending) {
1633 DRM_ERROR( "sending pending buffer %d\n", indirect.idx ); 1609 DRM_ERROR("sending pending buffer %d\n", indirect.idx);
1634 return DRM_ERR(EINVAL); 1610 return DRM_ERR(EINVAL);
1635 } 1611 }
1636 1612
1637 if ( indirect.start < buf->used ) { 1613 if (indirect.start < buf->used) {
1638 DRM_ERROR( "reusing indirect: start=0x%x actual=0x%x\n", 1614 DRM_ERROR("reusing indirect: start=0x%x actual=0x%x\n",
1639 indirect.start, buf->used ); 1615 indirect.start, buf->used);
1640 return DRM_ERR(EINVAL); 1616 return DRM_ERR(EINVAL);
1641 } 1617 }
1642 1618
1643 RING_SPACE_TEST_WITH_RETURN( dev_priv ); 1619 RING_SPACE_TEST_WITH_RETURN(dev_priv);
1644 VB_AGE_TEST_WITH_RETURN( dev_priv ); 1620 VB_AGE_TEST_WITH_RETURN(dev_priv);
1645 1621
1646 buf->used = indirect.end; 1622 buf->used = indirect.end;
1647 buf_priv->discard = indirect.discard; 1623 buf_priv->discard = indirect.discard;
@@ -1650,7 +1626,7 @@ static int r128_cce_indirect( DRM_IOCTL_ARGS )
1650 /* Wait for the 3D stream to idle before the indirect buffer 1626 /* Wait for the 3D stream to idle before the indirect buffer
1651 * containing 2D acceleration commands is processed. 1627 * containing 2D acceleration commands is processed.
1652 */ 1628 */
1653 BEGIN_RING( 2 ); 1629 BEGIN_RING(2);
1654 RADEON_WAIT_UNTIL_3D_IDLE(); 1630 RADEON_WAIT_UNTIL_3D_IDLE();
1655 ADVANCE_RING(); 1631 ADVANCE_RING();
1656#endif 1632#endif
@@ -1659,30 +1635,30 @@ static int r128_cce_indirect( DRM_IOCTL_ARGS )
1659 * X server. This is insecure and is thus only available to 1635 * X server. This is insecure and is thus only available to
1660 * privileged clients. 1636 * privileged clients.
1661 */ 1637 */
1662 r128_cce_dispatch_indirect( dev, buf, indirect.start, indirect.end ); 1638 r128_cce_dispatch_indirect(dev, buf, indirect.start, indirect.end);
1663 1639
1664 COMMIT_RING(); 1640 COMMIT_RING();
1665 return 0; 1641 return 0;
1666} 1642}
1667 1643
1668static int r128_getparam( DRM_IOCTL_ARGS ) 1644static int r128_getparam(DRM_IOCTL_ARGS)
1669{ 1645{
1670 DRM_DEVICE; 1646 DRM_DEVICE;
1671 drm_r128_private_t *dev_priv = dev->dev_private; 1647 drm_r128_private_t *dev_priv = dev->dev_private;
1672 drm_r128_getparam_t param; 1648 drm_r128_getparam_t param;
1673 int value; 1649 int value;
1674 1650
1675 if ( !dev_priv ) { 1651 if (!dev_priv) {
1676 DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ); 1652 DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
1677 return DRM_ERR(EINVAL); 1653 return DRM_ERR(EINVAL);
1678 } 1654 }
1679 1655
1680 DRM_COPY_FROM_USER_IOCTL( param, (drm_r128_getparam_t __user *)data, 1656 DRM_COPY_FROM_USER_IOCTL(param, (drm_r128_getparam_t __user *) data,
1681 sizeof(param) ); 1657 sizeof(param));
1682 1658
1683 DRM_DEBUG( "pid=%d\n", DRM_CURRENTPID ); 1659 DRM_DEBUG("pid=%d\n", DRM_CURRENTPID);
1684 1660
1685 switch( param.param ) { 1661 switch (param.param) {
1686 case R128_PARAM_IRQ_NR: 1662 case R128_PARAM_IRQ_NR:
1687 value = dev->irq; 1663 value = dev->irq;
1688 break; 1664 break;
@@ -1690,47 +1666,47 @@ static int r128_getparam( DRM_IOCTL_ARGS )
1690 return DRM_ERR(EINVAL); 1666 return DRM_ERR(EINVAL);
1691 } 1667 }
1692 1668
1693 if ( DRM_COPY_TO_USER( param.value, &value, sizeof(int) ) ) { 1669 if (DRM_COPY_TO_USER(param.value, &value, sizeof(int))) {
1694 DRM_ERROR( "copy_to_user\n" ); 1670 DRM_ERROR("copy_to_user\n");
1695 return DRM_ERR(EFAULT); 1671 return DRM_ERR(EFAULT);
1696 } 1672 }
1697 1673
1698 return 0; 1674 return 0;
1699} 1675}
1700 1676
1701void r128_driver_prerelease(drm_device_t *dev, DRMFILE filp) 1677void r128_driver_prerelease(drm_device_t * dev, DRMFILE filp)
1702{ 1678{
1703 if ( dev->dev_private ) { 1679 if (dev->dev_private) {
1704 drm_r128_private_t *dev_priv = dev->dev_private; 1680 drm_r128_private_t *dev_priv = dev->dev_private;
1705 if ( dev_priv->page_flipping ) { 1681 if (dev_priv->page_flipping) {
1706 r128_do_cleanup_pageflip( dev ); 1682 r128_do_cleanup_pageflip(dev);
1707 } 1683 }
1708 } 1684 }
1709} 1685}
1710 1686
1711void r128_driver_pretakedown(drm_device_t *dev) 1687void r128_driver_pretakedown(drm_device_t * dev)
1712{ 1688{
1713 r128_do_cleanup_cce( dev ); 1689 r128_do_cleanup_cce(dev);
1714} 1690}
1715 1691
1716drm_ioctl_desc_t r128_ioctls[] = { 1692drm_ioctl_desc_t r128_ioctls[] = {
1717 [DRM_IOCTL_NR(DRM_R128_INIT)] = { r128_cce_init, 1, 1 }, 1693 [DRM_IOCTL_NR(DRM_R128_INIT)] = {r128_cce_init, 1, 1},
1718 [DRM_IOCTL_NR(DRM_R128_CCE_START)] = { r128_cce_start, 1, 1 }, 1694 [DRM_IOCTL_NR(DRM_R128_CCE_START)] = {r128_cce_start, 1, 1},
1719 [DRM_IOCTL_NR(DRM_R128_CCE_STOP)] = { r128_cce_stop, 1, 1 }, 1695 [DRM_IOCTL_NR(DRM_R128_CCE_STOP)] = {r128_cce_stop, 1, 1},
1720 [DRM_IOCTL_NR(DRM_R128_CCE_RESET)] = { r128_cce_reset, 1, 1 }, 1696 [DRM_IOCTL_NR(DRM_R128_CCE_RESET)] = {r128_cce_reset, 1, 1},
1721 [DRM_IOCTL_NR(DRM_R128_CCE_IDLE)] = { r128_cce_idle, 1, 0 }, 1697 [DRM_IOCTL_NR(DRM_R128_CCE_IDLE)] = {r128_cce_idle, 1, 0},
1722 [DRM_IOCTL_NR(DRM_R128_RESET)] = { r128_engine_reset, 1, 0 }, 1698 [DRM_IOCTL_NR(DRM_R128_RESET)] = {r128_engine_reset, 1, 0},
1723 [DRM_IOCTL_NR(DRM_R128_FULLSCREEN)] = { r128_fullscreen, 1, 0 }, 1699 [DRM_IOCTL_NR(DRM_R128_FULLSCREEN)] = {r128_fullscreen, 1, 0},
1724 [DRM_IOCTL_NR(DRM_R128_SWAP)] = { r128_cce_swap, 1, 0 }, 1700 [DRM_IOCTL_NR(DRM_R128_SWAP)] = {r128_cce_swap, 1, 0},
1725 [DRM_IOCTL_NR(DRM_R128_FLIP)] = { r128_cce_flip, 1, 0 }, 1701 [DRM_IOCTL_NR(DRM_R128_FLIP)] = {r128_cce_flip, 1, 0},
1726 [DRM_IOCTL_NR(DRM_R128_CLEAR)] = { r128_cce_clear, 1, 0 }, 1702 [DRM_IOCTL_NR(DRM_R128_CLEAR)] = {r128_cce_clear, 1, 0},
1727 [DRM_IOCTL_NR(DRM_R128_VERTEX)] = { r128_cce_vertex, 1, 0 }, 1703 [DRM_IOCTL_NR(DRM_R128_VERTEX)] = {r128_cce_vertex, 1, 0},
1728 [DRM_IOCTL_NR(DRM_R128_INDICES)] = { r128_cce_indices, 1, 0 }, 1704 [DRM_IOCTL_NR(DRM_R128_INDICES)] = {r128_cce_indices, 1, 0},
1729 [DRM_IOCTL_NR(DRM_R128_BLIT)] = { r128_cce_blit, 1, 0 }, 1705 [DRM_IOCTL_NR(DRM_R128_BLIT)] = {r128_cce_blit, 1, 0},
1730 [DRM_IOCTL_NR(DRM_R128_DEPTH)] = { r128_cce_depth, 1, 0 }, 1706 [DRM_IOCTL_NR(DRM_R128_DEPTH)] = {r128_cce_depth, 1, 0},
1731 [DRM_IOCTL_NR(DRM_R128_STIPPLE)] = { r128_cce_stipple, 1, 0 }, 1707 [DRM_IOCTL_NR(DRM_R128_STIPPLE)] = {r128_cce_stipple, 1, 0},
1732 [DRM_IOCTL_NR(DRM_R128_INDIRECT)] = { r128_cce_indirect, 1, 1 }, 1708 [DRM_IOCTL_NR(DRM_R128_INDIRECT)] = {r128_cce_indirect, 1, 1},
1733 [DRM_IOCTL_NR(DRM_R128_GETPARAM)] = { r128_getparam, 1, 0 }, 1709 [DRM_IOCTL_NR(DRM_R128_GETPARAM)] = {r128_getparam, 1, 0},
1734}; 1710};
1735 1711
1736int r128_max_ioctl = DRM_ARRAY_SIZE(r128_ioctls); 1712int r128_max_ioctl = DRM_ARRAY_SIZE(r128_ioctls);
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-20 10:26:56 -0400