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authorDave Airlie <airlied@redhat.com>2008-05-28 20:09:59 -0400
committerDave Airlie <airlied@redhat.com>2008-07-13 20:45:01 -0400
commitc0e09200dc0813972442e550a5905a132768e56c (patch)
treed38e635a30ff8b0a2b98b9d7f97cab1501f8209e /drivers/char/drm/r128_drv.h
parentbce7f793daec3e65ec5c5705d2457b81fe7b5725 (diff)
drm: reorganise drm tree to be more future proof.
With the coming of kernel based modesetting and the memory manager stuff, the everything in one directory approach was getting very ugly and starting to be unmanageable. This restructures the drm along the lines of other kernel components. It creates a drivers/gpu/drm directory and moves the hw drivers into subdirectores. It moves the includes into an include/drm, and sets up the unifdef for the userspace headers we should be exporting. Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/char/drm/r128_drv.h')
-rw-r--r--drivers/char/drm/r128_drv.h522
1 files changed, 0 insertions, 522 deletions
diff --git a/drivers/char/drm/r128_drv.h b/drivers/char/drm/r128_drv.h
deleted file mode 100644
index 011105e51ac6..000000000000
--- a/drivers/char/drm/r128_drv.h
+++ /dev/null
@@ -1,522 +0,0 @@
1/* r128_drv.h -- Private header for r128 driver -*- linux-c -*-
2 * Created: Mon Dec 13 09:51:11 1999 by faith@precisioninsight.com
3 */
4/*
5 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
6 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
7 * All rights reserved.
8 *
9 * Permission is hereby granted, free of charge, to any person obtaining a
10 * copy of this software and associated documentation files (the "Software"),
11 * to deal in the Software without restriction, including without limitation
12 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
13 * and/or sell copies of the Software, and to permit persons to whom the
14 * Software is furnished to do so, subject to the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the next
17 * paragraph) shall be included in all copies or substantial portions of the
18 * Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
21 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
23 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
24 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
25 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
26 * DEALINGS IN THE SOFTWARE.
27 *
28 * Authors:
29 * Rickard E. (Rik) Faith <faith@valinux.com>
30 * Kevin E. Martin <martin@valinux.com>
31 * Gareth Hughes <gareth@valinux.com>
32 * Michel Dänzer <daenzerm@student.ethz.ch>
33 */
34
35#ifndef __R128_DRV_H__
36#define __R128_DRV_H__
37
38/* General customization:
39 */
40#define DRIVER_AUTHOR "Gareth Hughes, VA Linux Systems Inc."
41
42#define DRIVER_NAME "r128"
43#define DRIVER_DESC "ATI Rage 128"
44#define DRIVER_DATE "20030725"
45
46/* Interface history:
47 *
48 * ?? - ??
49 * 2.4 - Add support for ycbcr textures (no new ioctls)
50 * 2.5 - Add FLIP ioctl, disable FULLSCREEN.
51 */
52#define DRIVER_MAJOR 2
53#define DRIVER_MINOR 5
54#define DRIVER_PATCHLEVEL 0
55
56#define GET_RING_HEAD(dev_priv) R128_READ( R128_PM4_BUFFER_DL_RPTR )
57
58typedef struct drm_r128_freelist {
59 unsigned int age;
60 struct drm_buf *buf;
61 struct drm_r128_freelist *next;
62 struct drm_r128_freelist *prev;
63} drm_r128_freelist_t;
64
65typedef struct drm_r128_ring_buffer {
66 u32 *start;
67 u32 *end;
68 int size;
69 int size_l2qw;
70
71 u32 tail;
72 u32 tail_mask;
73 int space;
74
75 int high_mark;
76} drm_r128_ring_buffer_t;
77
78typedef struct drm_r128_private {
79 drm_r128_ring_buffer_t ring;
80 drm_r128_sarea_t *sarea_priv;
81
82 int cce_mode;
83 int cce_fifo_size;
84 int cce_running;
85
86 drm_r128_freelist_t *head;
87 drm_r128_freelist_t *tail;
88
89 int usec_timeout;
90 int is_pci;
91 unsigned long cce_buffers_offset;
92
93 atomic_t idle_count;
94
95 int page_flipping;
96 int current_page;
97 u32 crtc_offset;
98 u32 crtc_offset_cntl;
99
100 u32 color_fmt;
101 unsigned int front_offset;
102 unsigned int front_pitch;
103 unsigned int back_offset;
104 unsigned int back_pitch;
105
106 u32 depth_fmt;
107 unsigned int depth_offset;
108 unsigned int depth_pitch;
109 unsigned int span_offset;
110
111 u32 front_pitch_offset_c;
112 u32 back_pitch_offset_c;
113 u32 depth_pitch_offset_c;
114 u32 span_pitch_offset_c;
115
116 drm_local_map_t *sarea;
117 drm_local_map_t *mmio;
118 drm_local_map_t *cce_ring;
119 drm_local_map_t *ring_rptr;
120 drm_local_map_t *agp_textures;
121 struct drm_ati_pcigart_info gart_info;
122} drm_r128_private_t;
123
124typedef struct drm_r128_buf_priv {
125 u32 age;
126 int prim;
127 int discard;
128 int dispatched;
129 drm_r128_freelist_t *list_entry;
130} drm_r128_buf_priv_t;
131
132extern struct drm_ioctl_desc r128_ioctls[];
133extern int r128_max_ioctl;
134
135 /* r128_cce.c */
136extern int r128_cce_init(struct drm_device *dev, void *data, struct drm_file *file_priv);
137extern int r128_cce_start(struct drm_device *dev, void *data, struct drm_file *file_priv);
138extern int r128_cce_stop(struct drm_device *dev, void *data, struct drm_file *file_priv);
139extern int r128_cce_reset(struct drm_device *dev, void *data, struct drm_file *file_priv);
140extern int r128_cce_idle(struct drm_device *dev, void *data, struct drm_file *file_priv);
141extern int r128_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_priv);
142extern int r128_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv);
143extern int r128_cce_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv);
144
145extern void r128_freelist_reset(struct drm_device * dev);
146
147extern int r128_wait_ring(drm_r128_private_t * dev_priv, int n);
148
149extern int r128_do_cce_idle(drm_r128_private_t * dev_priv);
150extern int r128_do_cleanup_cce(struct drm_device * dev);
151
152extern int r128_driver_vblank_wait(struct drm_device * dev, unsigned int *sequence);
153
154extern irqreturn_t r128_driver_irq_handler(DRM_IRQ_ARGS);
155extern void r128_driver_irq_preinstall(struct drm_device * dev);
156extern void r128_driver_irq_postinstall(struct drm_device * dev);
157extern void r128_driver_irq_uninstall(struct drm_device * dev);
158extern void r128_driver_lastclose(struct drm_device * dev);
159extern void r128_driver_preclose(struct drm_device * dev,
160 struct drm_file *file_priv);
161
162extern long r128_compat_ioctl(struct file *filp, unsigned int cmd,
163 unsigned long arg);
164
165/* Register definitions, register access macros and drmAddMap constants
166 * for Rage 128 kernel driver.
167 */
168
169#define R128_AUX_SC_CNTL 0x1660
170# define R128_AUX1_SC_EN (1 << 0)
171# define R128_AUX1_SC_MODE_OR (0 << 1)
172# define R128_AUX1_SC_MODE_NAND (1 << 1)
173# define R128_AUX2_SC_EN (1 << 2)
174# define R128_AUX2_SC_MODE_OR (0 << 3)
175# define R128_AUX2_SC_MODE_NAND (1 << 3)
176# define R128_AUX3_SC_EN (1 << 4)
177# define R128_AUX3_SC_MODE_OR (0 << 5)
178# define R128_AUX3_SC_MODE_NAND (1 << 5)
179#define R128_AUX1_SC_LEFT 0x1664
180#define R128_AUX1_SC_RIGHT 0x1668
181#define R128_AUX1_SC_TOP 0x166c
182#define R128_AUX1_SC_BOTTOM 0x1670
183#define R128_AUX2_SC_LEFT 0x1674
184#define R128_AUX2_SC_RIGHT 0x1678
185#define R128_AUX2_SC_TOP 0x167c
186#define R128_AUX2_SC_BOTTOM 0x1680
187#define R128_AUX3_SC_LEFT 0x1684
188#define R128_AUX3_SC_RIGHT 0x1688
189#define R128_AUX3_SC_TOP 0x168c
190#define R128_AUX3_SC_BOTTOM 0x1690
191
192#define R128_BRUSH_DATA0 0x1480
193#define R128_BUS_CNTL 0x0030
194# define R128_BUS_MASTER_DIS (1 << 6)
195
196#define R128_CLOCK_CNTL_INDEX 0x0008
197#define R128_CLOCK_CNTL_DATA 0x000c
198# define R128_PLL_WR_EN (1 << 7)
199#define R128_CONSTANT_COLOR_C 0x1d34
200#define R128_CRTC_OFFSET 0x0224
201#define R128_CRTC_OFFSET_CNTL 0x0228
202# define R128_CRTC_OFFSET_FLIP_CNTL (1 << 16)
203
204#define R128_DP_GUI_MASTER_CNTL 0x146c
205# define R128_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0)
206# define R128_GMC_DST_PITCH_OFFSET_CNTL (1 << 1)
207# define R128_GMC_BRUSH_SOLID_COLOR (13 << 4)
208# define R128_GMC_BRUSH_NONE (15 << 4)
209# define R128_GMC_DST_16BPP (4 << 8)
210# define R128_GMC_DST_24BPP (5 << 8)
211# define R128_GMC_DST_32BPP (6 << 8)
212# define R128_GMC_DST_DATATYPE_SHIFT 8
213# define R128_GMC_SRC_DATATYPE_COLOR (3 << 12)
214# define R128_DP_SRC_SOURCE_MEMORY (2 << 24)
215# define R128_DP_SRC_SOURCE_HOST_DATA (3 << 24)
216# define R128_GMC_CLR_CMP_CNTL_DIS (1 << 28)
217# define R128_GMC_AUX_CLIP_DIS (1 << 29)
218# define R128_GMC_WR_MSK_DIS (1 << 30)
219# define R128_ROP3_S 0x00cc0000
220# define R128_ROP3_P 0x00f00000
221#define R128_DP_WRITE_MASK 0x16cc
222#define R128_DST_PITCH_OFFSET_C 0x1c80
223# define R128_DST_TILE (1 << 31)
224
225#define R128_GEN_INT_CNTL 0x0040
226# define R128_CRTC_VBLANK_INT_EN (1 << 0)
227#define R128_GEN_INT_STATUS 0x0044
228# define R128_CRTC_VBLANK_INT (1 << 0)
229# define R128_CRTC_VBLANK_INT_AK (1 << 0)
230#define R128_GEN_RESET_CNTL 0x00f0
231# define R128_SOFT_RESET_GUI (1 << 0)
232
233#define R128_GUI_SCRATCH_REG0 0x15e0
234#define R128_GUI_SCRATCH_REG1 0x15e4
235#define R128_GUI_SCRATCH_REG2 0x15e8
236#define R128_GUI_SCRATCH_REG3 0x15ec
237#define R128_GUI_SCRATCH_REG4 0x15f0
238#define R128_GUI_SCRATCH_REG5 0x15f4
239
240#define R128_GUI_STAT 0x1740
241# define R128_GUI_FIFOCNT_MASK 0x0fff
242# define R128_GUI_ACTIVE (1 << 31)
243
244#define R128_MCLK_CNTL 0x000f
245# define R128_FORCE_GCP (1 << 16)
246# define R128_FORCE_PIPE3D_CP (1 << 17)
247# define R128_FORCE_RCP (1 << 18)
248
249#define R128_PC_GUI_CTLSTAT 0x1748
250#define R128_PC_NGUI_CTLSTAT 0x0184
251# define R128_PC_FLUSH_GUI (3 << 0)
252# define R128_PC_RI_GUI (1 << 2)
253# define R128_PC_FLUSH_ALL 0x00ff
254# define R128_PC_BUSY (1 << 31)
255
256#define R128_PCI_GART_PAGE 0x017c
257#define R128_PRIM_TEX_CNTL_C 0x1cb0
258
259#define R128_SCALE_3D_CNTL 0x1a00
260#define R128_SEC_TEX_CNTL_C 0x1d00
261#define R128_SEC_TEXTURE_BORDER_COLOR_C 0x1d3c
262#define R128_SETUP_CNTL 0x1bc4
263#define R128_STEN_REF_MASK_C 0x1d40
264
265#define R128_TEX_CNTL_C 0x1c9c
266# define R128_TEX_CACHE_FLUSH (1 << 23)
267
268#define R128_WAIT_UNTIL 0x1720
269# define R128_EVENT_CRTC_OFFSET (1 << 0)
270#define R128_WINDOW_XY_OFFSET 0x1bcc
271
272/* CCE registers
273 */
274#define R128_PM4_BUFFER_OFFSET 0x0700
275#define R128_PM4_BUFFER_CNTL 0x0704
276# define R128_PM4_MASK (15 << 28)
277# define R128_PM4_NONPM4 (0 << 28)
278# define R128_PM4_192PIO (1 << 28)
279# define R128_PM4_192BM (2 << 28)
280# define R128_PM4_128PIO_64INDBM (3 << 28)
281# define R128_PM4_128BM_64INDBM (4 << 28)
282# define R128_PM4_64PIO_128INDBM (5 << 28)
283# define R128_PM4_64BM_128INDBM (6 << 28)
284# define R128_PM4_64PIO_64VCBM_64INDBM (7 << 28)
285# define R128_PM4_64BM_64VCBM_64INDBM (8 << 28)
286# define R128_PM4_64PIO_64VCPIO_64INDPIO (15 << 28)
287# define R128_PM4_BUFFER_CNTL_NOUPDATE (1 << 27)
288
289#define R128_PM4_BUFFER_WM_CNTL 0x0708
290# define R128_WMA_SHIFT 0
291# define R128_WMB_SHIFT 8
292# define R128_WMC_SHIFT 16
293# define R128_WB_WM_SHIFT 24
294
295#define R128_PM4_BUFFER_DL_RPTR_ADDR 0x070c
296#define R128_PM4_BUFFER_DL_RPTR 0x0710
297#define R128_PM4_BUFFER_DL_WPTR 0x0714
298# define R128_PM4_BUFFER_DL_DONE (1 << 31)
299
300#define R128_PM4_VC_FPU_SETUP 0x071c
301
302#define R128_PM4_IW_INDOFF 0x0738
303#define R128_PM4_IW_INDSIZE 0x073c
304
305#define R128_PM4_STAT 0x07b8
306# define R128_PM4_FIFOCNT_MASK 0x0fff
307# define R128_PM4_BUSY (1 << 16)
308# define R128_PM4_GUI_ACTIVE (1 << 31)
309
310#define R128_PM4_MICROCODE_ADDR 0x07d4
311#define R128_PM4_MICROCODE_RADDR 0x07d8
312#define R128_PM4_MICROCODE_DATAH 0x07dc
313#define R128_PM4_MICROCODE_DATAL 0x07e0
314
315#define R128_PM4_BUFFER_ADDR 0x07f0
316#define R128_PM4_MICRO_CNTL 0x07fc
317# define R128_PM4_MICRO_FREERUN (1 << 30)
318
319#define R128_PM4_FIFO_DATA_EVEN 0x1000
320#define R128_PM4_FIFO_DATA_ODD 0x1004
321
322/* CCE command packets
323 */
324#define R128_CCE_PACKET0 0x00000000
325#define R128_CCE_PACKET1 0x40000000
326#define R128_CCE_PACKET2 0x80000000
327#define R128_CCE_PACKET3 0xC0000000
328# define R128_CNTL_HOSTDATA_BLT 0x00009400
329# define R128_CNTL_PAINT_MULTI 0x00009A00
330# define R128_CNTL_BITBLT_MULTI 0x00009B00
331# define R128_3D_RNDR_GEN_INDX_PRIM 0x00002300
332
333#define R128_CCE_PACKET_MASK 0xC0000000
334#define R128_CCE_PACKET_COUNT_MASK 0x3fff0000
335#define R128_CCE_PACKET0_REG_MASK 0x000007ff
336#define R128_CCE_PACKET1_REG0_MASK 0x000007ff
337#define R128_CCE_PACKET1_REG1_MASK 0x003ff800
338
339#define R128_CCE_VC_CNTL_PRIM_TYPE_NONE 0x00000000
340#define R128_CCE_VC_CNTL_PRIM_TYPE_POINT 0x00000001
341#define R128_CCE_VC_CNTL_PRIM_TYPE_LINE 0x00000002
342#define R128_CCE_VC_CNTL_PRIM_TYPE_POLY_LINE 0x00000003
343#define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_LIST 0x00000004
344#define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_FAN 0x00000005
345#define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_STRIP 0x00000006
346#define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_TYPE2 0x00000007
347#define R128_CCE_VC_CNTL_PRIM_WALK_IND 0x00000010
348#define R128_CCE_VC_CNTL_PRIM_WALK_LIST 0x00000020
349#define R128_CCE_VC_CNTL_PRIM_WALK_RING 0x00000030
350#define R128_CCE_VC_CNTL_NUM_SHIFT 16
351
352#define R128_DATATYPE_VQ 0
353#define R128_DATATYPE_CI4 1
354#define R128_DATATYPE_CI8 2
355#define R128_DATATYPE_ARGB1555 3
356#define R128_DATATYPE_RGB565 4
357#define R128_DATATYPE_RGB888 5
358#define R128_DATATYPE_ARGB8888 6
359#define R128_DATATYPE_RGB332 7
360#define R128_DATATYPE_Y8 8
361#define R128_DATATYPE_RGB8 9
362#define R128_DATATYPE_CI16 10
363#define R128_DATATYPE_YVYU422 11
364#define R128_DATATYPE_VYUY422 12
365#define R128_DATATYPE_AYUV444 14
366#define R128_DATATYPE_ARGB4444 15
367
368/* Constants */
369#define R128_AGP_OFFSET 0x02000000
370
371#define R128_WATERMARK_L 16
372#define R128_WATERMARK_M 8
373#define R128_WATERMARK_N 8
374#define R128_WATERMARK_K 128
375
376#define R128_MAX_USEC_TIMEOUT 100000 /* 100 ms */
377
378#define R128_LAST_FRAME_REG R128_GUI_SCRATCH_REG0
379#define R128_LAST_DISPATCH_REG R128_GUI_SCRATCH_REG1
380#define R128_MAX_VB_AGE 0x7fffffff
381#define R128_MAX_VB_VERTS (0xffff)
382
383#define R128_RING_HIGH_MARK 128
384
385#define R128_PERFORMANCE_BOXES 0
386
387#define R128_PCIGART_TABLE_SIZE 32768
388
389#define R128_READ(reg) DRM_READ32( dev_priv->mmio, (reg) )
390#define R128_WRITE(reg,val) DRM_WRITE32( dev_priv->mmio, (reg), (val) )
391#define R128_READ8(reg) DRM_READ8( dev_priv->mmio, (reg) )
392#define R128_WRITE8(reg,val) DRM_WRITE8( dev_priv->mmio, (reg), (val) )
393
394#define R128_WRITE_PLL(addr,val) \
395do { \
396 R128_WRITE8(R128_CLOCK_CNTL_INDEX, \
397 ((addr) & 0x1f) | R128_PLL_WR_EN); \
398 R128_WRITE(R128_CLOCK_CNTL_DATA, (val)); \
399} while (0)
400
401#define CCE_PACKET0( reg, n ) (R128_CCE_PACKET0 | \
402 ((n) << 16) | ((reg) >> 2))
403#define CCE_PACKET1( reg0, reg1 ) (R128_CCE_PACKET1 | \
404 (((reg1) >> 2) << 11) | ((reg0) >> 2))
405#define CCE_PACKET2() (R128_CCE_PACKET2)
406#define CCE_PACKET3( pkt, n ) (R128_CCE_PACKET3 | \
407 (pkt) | ((n) << 16))
408
409static __inline__ void r128_update_ring_snapshot(drm_r128_private_t * dev_priv)
410{
411 drm_r128_ring_buffer_t *ring = &dev_priv->ring;
412 ring->space = (GET_RING_HEAD(dev_priv) - ring->tail) * sizeof(u32);
413 if (ring->space <= 0)
414 ring->space += ring->size;
415}
416
417/* ================================================================
418 * Misc helper macros
419 */
420
421#define RING_SPACE_TEST_WITH_RETURN( dev_priv ) \
422do { \
423 drm_r128_ring_buffer_t *ring = &dev_priv->ring; int i; \
424 if ( ring->space < ring->high_mark ) { \
425 for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) { \
426 r128_update_ring_snapshot( dev_priv ); \
427 if ( ring->space >= ring->high_mark ) \
428 goto __ring_space_done; \
429 DRM_UDELAY(1); \
430 } \
431 DRM_ERROR( "ring space check failed!\n" ); \
432 return -EBUSY; \
433 } \
434 __ring_space_done: \
435 ; \
436} while (0)
437
438#define VB_AGE_TEST_WITH_RETURN( dev_priv ) \
439do { \
440 drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; \
441 if ( sarea_priv->last_dispatch >= R128_MAX_VB_AGE ) { \
442 int __ret = r128_do_cce_idle( dev_priv ); \
443 if ( __ret ) return __ret; \
444 sarea_priv->last_dispatch = 0; \
445 r128_freelist_reset( dev ); \
446 } \
447} while (0)
448
449#define R128_WAIT_UNTIL_PAGE_FLIPPED() do { \
450 OUT_RING( CCE_PACKET0( R128_WAIT_UNTIL, 0 ) ); \
451 OUT_RING( R128_EVENT_CRTC_OFFSET ); \
452} while (0)
453
454/* ================================================================
455 * Ring control
456 */
457
458#define R128_VERBOSE 0
459
460#define RING_LOCALS \
461 int write, _nr; unsigned int tail_mask; volatile u32 *ring;
462
463#define BEGIN_RING( n ) do { \
464 if ( R128_VERBOSE ) { \
465 DRM_INFO( "BEGIN_RING( %d )\n", (n)); \
466 } \
467 if ( dev_priv->ring.space <= (n) * sizeof(u32) ) { \
468 COMMIT_RING(); \
469 r128_wait_ring( dev_priv, (n) * sizeof(u32) ); \
470 } \
471 _nr = n; dev_priv->ring.space -= (n) * sizeof(u32); \
472 ring = dev_priv->ring.start; \
473 write = dev_priv->ring.tail; \
474 tail_mask = dev_priv->ring.tail_mask; \
475} while (0)
476
477/* You can set this to zero if you want. If the card locks up, you'll
478 * need to keep this set. It works around a bug in early revs of the
479 * Rage 128 chipset, where the CCE would read 32 dwords past the end of
480 * the ring buffer before wrapping around.
481 */
482#define R128_BROKEN_CCE 1
483
484#define ADVANCE_RING() do { \
485 if ( R128_VERBOSE ) { \
486 DRM_INFO( "ADVANCE_RING() wr=0x%06x tail=0x%06x\n", \
487 write, dev_priv->ring.tail ); \
488 } \
489 if ( R128_BROKEN_CCE && write < 32 ) { \
490 memcpy( dev_priv->ring.end, \
491 dev_priv->ring.start, \
492 write * sizeof(u32) ); \
493 } \
494 if (((dev_priv->ring.tail + _nr) & tail_mask) != write) { \
495 DRM_ERROR( \
496 "ADVANCE_RING(): mismatch: nr: %x write: %x line: %d\n", \
497 ((dev_priv->ring.tail + _nr) & tail_mask), \
498 write, __LINE__); \
499 } else \
500 dev_priv->ring.tail = write; \
501} while (0)
502
503#define COMMIT_RING() do { \
504 if ( R128_VERBOSE ) { \
505 DRM_INFO( "COMMIT_RING() tail=0x%06x\n", \
506 dev_priv->ring.tail ); \
507 } \
508 DRM_MEMORYBARRIER(); \
509 R128_WRITE( R128_PM4_BUFFER_DL_WPTR, dev_priv->ring.tail ); \
510 R128_READ( R128_PM4_BUFFER_DL_WPTR ); \
511} while (0)
512
513#define OUT_RING( x ) do { \
514 if ( R128_VERBOSE ) { \
515 DRM_INFO( " OUT_RING( 0x%08x ) at 0x%x\n", \
516 (unsigned int)(x), write ); \
517 } \
518 ring[write++] = cpu_to_le32( x ); \
519 write &= tail_mask; \
520} while (0)
521
522#endif /* __R128_DRV_H__ */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-25 21:29:52 -0500