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authorLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
committerLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
commit1da177e4c3f41524e886b7f1b8a0c1fc7321cac2 (patch)
tree0bba044c4ce775e45a88a51686b5d9f90697ea9d /drivers/char/drm/mga_drv.h
Linux-2.6.12-rc2v2.6.12-rc2
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
Diffstat (limited to 'drivers/char/drm/mga_drv.h')
-rw-r--r--drivers/char/drm/mga_drv.h638
1 files changed, 638 insertions, 0 deletions
diff --git a/drivers/char/drm/mga_drv.h b/drivers/char/drm/mga_drv.h
new file mode 100644
index 000000000000..1d84a1eb34db
--- /dev/null
+++ b/drivers/char/drm/mga_drv.h
@@ -0,0 +1,638 @@
1/* mga_drv.h -- Private header for the Matrox G200/G400 driver -*- linux-c -*-
2 * Created: Mon Dec 13 01:50:01 1999 by jhartmann@precisioninsight.com
3 *
4 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
5 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
6 * All rights reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
25 * OTHER DEALINGS IN THE SOFTWARE.
26 *
27 * Authors:
28 * Gareth Hughes <gareth@valinux.com>
29 */
30
31#ifndef __MGA_DRV_H__
32#define __MGA_DRV_H__
33
34/* General customization:
35 */
36
37#define DRIVER_AUTHOR "Gareth Hughes, VA Linux Systems Inc."
38
39#define DRIVER_NAME "mga"
40#define DRIVER_DESC "Matrox G200/G400"
41#define DRIVER_DATE "20021029"
42
43#define DRIVER_MAJOR 3
44#define DRIVER_MINOR 1
45#define DRIVER_PATCHLEVEL 0
46
47typedef struct drm_mga_primary_buffer {
48 u8 *start;
49 u8 *end;
50 int size;
51
52 u32 tail;
53 int space;
54 volatile long wrapped;
55
56 volatile u32 *status;
57
58 u32 last_flush;
59 u32 last_wrap;
60
61 u32 high_mark;
62} drm_mga_primary_buffer_t;
63
64typedef struct drm_mga_freelist {
65 struct drm_mga_freelist *next;
66 struct drm_mga_freelist *prev;
67 drm_mga_age_t age;
68 drm_buf_t *buf;
69} drm_mga_freelist_t;
70
71typedef struct {
72 drm_mga_freelist_t *list_entry;
73 int discard;
74 int dispatched;
75} drm_mga_buf_priv_t;
76
77typedef struct drm_mga_private {
78 drm_mga_primary_buffer_t prim;
79 drm_mga_sarea_t *sarea_priv;
80
81 drm_mga_freelist_t *head;
82 drm_mga_freelist_t *tail;
83
84 unsigned int warp_pipe;
85 unsigned long warp_pipe_phys[MGA_MAX_WARP_PIPES];
86
87 int chipset;
88 int usec_timeout;
89
90 u32 clear_cmd;
91 u32 maccess;
92
93 unsigned int fb_cpp;
94 unsigned int front_offset;
95 unsigned int front_pitch;
96 unsigned int back_offset;
97 unsigned int back_pitch;
98
99 unsigned int depth_cpp;
100 unsigned int depth_offset;
101 unsigned int depth_pitch;
102
103 unsigned int texture_offset;
104 unsigned int texture_size;
105
106 drm_local_map_t *sarea;
107 drm_local_map_t *mmio;
108 drm_local_map_t *status;
109 drm_local_map_t *warp;
110 drm_local_map_t *primary;
111 drm_local_map_t *buffers;
112 drm_local_map_t *agp_textures;
113} drm_mga_private_t;
114
115 /* mga_dma.c */
116extern int mga_dma_init( DRM_IOCTL_ARGS );
117extern int mga_dma_flush( DRM_IOCTL_ARGS );
118extern int mga_dma_reset( DRM_IOCTL_ARGS );
119extern int mga_dma_buffers( DRM_IOCTL_ARGS );
120extern void mga_driver_pretakedown(drm_device_t *dev);
121extern int mga_driver_dma_quiescent(drm_device_t *dev);
122
123extern int mga_do_wait_for_idle( drm_mga_private_t *dev_priv );
124
125extern void mga_do_dma_flush( drm_mga_private_t *dev_priv );
126extern void mga_do_dma_wrap_start( drm_mga_private_t *dev_priv );
127extern void mga_do_dma_wrap_end( drm_mga_private_t *dev_priv );
128
129extern int mga_freelist_put( drm_device_t *dev, drm_buf_t *buf );
130
131 /* mga_warp.c */
132extern int mga_warp_install_microcode( drm_mga_private_t *dev_priv );
133extern int mga_warp_init( drm_mga_private_t *dev_priv );
134
135extern int mga_driver_vblank_wait(drm_device_t *dev, unsigned int *sequence);
136extern irqreturn_t mga_driver_irq_handler( DRM_IRQ_ARGS );
137extern void mga_driver_irq_preinstall( drm_device_t *dev );
138extern void mga_driver_irq_postinstall( drm_device_t *dev );
139extern void mga_driver_irq_uninstall( drm_device_t *dev );
140
141#define mga_flush_write_combine() DRM_WRITEMEMORYBARRIER()
142
143#if defined(__linux__) && defined(__alpha__)
144#define MGA_BASE( reg ) ((unsigned long)(dev_priv->mmio->handle))
145#define MGA_ADDR( reg ) (MGA_BASE(reg) + reg)
146
147#define MGA_DEREF( reg ) *(volatile u32 *)MGA_ADDR( reg )
148#define MGA_DEREF8( reg ) *(volatile u8 *)MGA_ADDR( reg )
149
150#define MGA_READ( reg ) (_MGA_READ((u32 *)MGA_ADDR(reg)))
151#define MGA_READ8( reg ) (_MGA_READ((u8 *)MGA_ADDR(reg)))
152#define MGA_WRITE( reg, val ) do { DRM_WRITEMEMORYBARRIER(); MGA_DEREF( reg ) = val; } while (0)
153#define MGA_WRITE8( reg, val ) do { DRM_WRITEMEMORYBARRIER(); MGA_DEREF8( reg ) = val; } while (0)
154
155static inline u32 _MGA_READ(u32 *addr)
156{
157 DRM_MEMORYBARRIER();
158 return *(volatile u32 *)addr;
159}
160#else
161#define MGA_READ8( reg ) DRM_READ8(dev_priv->mmio, (reg))
162#define MGA_READ( reg ) DRM_READ32(dev_priv->mmio, (reg))
163#define MGA_WRITE8( reg, val ) DRM_WRITE8(dev_priv->mmio, (reg), (val))
164#define MGA_WRITE( reg, val ) DRM_WRITE32(dev_priv->mmio, (reg), (val))
165#endif
166
167#define DWGREG0 0x1c00
168#define DWGREG0_END 0x1dff
169#define DWGREG1 0x2c00
170#define DWGREG1_END 0x2dff
171
172#define ISREG0(r) (r >= DWGREG0 && r <= DWGREG0_END)
173#define DMAREG0(r) (u8)((r - DWGREG0) >> 2)
174#define DMAREG1(r) (u8)(((r - DWGREG1) >> 2) | 0x80)
175#define DMAREG(r) (ISREG0(r) ? DMAREG0(r) : DMAREG1(r))
176
177
178
179/* ================================================================
180 * Helper macross...
181 */
182
183#define MGA_EMIT_STATE( dev_priv, dirty ) \
184do { \
185 if ( (dirty) & ~MGA_UPLOAD_CLIPRECTS ) { \
186 if ( dev_priv->chipset == MGA_CARD_TYPE_G400 ) { \
187 mga_g400_emit_state( dev_priv ); \
188 } else { \
189 mga_g200_emit_state( dev_priv ); \
190 } \
191 } \
192} while (0)
193
194#define WRAP_TEST_WITH_RETURN( dev_priv ) \
195do { \
196 if ( test_bit( 0, &dev_priv->prim.wrapped ) ) { \
197 if ( mga_is_idle( dev_priv ) ) { \
198 mga_do_dma_wrap_end( dev_priv ); \
199 } else if ( dev_priv->prim.space < \
200 dev_priv->prim.high_mark ) { \
201 if ( MGA_DMA_DEBUG ) \
202 DRM_INFO( "%s: wrap...\n", __FUNCTION__ ); \
203 return DRM_ERR(EBUSY); \
204 } \
205 } \
206} while (0)
207
208#define WRAP_WAIT_WITH_RETURN( dev_priv ) \
209do { \
210 if ( test_bit( 0, &dev_priv->prim.wrapped ) ) { \
211 if ( mga_do_wait_for_idle( dev_priv ) < 0 ) { \
212 if ( MGA_DMA_DEBUG ) \
213 DRM_INFO( "%s: wrap...\n", __FUNCTION__ ); \
214 return DRM_ERR(EBUSY); \
215 } \
216 mga_do_dma_wrap_end( dev_priv ); \
217 } \
218} while (0)
219
220
221/* ================================================================
222 * Primary DMA command stream
223 */
224
225#define MGA_VERBOSE 0
226
227#define DMA_LOCALS unsigned int write; volatile u8 *prim;
228
229#define DMA_BLOCK_SIZE (5 * sizeof(u32))
230
231#define BEGIN_DMA( n ) \
232do { \
233 if ( MGA_VERBOSE ) { \
234 DRM_INFO( "BEGIN_DMA( %d ) in %s\n", \
235 (n), __FUNCTION__ ); \
236 DRM_INFO( " space=0x%x req=0x%Zx\n", \
237 dev_priv->prim.space, (n) * DMA_BLOCK_SIZE ); \
238 } \
239 prim = dev_priv->prim.start; \
240 write = dev_priv->prim.tail; \
241} while (0)
242
243#define BEGIN_DMA_WRAP() \
244do { \
245 if ( MGA_VERBOSE ) { \
246 DRM_INFO( "BEGIN_DMA() in %s\n", __FUNCTION__ ); \
247 DRM_INFO( " space=0x%x\n", dev_priv->prim.space ); \
248 } \
249 prim = dev_priv->prim.start; \
250 write = dev_priv->prim.tail; \
251} while (0)
252
253#define ADVANCE_DMA() \
254do { \
255 dev_priv->prim.tail = write; \
256 if ( MGA_VERBOSE ) { \
257 DRM_INFO( "ADVANCE_DMA() tail=0x%05x sp=0x%x\n", \
258 write, dev_priv->prim.space ); \
259 } \
260} while (0)
261
262#define FLUSH_DMA() \
263do { \
264 if ( 0 ) { \
265 DRM_INFO( "%s:\n", __FUNCTION__ ); \
266 DRM_INFO( " tail=0x%06x head=0x%06lx\n", \
267 dev_priv->prim.tail, \
268 MGA_READ( MGA_PRIMADDRESS ) - \
269 dev_priv->primary->offset ); \
270 } \
271 if ( !test_bit( 0, &dev_priv->prim.wrapped ) ) { \
272 if ( dev_priv->prim.space < \
273 dev_priv->prim.high_mark ) { \
274 mga_do_dma_wrap_start( dev_priv ); \
275 } else { \
276 mga_do_dma_flush( dev_priv ); \
277 } \
278 } \
279} while (0)
280
281/* Never use this, always use DMA_BLOCK(...) for primary DMA output.
282 */
283#define DMA_WRITE( offset, val ) \
284do { \
285 if ( MGA_VERBOSE ) { \
286 DRM_INFO( " DMA_WRITE( 0x%08x ) at 0x%04Zx\n", \
287 (u32)(val), write + (offset) * sizeof(u32) ); \
288 } \
289 *(volatile u32 *)(prim + write + (offset) * sizeof(u32)) = val; \
290} while (0)
291
292#define DMA_BLOCK( reg0, val0, reg1, val1, reg2, val2, reg3, val3 ) \
293do { \
294 DMA_WRITE( 0, ((DMAREG( reg0 ) << 0) | \
295 (DMAREG( reg1 ) << 8) | \
296 (DMAREG( reg2 ) << 16) | \
297 (DMAREG( reg3 ) << 24)) ); \
298 DMA_WRITE( 1, val0 ); \
299 DMA_WRITE( 2, val1 ); \
300 DMA_WRITE( 3, val2 ); \
301 DMA_WRITE( 4, val3 ); \
302 write += DMA_BLOCK_SIZE; \
303} while (0)
304
305
306/* Buffer aging via primary DMA stream head pointer.
307 */
308
309#define SET_AGE( age, h, w ) \
310do { \
311 (age)->head = h; \
312 (age)->wrap = w; \
313} while (0)
314
315#define TEST_AGE( age, h, w ) ( (age)->wrap < w || \
316 ( (age)->wrap == w && \
317 (age)->head < h ) )
318
319#define AGE_BUFFER( buf_priv ) \
320do { \
321 drm_mga_freelist_t *entry = (buf_priv)->list_entry; \
322 if ( (buf_priv)->dispatched ) { \
323 entry->age.head = (dev_priv->prim.tail + \
324 dev_priv->primary->offset); \
325 entry->age.wrap = dev_priv->sarea_priv->last_wrap; \
326 } else { \
327 entry->age.head = 0; \
328 entry->age.wrap = 0; \
329 } \
330} while (0)
331
332
333#define MGA_ENGINE_IDLE_MASK (MGA_SOFTRAPEN | \
334 MGA_DWGENGSTS | \
335 MGA_ENDPRDMASTS)
336#define MGA_DMA_IDLE_MASK (MGA_SOFTRAPEN | \
337 MGA_ENDPRDMASTS)
338
339#define MGA_DMA_DEBUG 0
340
341
342
343/* A reduced set of the mga registers.
344 */
345#define MGA_CRTC_INDEX 0x1fd4
346#define MGA_CRTC_DATA 0x1fd5
347
348/* CRTC11 */
349#define MGA_VINTCLR (1 << 4)
350#define MGA_VINTEN (1 << 5)
351
352#define MGA_ALPHACTRL 0x2c7c
353#define MGA_AR0 0x1c60
354#define MGA_AR1 0x1c64
355#define MGA_AR2 0x1c68
356#define MGA_AR3 0x1c6c
357#define MGA_AR4 0x1c70
358#define MGA_AR5 0x1c74
359#define MGA_AR6 0x1c78
360
361#define MGA_CXBNDRY 0x1c80
362#define MGA_CXLEFT 0x1ca0
363#define MGA_CXRIGHT 0x1ca4
364
365#define MGA_DMAPAD 0x1c54
366#define MGA_DSTORG 0x2cb8
367#define MGA_DWGCTL 0x1c00
368# define MGA_OPCOD_MASK (15 << 0)
369# define MGA_OPCOD_TRAP (4 << 0)
370# define MGA_OPCOD_TEXTURE_TRAP (6 << 0)
371# define MGA_OPCOD_BITBLT (8 << 0)
372# define MGA_OPCOD_ILOAD (9 << 0)
373# define MGA_ATYPE_MASK (7 << 4)
374# define MGA_ATYPE_RPL (0 << 4)
375# define MGA_ATYPE_RSTR (1 << 4)
376# define MGA_ATYPE_ZI (3 << 4)
377# define MGA_ATYPE_BLK (4 << 4)
378# define MGA_ATYPE_I (7 << 4)
379# define MGA_LINEAR (1 << 7)
380# define MGA_ZMODE_MASK (7 << 8)
381# define MGA_ZMODE_NOZCMP (0 << 8)
382# define MGA_ZMODE_ZE (2 << 8)
383# define MGA_ZMODE_ZNE (3 << 8)
384# define MGA_ZMODE_ZLT (4 << 8)
385# define MGA_ZMODE_ZLTE (5 << 8)
386# define MGA_ZMODE_ZGT (6 << 8)
387# define MGA_ZMODE_ZGTE (7 << 8)
388# define MGA_SOLID (1 << 11)
389# define MGA_ARZERO (1 << 12)
390# define MGA_SGNZERO (1 << 13)
391# define MGA_SHIFTZERO (1 << 14)
392# define MGA_BOP_MASK (15 << 16)
393# define MGA_BOP_ZERO (0 << 16)
394# define MGA_BOP_DST (10 << 16)
395# define MGA_BOP_SRC (12 << 16)
396# define MGA_BOP_ONE (15 << 16)
397# define MGA_TRANS_SHIFT 20
398# define MGA_TRANS_MASK (15 << 20)
399# define MGA_BLTMOD_MASK (15 << 25)
400# define MGA_BLTMOD_BMONOLEF (0 << 25)
401# define MGA_BLTMOD_BMONOWF (4 << 25)
402# define MGA_BLTMOD_PLAN (1 << 25)
403# define MGA_BLTMOD_BFCOL (2 << 25)
404# define MGA_BLTMOD_BU32BGR (3 << 25)
405# define MGA_BLTMOD_BU32RGB (7 << 25)
406# define MGA_BLTMOD_BU24BGR (11 << 25)
407# define MGA_BLTMOD_BU24RGB (15 << 25)
408# define MGA_PATTERN (1 << 29)
409# define MGA_TRANSC (1 << 30)
410# define MGA_CLIPDIS (1 << 31)
411#define MGA_DWGSYNC 0x2c4c
412
413#define MGA_FCOL 0x1c24
414#define MGA_FIFOSTATUS 0x1e10
415#define MGA_FOGCOL 0x1cf4
416#define MGA_FXBNDRY 0x1c84
417#define MGA_FXLEFT 0x1ca8
418#define MGA_FXRIGHT 0x1cac
419
420#define MGA_ICLEAR 0x1e18
421# define MGA_SOFTRAPICLR (1 << 0)
422# define MGA_VLINEICLR (1 << 5)
423#define MGA_IEN 0x1e1c
424# define MGA_SOFTRAPIEN (1 << 0)
425# define MGA_VLINEIEN (1 << 5)
426
427#define MGA_LEN 0x1c5c
428
429#define MGA_MACCESS 0x1c04
430
431#define MGA_PITCH 0x1c8c
432#define MGA_PLNWT 0x1c1c
433#define MGA_PRIMADDRESS 0x1e58
434# define MGA_DMA_GENERAL (0 << 0)
435# define MGA_DMA_BLIT (1 << 0)
436# define MGA_DMA_VECTOR (2 << 0)
437# define MGA_DMA_VERTEX (3 << 0)
438#define MGA_PRIMEND 0x1e5c
439# define MGA_PRIMNOSTART (1 << 0)
440# define MGA_PAGPXFER (1 << 1)
441#define MGA_PRIMPTR 0x1e50
442# define MGA_PRIMPTREN0 (1 << 0)
443# define MGA_PRIMPTREN1 (1 << 1)
444
445#define MGA_RST 0x1e40
446# define MGA_SOFTRESET (1 << 0)
447# define MGA_SOFTEXTRST (1 << 1)
448
449#define MGA_SECADDRESS 0x2c40
450#define MGA_SECEND 0x2c44
451#define MGA_SETUPADDRESS 0x2cd0
452#define MGA_SETUPEND 0x2cd4
453#define MGA_SGN 0x1c58
454#define MGA_SOFTRAP 0x2c48
455#define MGA_SRCORG 0x2cb4
456# define MGA_SRMMAP_MASK (1 << 0)
457# define MGA_SRCMAP_FB (0 << 0)
458# define MGA_SRCMAP_SYSMEM (1 << 0)
459# define MGA_SRCACC_MASK (1 << 1)
460# define MGA_SRCACC_PCI (0 << 1)
461# define MGA_SRCACC_AGP (1 << 1)
462#define MGA_STATUS 0x1e14
463# define MGA_SOFTRAPEN (1 << 0)
464# define MGA_VSYNCPEN (1 << 4)
465# define MGA_VLINEPEN (1 << 5)
466# define MGA_DWGENGSTS (1 << 16)
467# define MGA_ENDPRDMASTS (1 << 17)
468#define MGA_STENCIL 0x2cc8
469#define MGA_STENCILCTL 0x2ccc
470
471#define MGA_TDUALSTAGE0 0x2cf8
472#define MGA_TDUALSTAGE1 0x2cfc
473#define MGA_TEXBORDERCOL 0x2c5c
474#define MGA_TEXCTL 0x2c30
475#define MGA_TEXCTL2 0x2c3c
476# define MGA_DUALTEX (1 << 7)
477# define MGA_G400_TC2_MAGIC (1 << 15)
478# define MGA_MAP1_ENABLE (1 << 31)
479#define MGA_TEXFILTER 0x2c58
480#define MGA_TEXHEIGHT 0x2c2c
481#define MGA_TEXORG 0x2c24
482# define MGA_TEXORGMAP_MASK (1 << 0)
483# define MGA_TEXORGMAP_FB (0 << 0)
484# define MGA_TEXORGMAP_SYSMEM (1 << 0)
485# define MGA_TEXORGACC_MASK (1 << 1)
486# define MGA_TEXORGACC_PCI (0 << 1)
487# define MGA_TEXORGACC_AGP (1 << 1)
488#define MGA_TEXORG1 0x2ca4
489#define MGA_TEXORG2 0x2ca8
490#define MGA_TEXORG3 0x2cac
491#define MGA_TEXORG4 0x2cb0
492#define MGA_TEXTRANS 0x2c34
493#define MGA_TEXTRANSHIGH 0x2c38
494#define MGA_TEXWIDTH 0x2c28
495
496#define MGA_WACCEPTSEQ 0x1dd4
497#define MGA_WCODEADDR 0x1e6c
498#define MGA_WFLAG 0x1dc4
499#define MGA_WFLAG1 0x1de0
500#define MGA_WFLAGNB 0x1e64
501#define MGA_WFLAGNB1 0x1e08
502#define MGA_WGETMSB 0x1dc8
503#define MGA_WIADDR 0x1dc0
504#define MGA_WIADDR2 0x1dd8
505# define MGA_WMODE_SUSPEND (0 << 0)
506# define MGA_WMODE_RESUME (1 << 0)
507# define MGA_WMODE_JUMP (2 << 0)
508# define MGA_WMODE_START (3 << 0)
509# define MGA_WAGP_ENABLE (1 << 2)
510#define MGA_WMISC 0x1e70
511# define MGA_WUCODECACHE_ENABLE (1 << 0)
512# define MGA_WMASTER_ENABLE (1 << 1)
513# define MGA_WCACHEFLUSH_ENABLE (1 << 3)
514#define MGA_WVRTXSZ 0x1dcc
515
516#define MGA_YBOT 0x1c9c
517#define MGA_YDST 0x1c90
518#define MGA_YDSTLEN 0x1c88
519#define MGA_YDSTORG 0x1c94
520#define MGA_YTOP 0x1c98
521
522#define MGA_ZORG 0x1c0c
523
524/* This finishes the current batch of commands
525 */
526#define MGA_EXEC 0x0100
527
528/* Warp registers
529 */
530#define MGA_WR0 0x2d00
531#define MGA_WR1 0x2d04
532#define MGA_WR2 0x2d08
533#define MGA_WR3 0x2d0c
534#define MGA_WR4 0x2d10
535#define MGA_WR5 0x2d14
536#define MGA_WR6 0x2d18
537#define MGA_WR7 0x2d1c
538#define MGA_WR8 0x2d20
539#define MGA_WR9 0x2d24
540#define MGA_WR10 0x2d28
541#define MGA_WR11 0x2d2c
542#define MGA_WR12 0x2d30
543#define MGA_WR13 0x2d34
544#define MGA_WR14 0x2d38
545#define MGA_WR15 0x2d3c
546#define MGA_WR16 0x2d40
547#define MGA_WR17 0x2d44
548#define MGA_WR18 0x2d48
549#define MGA_WR19 0x2d4c
550#define MGA_WR20 0x2d50
551#define MGA_WR21 0x2d54
552#define MGA_WR22 0x2d58
553#define MGA_WR23 0x2d5c
554#define MGA_WR24 0x2d60
555#define MGA_WR25 0x2d64
556#define MGA_WR26 0x2d68
557#define MGA_WR27 0x2d6c
558#define MGA_WR28 0x2d70
559#define MGA_WR29 0x2d74
560#define MGA_WR30 0x2d78
561#define MGA_WR31 0x2d7c
562#define MGA_WR32 0x2d80
563#define MGA_WR33 0x2d84
564#define MGA_WR34 0x2d88
565#define MGA_WR35 0x2d8c
566#define MGA_WR36 0x2d90
567#define MGA_WR37 0x2d94
568#define MGA_WR38 0x2d98
569#define MGA_WR39 0x2d9c
570#define MGA_WR40 0x2da0
571#define MGA_WR41 0x2da4
572#define MGA_WR42 0x2da8
573#define MGA_WR43 0x2dac
574#define MGA_WR44 0x2db0
575#define MGA_WR45 0x2db4
576#define MGA_WR46 0x2db8
577#define MGA_WR47 0x2dbc
578#define MGA_WR48 0x2dc0
579#define MGA_WR49 0x2dc4
580#define MGA_WR50 0x2dc8
581#define MGA_WR51 0x2dcc
582#define MGA_WR52 0x2dd0
583#define MGA_WR53 0x2dd4
584#define MGA_WR54 0x2dd8
585#define MGA_WR55 0x2ddc
586#define MGA_WR56 0x2de0
587#define MGA_WR57 0x2de4
588#define MGA_WR58 0x2de8
589#define MGA_WR59 0x2dec
590#define MGA_WR60 0x2df0
591#define MGA_WR61 0x2df4
592#define MGA_WR62 0x2df8
593#define MGA_WR63 0x2dfc
594# define MGA_G400_WR_MAGIC (1 << 6)
595# define MGA_G400_WR56_MAGIC 0x46480000 /* 12800.0f */
596
597
598#define MGA_ILOAD_ALIGN 64
599#define MGA_ILOAD_MASK (MGA_ILOAD_ALIGN - 1)
600
601#define MGA_DWGCTL_FLUSH (MGA_OPCOD_TEXTURE_TRAP | \
602 MGA_ATYPE_I | \
603 MGA_ZMODE_NOZCMP | \
604 MGA_ARZERO | \
605 MGA_SGNZERO | \
606 MGA_BOP_SRC | \
607 (15 << MGA_TRANS_SHIFT))
608
609#define MGA_DWGCTL_CLEAR (MGA_OPCOD_TRAP | \
610 MGA_ZMODE_NOZCMP | \
611 MGA_SOLID | \
612 MGA_ARZERO | \
613 MGA_SGNZERO | \
614 MGA_SHIFTZERO | \
615 MGA_BOP_SRC | \
616 (0 << MGA_TRANS_SHIFT) | \
617 MGA_BLTMOD_BMONOLEF | \
618 MGA_TRANSC | \
619 MGA_CLIPDIS)
620
621#define MGA_DWGCTL_COPY (MGA_OPCOD_BITBLT | \
622 MGA_ATYPE_RPL | \
623 MGA_SGNZERO | \
624 MGA_SHIFTZERO | \
625 MGA_BOP_SRC | \
626 (0 << MGA_TRANS_SHIFT) | \
627 MGA_BLTMOD_BFCOL | \
628 MGA_CLIPDIS)
629
630/* Simple idle test.
631 */
632static __inline__ int mga_is_idle( drm_mga_private_t *dev_priv )
633{
634 u32 status = MGA_READ( MGA_STATUS ) & MGA_ENGINE_IDLE_MASK;
635 return ( status == MGA_ENDPRDMASTS );
636}
637
638#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-03 18:32:24 -0500