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authorJesse Barnes <jbarnes@virtuousgeek.org>2008-04-22 02:03:07 -0400
committerDave Airlie <airlied@linux.ie>2008-04-26 04:01:07 -0400
commitac741ab71bb39e6977694ac0cc26678d8673cda4 (patch)
treef82e08399a0da5accba930444744b269479185dd /drivers/char/drm/i915_irq.c
parent2c14f28be2a3f2a2e9861b156d64fbe2bc7000c3 (diff)
drm/vbl rework: rework how the drm deals with vblank.
Other Authors: Michel Dänzer <michel@tungstengraphics.com> mga: Ian Romanick <idr@us.ibm.com> via: Thomas Hellstrom <thomas-at-tungstengraphics-dot-com> This re-works the DRM internals to provide a better interface for drivers to expose vblank on multiple crtcs. It also includes work done by Michel on making i915 triple buffering and pageflipping work properly. Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/char/drm/i915_irq.c')
-rw-r--r--drivers/char/drm/i915_irq.c597
1 files changed, 445 insertions, 152 deletions
diff --git a/drivers/char/drm/i915_irq.c b/drivers/char/drm/i915_irq.c
index f7f16e7a8bf3..023ce66ef3ab 100644
--- a/drivers/char/drm/i915_irq.c
+++ b/drivers/char/drm/i915_irq.c
@@ -38,6 +38,109 @@
38#define MAX_NOPID ((u32)~0) 38#define MAX_NOPID ((u32)~0)
39 39
40/** 40/**
41 * i915_get_pipe - return the the pipe associated with a given plane
42 * @dev: DRM device
43 * @plane: plane to look for
44 *
45 * The Intel Mesa & 2D drivers call the vblank routines with a plane number
46 * rather than a pipe number, since they may not always be equal. This routine
47 * maps the given @plane back to a pipe number.
48 */
49static int
50i915_get_pipe(struct drm_device *dev, int plane)
51{
52 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
53 u32 dspcntr;
54
55 dspcntr = plane ? I915_READ(DSPBCNTR) : I915_READ(DSPACNTR);
56
57 return dspcntr & DISPPLANE_SEL_PIPE_MASK ? 1 : 0;
58}
59
60/**
61 * i915_get_plane - return the the plane associated with a given pipe
62 * @dev: DRM device
63 * @pipe: pipe to look for
64 *
65 * The Intel Mesa & 2D drivers call the vblank routines with a plane number
66 * rather than a plane number, since they may not always be equal. This routine
67 * maps the given @pipe back to a plane number.
68 */
69static int
70i915_get_plane(struct drm_device *dev, int pipe)
71{
72 if (i915_get_pipe(dev, 0) == pipe)
73 return 0;
74 return 1;
75}
76
77/**
78 * i915_pipe_enabled - check if a pipe is enabled
79 * @dev: DRM device
80 * @pipe: pipe to check
81 *
82 * Reading certain registers when the pipe is disabled can hang the chip.
83 * Use this routine to make sure the PLL is running and the pipe is active
84 * before reading such registers if unsure.
85 */
86static int
87i915_pipe_enabled(struct drm_device *dev, int pipe)
88{
89 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
90 unsigned long pipeconf = pipe ? PIPEBCONF : PIPEACONF;
91
92 if (I915_READ(pipeconf) & PIPEACONF_ENABLE)
93 return 1;
94
95 return 0;
96}
97
98/**
99 * Emit a synchronous flip.
100 *
101 * This function must be called with the drawable spinlock held.
102 */
103static void
104i915_dispatch_vsync_flip(struct drm_device *dev, struct drm_drawable_info *drw,
105 int plane)
106{
107 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
108 drm_i915_sarea_t *sarea_priv = dev_priv->sarea_priv;
109 u16 x1, y1, x2, y2;
110 int pf_planes = 1 << plane;
111
112 /* If the window is visible on the other plane, we have to flip on that
113 * plane as well.
114 */
115 if (plane == 1) {
116 x1 = sarea_priv->planeA_x;
117 y1 = sarea_priv->planeA_y;
118 x2 = x1 + sarea_priv->planeA_w;
119 y2 = y1 + sarea_priv->planeA_h;
120 } else {
121 x1 = sarea_priv->planeB_x;
122 y1 = sarea_priv->planeB_y;
123 x2 = x1 + sarea_priv->planeB_w;
124 y2 = y1 + sarea_priv->planeB_h;
125 }
126
127 if (x2 > 0 && y2 > 0) {
128 int i, num_rects = drw->num_rects;
129 struct drm_clip_rect *rect = drw->rects;
130
131 for (i = 0; i < num_rects; i++)
132 if (!(rect[i].x1 >= x2 || rect[i].y1 >= y2 ||
133 rect[i].x2 <= x1 || rect[i].y2 <= y1)) {
134 pf_planes = 0x3;
135
136 break;
137 }
138 }
139
140 i915_dispatch_flip(dev, pf_planes, 1);
141}
142
143/**
41 * Emit blits for scheduled buffer swaps. 144 * Emit blits for scheduled buffer swaps.
42 * 145 *
43 * This function will be called with the HW lock held. 146 * This function will be called with the HW lock held.
@@ -45,20 +148,19 @@
45static void i915_vblank_tasklet(struct drm_device *dev) 148static void i915_vblank_tasklet(struct drm_device *dev)
46{ 149{
47 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 150 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
48 unsigned long irqflags;
49 struct list_head *list, *tmp, hits, *hit; 151 struct list_head *list, *tmp, hits, *hit;
50 int nhits, nrects, slice[2], upper[2], lower[2], i; 152 int nhits, nrects, slice[2], upper[2], lower[2], i, num_pages;
51 unsigned counter[2] = { atomic_read(&dev->vbl_received), 153 unsigned counter[2];
52 atomic_read(&dev->vbl_received2) };
53 struct drm_drawable_info *drw; 154 struct drm_drawable_info *drw;
54 drm_i915_sarea_t *sarea_priv = dev_priv->sarea_priv; 155 drm_i915_sarea_t *sarea_priv = dev_priv->sarea_priv;
55 u32 cpp = dev_priv->cpp; 156 u32 cpp = dev_priv->cpp, offsets[3];
56 u32 cmd = (cpp == 4) ? (XY_SRC_COPY_BLT_CMD | 157 u32 cmd = (cpp == 4) ? (XY_SRC_COPY_BLT_CMD |
57 XY_SRC_COPY_BLT_WRITE_ALPHA | 158 XY_SRC_COPY_BLT_WRITE_ALPHA |
58 XY_SRC_COPY_BLT_WRITE_RGB) 159 XY_SRC_COPY_BLT_WRITE_RGB)
59 : XY_SRC_COPY_BLT_CMD; 160 : XY_SRC_COPY_BLT_CMD;
60 u32 src_pitch = sarea_priv->pitch * cpp; 161 u32 src_pitch = sarea_priv->pitch * cpp;
61 u32 dst_pitch = sarea_priv->pitch * cpp; 162 u32 dst_pitch = sarea_priv->pitch * cpp;
163 /* COPY rop (0xcc), map cpp to magic color depth constants */
62 u32 ropcpp = (0xcc << 16) | ((cpp - 1) << 24); 164 u32 ropcpp = (0xcc << 16) | ((cpp - 1) << 24);
63 RING_LOCALS; 165 RING_LOCALS;
64 166
@@ -71,24 +173,34 @@ static void i915_vblank_tasklet(struct drm_device *dev)
71 src_pitch >>= 2; 173 src_pitch >>= 2;
72 } 174 }
73 175
176 counter[0] = drm_vblank_count(dev, 0);
177 counter[1] = drm_vblank_count(dev, 1);
178
74 DRM_DEBUG("\n"); 179 DRM_DEBUG("\n");
75 180
76 INIT_LIST_HEAD(&hits); 181 INIT_LIST_HEAD(&hits);
77 182
78 nhits = nrects = 0; 183 nhits = nrects = 0;
79 184
80 spin_lock_irqsave(&dev_priv->swaps_lock, irqflags); 185 /* No irqsave/restore necessary. This tasklet may be run in an
186 * interrupt context or normal context, but we don't have to worry
187 * about getting interrupted by something acquiring the lock, because
188 * we are the interrupt context thing that acquires the lock.
189 */
190 spin_lock(&dev_priv->swaps_lock);
81 191
82 /* Find buffer swaps scheduled for this vertical blank */ 192 /* Find buffer swaps scheduled for this vertical blank */
83 list_for_each_safe(list, tmp, &dev_priv->vbl_swaps.head) { 193 list_for_each_safe(list, tmp, &dev_priv->vbl_swaps.head) {
84 drm_i915_vbl_swap_t *vbl_swap = 194 drm_i915_vbl_swap_t *vbl_swap =
85 list_entry(list, drm_i915_vbl_swap_t, head); 195 list_entry(list, drm_i915_vbl_swap_t, head);
196 int pipe = i915_get_pipe(dev, vbl_swap->plane);
86 197
87 if ((counter[vbl_swap->pipe] - vbl_swap->sequence) > (1<<23)) 198 if ((counter[pipe] - vbl_swap->sequence) > (1<<23))
88 continue; 199 continue;
89 200
90 list_del(list); 201 list_del(list);
91 dev_priv->swaps_pending--; 202 dev_priv->swaps_pending--;
203 drm_vblank_put(dev, pipe);
92 204
93 spin_unlock(&dev_priv->swaps_lock); 205 spin_unlock(&dev_priv->swaps_lock);
94 spin_lock(&dev->drw_lock); 206 spin_lock(&dev->drw_lock);
@@ -126,43 +238,23 @@ static void i915_vblank_tasklet(struct drm_device *dev)
126 spin_lock(&dev_priv->swaps_lock); 238 spin_lock(&dev_priv->swaps_lock);
127 } 239 }
128 240
129 if (nhits == 0) {
130 spin_unlock_irqrestore(&dev_priv->swaps_lock, irqflags);
131 return;
132 }
133
134 spin_unlock(&dev_priv->swaps_lock); 241 spin_unlock(&dev_priv->swaps_lock);
135 242
136 i915_kernel_lost_context(dev); 243 if (nhits == 0)
137 244 return;
138 if (IS_I965G(dev)) {
139 BEGIN_LP_RING(4);
140
141 OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
142 OUT_RING(0);
143 OUT_RING(((sarea_priv->width - 1) & 0xffff) | ((sarea_priv->height - 1) << 16));
144 OUT_RING(0);
145 ADVANCE_LP_RING();
146 } else {
147 BEGIN_LP_RING(6);
148
149 OUT_RING(GFX_OP_DRAWRECT_INFO);
150 OUT_RING(0);
151 OUT_RING(0);
152 OUT_RING(sarea_priv->width | sarea_priv->height << 16);
153 OUT_RING(sarea_priv->width | sarea_priv->height << 16);
154 OUT_RING(0);
155
156 ADVANCE_LP_RING();
157 }
158 245
159 sarea_priv->ctxOwner = DRM_KERNEL_CONTEXT; 246 i915_kernel_lost_context(dev);
160 247
161 upper[0] = upper[1] = 0; 248 upper[0] = upper[1] = 0;
162 slice[0] = max(sarea_priv->pipeA_h / nhits, 1); 249 slice[0] = max(sarea_priv->planeA_h / nhits, 1);
163 slice[1] = max(sarea_priv->pipeB_h / nhits, 1); 250 slice[1] = max(sarea_priv->planeB_h / nhits, 1);
164 lower[0] = sarea_priv->pipeA_y + slice[0]; 251 lower[0] = sarea_priv->planeA_y + slice[0];
165 lower[1] = sarea_priv->pipeB_y + slice[0]; 252 lower[1] = sarea_priv->planeB_y + slice[0];
253
254 offsets[0] = sarea_priv->front_offset;
255 offsets[1] = sarea_priv->back_offset;
256 offsets[2] = sarea_priv->third_offset;
257 num_pages = sarea_priv->third_handle ? 3 : 2;
166 258
167 spin_lock(&dev->drw_lock); 259 spin_lock(&dev->drw_lock);
168 260
@@ -174,6 +266,8 @@ static void i915_vblank_tasklet(struct drm_device *dev)
174 for (i = 0; i++ < nhits; 266 for (i = 0; i++ < nhits;
175 upper[0] = lower[0], lower[0] += slice[0], 267 upper[0] = lower[0], lower[0] += slice[0],
176 upper[1] = lower[1], lower[1] += slice[1]) { 268 upper[1] = lower[1], lower[1] += slice[1]) {
269 int init_drawrect = 1;
270
177 if (i == nhits) 271 if (i == nhits)
178 lower[0] = lower[1] = sarea_priv->height; 272 lower[0] = lower[1] = sarea_priv->height;
179 273
@@ -181,7 +275,7 @@ static void i915_vblank_tasklet(struct drm_device *dev)
181 drm_i915_vbl_swap_t *swap_hit = 275 drm_i915_vbl_swap_t *swap_hit =
182 list_entry(hit, drm_i915_vbl_swap_t, head); 276 list_entry(hit, drm_i915_vbl_swap_t, head);
183 struct drm_clip_rect *rect; 277 struct drm_clip_rect *rect;
184 int num_rects, pipe; 278 int num_rects, plane, front, back;
185 unsigned short top, bottom; 279 unsigned short top, bottom;
186 280
187 drw = drm_get_drawable_info(dev, swap_hit->drw_id); 281 drw = drm_get_drawable_info(dev, swap_hit->drw_id);
@@ -189,10 +283,50 @@ static void i915_vblank_tasklet(struct drm_device *dev)
189 if (!drw) 283 if (!drw)
190 continue; 284 continue;
191 285
286 plane = swap_hit->plane;
287
288 if (swap_hit->flip) {
289 i915_dispatch_vsync_flip(dev, drw, plane);
290 continue;
291 }
292
293 if (init_drawrect) {
294 int width = sarea_priv->width;
295 int height = sarea_priv->height;
296 if (IS_I965G(dev)) {
297 BEGIN_LP_RING(4);
298
299 OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
300 OUT_RING(0);
301 OUT_RING(((width - 1) & 0xffff) | ((height - 1) << 16));
302 OUT_RING(0);
303
304 ADVANCE_LP_RING();
305 } else {
306 BEGIN_LP_RING(6);
307
308 OUT_RING(GFX_OP_DRAWRECT_INFO);
309 OUT_RING(0);
310 OUT_RING(0);
311 OUT_RING(((width - 1) & 0xffff) | ((height - 1) << 16));
312 OUT_RING(0);
313 OUT_RING(0);
314
315 ADVANCE_LP_RING();
316 }
317
318 sarea_priv->ctxOwner = DRM_KERNEL_CONTEXT;
319
320 init_drawrect = 0;
321 }
322
192 rect = drw->rects; 323 rect = drw->rects;
193 pipe = swap_hit->pipe; 324 top = upper[plane];
194 top = upper[pipe]; 325 bottom = lower[plane];
195 bottom = lower[pipe]; 326
327 front = (dev_priv->sarea_priv->pf_current_page >>
328 (2 * plane)) & 0x3;
329 back = (front + 1) % num_pages;
196 330
197 for (num_rects = drw->num_rects; num_rects--; rect++) { 331 for (num_rects = drw->num_rects; num_rects--; rect++) {
198 int y1 = max(rect->y1, top); 332 int y1 = max(rect->y1, top);
@@ -207,17 +341,17 @@ static void i915_vblank_tasklet(struct drm_device *dev)
207 OUT_RING(ropcpp | dst_pitch); 341 OUT_RING(ropcpp | dst_pitch);
208 OUT_RING((y1 << 16) | rect->x1); 342 OUT_RING((y1 << 16) | rect->x1);
209 OUT_RING((y2 << 16) | rect->x2); 343 OUT_RING((y2 << 16) | rect->x2);
210 OUT_RING(sarea_priv->front_offset); 344 OUT_RING(offsets[front]);
211 OUT_RING((y1 << 16) | rect->x1); 345 OUT_RING((y1 << 16) | rect->x1);
212 OUT_RING(src_pitch); 346 OUT_RING(src_pitch);
213 OUT_RING(sarea_priv->back_offset); 347 OUT_RING(offsets[back]);
214 348
215 ADVANCE_LP_RING(); 349 ADVANCE_LP_RING();
216 } 350 }
217 } 351 }
218 } 352 }
219 353
220 spin_unlock_irqrestore(&dev->drw_lock, irqflags); 354 spin_unlock(&dev->drw_lock);
221 355
222 list_for_each_safe(hit, tmp, &hits) { 356 list_for_each_safe(hit, tmp, &hits) {
223 drm_i915_vbl_swap_t *swap_hit = 357 drm_i915_vbl_swap_t *swap_hit =
@@ -229,67 +363,112 @@ static void i915_vblank_tasklet(struct drm_device *dev)
229 } 363 }
230} 364}
231 365
366u32 i915_get_vblank_counter(struct drm_device *dev, int plane)
367{
368 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
369 unsigned long high_frame;
370 unsigned long low_frame;
371 u32 high1, high2, low, count;
372 int pipe;
373
374 pipe = i915_get_pipe(dev, plane);
375 high_frame = pipe ? PIPEBFRAMEHIGH : PIPEAFRAMEHIGH;
376 low_frame = pipe ? PIPEBFRAMEPIXEL : PIPEAFRAMEPIXEL;
377
378 if (!i915_pipe_enabled(dev, pipe)) {
379 printk(KERN_ERR "trying to get vblank count for disabled "
380 "pipe %d\n", pipe);
381 return 0;
382 }
383
384 /*
385 * High & low register fields aren't synchronized, so make sure
386 * we get a low value that's stable across two reads of the high
387 * register.
388 */
389 do {
390 high1 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
391 PIPE_FRAME_HIGH_SHIFT);
392 low = ((I915_READ(low_frame) & PIPE_FRAME_LOW_MASK) >>
393 PIPE_FRAME_LOW_SHIFT);
394 high2 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
395 PIPE_FRAME_HIGH_SHIFT);
396 } while (high1 != high2);
397
398 count = (high1 << 8) | low;
399
400 /* count may be reset by other driver(e.g. 2D driver),
401 we have no way to know if it is wrapped or resetted
402 when count is zero. do a rough guess.
403 */
404 if (count == 0 && dev->last_vblank[pipe] < dev->max_vblank_count/2)
405 dev->last_vblank[pipe] = 0;
406
407 return count;
408}
409
232irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS) 410irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
233{ 411{
234 struct drm_device *dev = (struct drm_device *) arg; 412 struct drm_device *dev = (struct drm_device *) arg;
235 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 413 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
236 u16 temp; 414 u32 iir;
237 u32 pipea_stats, pipeb_stats; 415 u32 pipea_stats, pipeb_stats;
238 416 int vblank = 0;
239 pipea_stats = I915_READ(I915REG_PIPEASTAT); 417
240 pipeb_stats = I915_READ(I915REG_PIPEBSTAT); 418 iir = I915_READ(I915REG_INT_IDENTITY_R);
241 419 if (iir == 0) {
242 temp = I915_READ16(I915REG_INT_IDENTITY_R); 420 DRM_DEBUG ("iir 0x%08x im 0x%08x ie 0x%08x pipea 0x%08x pipeb 0x%08x\n",
243 421 iir,
244 temp &= (USER_INT_FLAG | VSYNC_PIPEA_FLAG | VSYNC_PIPEB_FLAG); 422 I915_READ(I915REG_INT_MASK_R),
245 423 I915_READ(I915REG_INT_ENABLE_R),
246 DRM_DEBUG("%s flag=%08x\n", __FUNCTION__, temp); 424 I915_READ(I915REG_PIPEASTAT),
247 425 I915_READ(I915REG_PIPEBSTAT));
248 if (temp == 0)
249 return IRQ_NONE; 426 return IRQ_NONE;
427 }
250 428
251 I915_WRITE16(I915REG_INT_IDENTITY_R, temp); 429 /*
252 (void) I915_READ16(I915REG_INT_IDENTITY_R); 430 * Clear the PIPE(A|B)STAT regs before the IIR otherwise
253 DRM_READMEMORYBARRIER(); 431 * we may get extra interrupts.
254 432 */
255 dev_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv); 433 if (iir & I915_DISPLAY_PIPE_A_EVENT_INTERRUPT) {
434 pipea_stats = I915_READ(I915REG_PIPEASTAT);
435 if (pipea_stats & (I915_START_VBLANK_INTERRUPT_STATUS|
436 I915_VBLANK_INTERRUPT_STATUS))
437 {
438 vblank++;
439 drm_handle_vblank(dev, i915_get_plane(dev, 0));
440 }
441 I915_WRITE(I915REG_PIPEASTAT, pipea_stats);
442 }
443 if (iir & I915_DISPLAY_PIPE_B_EVENT_INTERRUPT) {
444 pipeb_stats = I915_READ(I915REG_PIPEBSTAT);
445 if (pipeb_stats & (I915_START_VBLANK_INTERRUPT_STATUS|
446 I915_VBLANK_INTERRUPT_STATUS))
447 {
448 vblank++;
449 drm_handle_vblank(dev, i915_get_plane(dev, 1));
450 }
451 I915_WRITE(I915REG_PIPEBSTAT, pipeb_stats);
452 }
256 453
257 if (temp & USER_INT_FLAG) 454 if (dev_priv->sarea_priv)
258 DRM_WAKEUP(&dev_priv->irq_queue); 455 dev_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
259 456
260 if (temp & (VSYNC_PIPEA_FLAG | VSYNC_PIPEB_FLAG)) { 457 I915_WRITE(I915REG_INT_IDENTITY_R, iir);
261 int vblank_pipe = dev_priv->vblank_pipe; 458 (void) I915_READ(I915REG_INT_IDENTITY_R); /* Flush posted write */
262
263 if ((vblank_pipe &
264 (DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B))
265 == (DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B)) {
266 if (temp & VSYNC_PIPEA_FLAG)
267 atomic_inc(&dev->vbl_received);
268 if (temp & VSYNC_PIPEB_FLAG)
269 atomic_inc(&dev->vbl_received2);
270 } else if (((temp & VSYNC_PIPEA_FLAG) &&
271 (vblank_pipe & DRM_I915_VBLANK_PIPE_A)) ||
272 ((temp & VSYNC_PIPEB_FLAG) &&
273 (vblank_pipe & DRM_I915_VBLANK_PIPE_B)))
274 atomic_inc(&dev->vbl_received);
275
276 DRM_WAKEUP(&dev->vbl_queue);
277 drm_vbl_send_signals(dev);
278 459
460 if (iir & I915_USER_INTERRUPT) {
461 DRM_WAKEUP(&dev_priv->irq_queue);
462 }
463 if (vblank) {
279 if (dev_priv->swaps_pending > 0) 464 if (dev_priv->swaps_pending > 0)
280 drm_locked_tasklet(dev, i915_vblank_tasklet); 465 drm_locked_tasklet(dev, i915_vblank_tasklet);
281 I915_WRITE(I915REG_PIPEASTAT,
282 pipea_stats|I915_VBLANK_INTERRUPT_ENABLE|
283 I915_VBLANK_CLEAR);
284 I915_WRITE(I915REG_PIPEBSTAT,
285 pipeb_stats|I915_VBLANK_INTERRUPT_ENABLE|
286 I915_VBLANK_CLEAR);
287 } 466 }
288 467
289 return IRQ_HANDLED; 468 return IRQ_HANDLED;
290} 469}
291 470
292static int i915_emit_irq(struct drm_device * dev) 471static int i915_emit_irq(struct drm_device *dev)
293{ 472{
294 drm_i915_private_t *dev_priv = dev->dev_private; 473 drm_i915_private_t *dev_priv = dev->dev_private;
295 RING_LOCALS; 474 RING_LOCALS;
@@ -336,42 +515,12 @@ static int i915_wait_irq(struct drm_device * dev, int irq_nr)
336 READ_BREADCRUMB(dev_priv), (int)dev_priv->counter); 515 READ_BREADCRUMB(dev_priv), (int)dev_priv->counter);
337 } 516 }
338 517
339 dev_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv); 518 if (dev_priv->sarea_priv)
519 dev_priv->sarea_priv->last_dispatch =
520 READ_BREADCRUMB(dev_priv);
340 return ret; 521 return ret;
341} 522}
342 523
343static int i915_driver_vblank_do_wait(struct drm_device *dev, unsigned int *sequence,
344 atomic_t *counter)
345{
346 drm_i915_private_t *dev_priv = dev->dev_private;
347 unsigned int cur_vblank;
348 int ret = 0;
349
350 if (!dev_priv) {
351 DRM_ERROR("called with no initialization\n");
352 return -EINVAL;
353 }
354
355 DRM_WAIT_ON(ret, dev->vbl_queue, 3 * DRM_HZ,
356 (((cur_vblank = atomic_read(counter))
357 - *sequence) <= (1<<23)));
358
359 *sequence = cur_vblank;
360
361 return ret;
362}
363
364
365int i915_driver_vblank_wait(struct drm_device *dev, unsigned int *sequence)
366{
367 return i915_driver_vblank_do_wait(dev, sequence, &dev->vbl_received);
368}
369
370int i915_driver_vblank_wait2(struct drm_device *dev, unsigned int *sequence)
371{
372 return i915_driver_vblank_do_wait(dev, sequence, &dev->vbl_received2);
373}
374
375/* Needs the lock as it touches the ring. 524/* Needs the lock as it touches the ring.
376 */ 525 */
377int i915_irq_emit(struct drm_device *dev, void *data, 526int i915_irq_emit(struct drm_device *dev, void *data,
@@ -414,18 +563,96 @@ int i915_irq_wait(struct drm_device *dev, void *data,
414 return i915_wait_irq(dev, irqwait->irq_seq); 563 return i915_wait_irq(dev, irqwait->irq_seq);
415} 564}
416 565
566int i915_enable_vblank(struct drm_device *dev, int plane)
567{
568 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
569 int pipe = i915_get_pipe(dev, plane);
570 u32 pipestat_reg = 0;
571 u32 pipestat;
572
573 switch (pipe) {
574 case 0:
575 pipestat_reg = I915REG_PIPEASTAT;
576 dev_priv->irq_enable_reg |= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT;
577 break;
578 case 1:
579 pipestat_reg = I915REG_PIPEBSTAT;
580 dev_priv->irq_enable_reg |= I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
581 break;
582 default:
583 DRM_ERROR("tried to enable vblank on non-existent pipe %d\n",
584 pipe);
585 break;
586 }
587
588 if (pipestat_reg)
589 {
590 pipestat = I915_READ (pipestat_reg);
591 /*
592 * Older chips didn't have the start vblank interrupt,
593 * but
594 */
595 if (IS_I965G (dev))
596 pipestat |= I915_START_VBLANK_INTERRUPT_ENABLE;
597 else
598 pipestat |= I915_VBLANK_INTERRUPT_ENABLE;
599 /*
600 * Clear any pending status
601 */
602 pipestat |= (I915_START_VBLANK_INTERRUPT_STATUS |
603 I915_VBLANK_INTERRUPT_STATUS);
604 I915_WRITE(pipestat_reg, pipestat);
605 }
606 I915_WRITE(I915REG_INT_ENABLE_R, dev_priv->irq_enable_reg);
607
608 return 0;
609}
610
611void i915_disable_vblank(struct drm_device *dev, int plane)
612{
613 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
614 int pipe = i915_get_pipe(dev, plane);
615 u32 pipestat_reg = 0;
616 u32 pipestat;
617
618 switch (pipe) {
619 case 0:
620 pipestat_reg = I915REG_PIPEASTAT;
621 dev_priv->irq_enable_reg &= ~I915_DISPLAY_PIPE_A_EVENT_INTERRUPT;
622 break;
623 case 1:
624 pipestat_reg = I915REG_PIPEBSTAT;
625 dev_priv->irq_enable_reg &= ~I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
626 break;
627 default:
628 DRM_ERROR("tried to disable vblank on non-existent pipe %d\n",
629 pipe);
630 break;
631 }
632
633 I915_WRITE(I915REG_INT_ENABLE_R, dev_priv->irq_enable_reg);
634 if (pipestat_reg)
635 {
636 pipestat = I915_READ (pipestat_reg);
637 pipestat &= ~(I915_START_VBLANK_INTERRUPT_ENABLE |
638 I915_VBLANK_INTERRUPT_ENABLE);
639 /*
640 * Clear any pending status
641 */
642 pipestat |= (I915_START_VBLANK_INTERRUPT_STATUS |
643 I915_VBLANK_INTERRUPT_STATUS);
644 I915_WRITE(pipestat_reg, pipestat);
645 }
646}
647
417static void i915_enable_interrupt (struct drm_device *dev) 648static void i915_enable_interrupt (struct drm_device *dev)
418{ 649{
419 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 650 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
420 u16 flag;
421 651
422 flag = 0; 652 dev_priv->irq_enable_reg |= I915_USER_INTERRUPT;
423 if (dev_priv->vblank_pipe & DRM_I915_VBLANK_PIPE_A)
424 flag |= VSYNC_PIPEA_FLAG;
425 if (dev_priv->vblank_pipe & DRM_I915_VBLANK_PIPE_B)
426 flag |= VSYNC_PIPEB_FLAG;
427 653
428 I915_WRITE16(I915REG_INT_ENABLE_R, USER_INT_FLAG | flag); 654 I915_WRITE(I915REG_INT_ENABLE_R, dev_priv->irq_enable_reg);
655 dev_priv->irq_enabled = 1;
429} 656}
430 657
431/* Set the vblank monitor pipe 658/* Set the vblank monitor pipe
@@ -448,8 +675,6 @@ int i915_vblank_pipe_set(struct drm_device *dev, void *data,
448 675
449 dev_priv->vblank_pipe = pipe->pipe; 676 dev_priv->vblank_pipe = pipe->pipe;
450 677
451 i915_enable_interrupt (dev);
452
453 return 0; 678 return 0;
454} 679}
455 680
@@ -467,9 +692,9 @@ int i915_vblank_pipe_get(struct drm_device *dev, void *data,
467 692
468 flag = I915_READ(I915REG_INT_ENABLE_R); 693 flag = I915_READ(I915REG_INT_ENABLE_R);
469 pipe->pipe = 0; 694 pipe->pipe = 0;
470 if (flag & VSYNC_PIPEA_FLAG) 695 if (flag & I915_DISPLAY_PIPE_A_EVENT_INTERRUPT)
471 pipe->pipe |= DRM_I915_VBLANK_PIPE_A; 696 pipe->pipe |= DRM_I915_VBLANK_PIPE_A;
472 if (flag & VSYNC_PIPEB_FLAG) 697 if (flag & I915_DISPLAY_PIPE_B_EVENT_INTERRUPT)
473 pipe->pipe |= DRM_I915_VBLANK_PIPE_B; 698 pipe->pipe |= DRM_I915_VBLANK_PIPE_B;
474 699
475 return 0; 700 return 0;
@@ -484,27 +709,30 @@ int i915_vblank_swap(struct drm_device *dev, void *data,
484 drm_i915_private_t *dev_priv = dev->dev_private; 709 drm_i915_private_t *dev_priv = dev->dev_private;
485 drm_i915_vblank_swap_t *swap = data; 710 drm_i915_vblank_swap_t *swap = data;
486 drm_i915_vbl_swap_t *vbl_swap; 711 drm_i915_vbl_swap_t *vbl_swap;
487 unsigned int pipe, seqtype, curseq; 712 unsigned int pipe, seqtype, curseq, plane;
488 unsigned long irqflags; 713 unsigned long irqflags;
489 struct list_head *list; 714 struct list_head *list;
715 int ret;
490 716
491 if (!dev_priv) { 717 if (!dev_priv) {
492 DRM_ERROR("%s called with no initialization\n", __func__); 718 DRM_ERROR("%s called with no initialization\n", __func__);
493 return -EINVAL; 719 return -EINVAL;
494 } 720 }
495 721
496 if (dev_priv->sarea_priv->rotation) { 722 if (!dev_priv->sarea_priv || dev_priv->sarea_priv->rotation) {
497 DRM_DEBUG("Rotation not supported\n"); 723 DRM_DEBUG("Rotation not supported\n");
498 return -EINVAL; 724 return -EINVAL;
499 } 725 }
500 726
501 if (swap->seqtype & ~(_DRM_VBLANK_RELATIVE | _DRM_VBLANK_ABSOLUTE | 727 if (swap->seqtype & ~(_DRM_VBLANK_RELATIVE | _DRM_VBLANK_ABSOLUTE |
502 _DRM_VBLANK_SECONDARY | _DRM_VBLANK_NEXTONMISS)) { 728 _DRM_VBLANK_SECONDARY | _DRM_VBLANK_NEXTONMISS |
729 _DRM_VBLANK_FLIP)) {
503 DRM_ERROR("Invalid sequence type 0x%x\n", swap->seqtype); 730 DRM_ERROR("Invalid sequence type 0x%x\n", swap->seqtype);
504 return -EINVAL; 731 return -EINVAL;
505 } 732 }
506 733
507 pipe = (swap->seqtype & _DRM_VBLANK_SECONDARY) ? 1 : 0; 734 plane = (swap->seqtype & _DRM_VBLANK_SECONDARY) ? 1 : 0;
735 pipe = i915_get_pipe(dev, plane);
508 736
509 seqtype = swap->seqtype & (_DRM_VBLANK_RELATIVE | _DRM_VBLANK_ABSOLUTE); 737 seqtype = swap->seqtype & (_DRM_VBLANK_RELATIVE | _DRM_VBLANK_ABSOLUTE);
510 738
@@ -515,6 +743,11 @@ int i915_vblank_swap(struct drm_device *dev, void *data,
515 743
516 spin_lock_irqsave(&dev->drw_lock, irqflags); 744 spin_lock_irqsave(&dev->drw_lock, irqflags);
517 745
746 /* It makes no sense to schedule a swap for a drawable that doesn't have
747 * valid information at this point. E.g. this could mean that the X
748 * server is too old to push drawable information to the DRM, in which
749 * case all such swaps would become ineffective.
750 */
518 if (!drm_get_drawable_info(dev, swap->drawable)) { 751 if (!drm_get_drawable_info(dev, swap->drawable)) {
519 spin_unlock_irqrestore(&dev->drw_lock, irqflags); 752 spin_unlock_irqrestore(&dev->drw_lock, irqflags);
520 DRM_DEBUG("Invalid drawable ID %d\n", swap->drawable); 753 DRM_DEBUG("Invalid drawable ID %d\n", swap->drawable);
@@ -523,7 +756,8 @@ int i915_vblank_swap(struct drm_device *dev, void *data,
523 756
524 spin_unlock_irqrestore(&dev->drw_lock, irqflags); 757 spin_unlock_irqrestore(&dev->drw_lock, irqflags);
525 758
526 curseq = atomic_read(pipe ? &dev->vbl_received2 : &dev->vbl_received); 759 drm_update_vblank_count(dev, pipe);
760 curseq = drm_vblank_count(dev, pipe);
527 761
528 if (seqtype == _DRM_VBLANK_RELATIVE) 762 if (seqtype == _DRM_VBLANK_RELATIVE)
529 swap->sequence += curseq; 763 swap->sequence += curseq;
@@ -537,14 +771,43 @@ int i915_vblank_swap(struct drm_device *dev, void *data,
537 } 771 }
538 } 772 }
539 773
774 if (swap->seqtype & _DRM_VBLANK_FLIP) {
775 swap->sequence--;
776
777 if ((curseq - swap->sequence) <= (1<<23)) {
778 struct drm_drawable_info *drw;
779
780 LOCK_TEST_WITH_RETURN(dev, file_priv);
781
782 spin_lock_irqsave(&dev->drw_lock, irqflags);
783
784 drw = drm_get_drawable_info(dev, swap->drawable);
785
786 if (!drw) {
787 spin_unlock_irqrestore(&dev->drw_lock,
788 irqflags);
789 DRM_DEBUG("Invalid drawable ID %d\n",
790 swap->drawable);
791 return -EINVAL;
792 }
793
794 i915_dispatch_vsync_flip(dev, drw, plane);
795
796 spin_unlock_irqrestore(&dev->drw_lock, irqflags);
797
798 return 0;
799 }
800 }
801
540 spin_lock_irqsave(&dev_priv->swaps_lock, irqflags); 802 spin_lock_irqsave(&dev_priv->swaps_lock, irqflags);
541 803
542 list_for_each(list, &dev_priv->vbl_swaps.head) { 804 list_for_each(list, &dev_priv->vbl_swaps.head) {
543 vbl_swap = list_entry(list, drm_i915_vbl_swap_t, head); 805 vbl_swap = list_entry(list, drm_i915_vbl_swap_t, head);
544 806
545 if (vbl_swap->drw_id == swap->drawable && 807 if (vbl_swap->drw_id == swap->drawable &&
546 vbl_swap->pipe == pipe && 808 vbl_swap->plane == plane &&
547 vbl_swap->sequence == swap->sequence) { 809 vbl_swap->sequence == swap->sequence) {
810 vbl_swap->flip = (swap->seqtype & _DRM_VBLANK_FLIP);
548 spin_unlock_irqrestore(&dev_priv->swaps_lock, irqflags); 811 spin_unlock_irqrestore(&dev_priv->swaps_lock, irqflags);
549 DRM_DEBUG("Already scheduled\n"); 812 DRM_DEBUG("Already scheduled\n");
550 return 0; 813 return 0;
@@ -567,9 +830,19 @@ int i915_vblank_swap(struct drm_device *dev, void *data,
567 830
568 DRM_DEBUG("\n"); 831 DRM_DEBUG("\n");
569 832
833 ret = drm_vblank_get(dev, pipe);
834 if (ret) {
835 drm_free(vbl_swap, sizeof(*vbl_swap), DRM_MEM_DRIVER);
836 return ret;
837 }
838
570 vbl_swap->drw_id = swap->drawable; 839 vbl_swap->drw_id = swap->drawable;
571 vbl_swap->pipe = pipe; 840 vbl_swap->plane = plane;
572 vbl_swap->sequence = swap->sequence; 841 vbl_swap->sequence = swap->sequence;
842 vbl_swap->flip = (swap->seqtype & _DRM_VBLANK_FLIP);
843
844 if (vbl_swap->flip)
845 swap->sequence++;
573 846
574 spin_lock_irqsave(&dev_priv->swaps_lock, irqflags); 847 spin_lock_irqsave(&dev_priv->swaps_lock, irqflags);
575 848
@@ -587,37 +860,57 @@ void i915_driver_irq_preinstall(struct drm_device * dev)
587{ 860{
588 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 861 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
589 862
590 I915_WRITE16(I915REG_HWSTAM, 0xfffe); 863 I915_WRITE16(I915REG_HWSTAM, 0xeffe);
591 I915_WRITE16(I915REG_INT_MASK_R, 0x0); 864 I915_WRITE16(I915REG_INT_MASK_R, 0x0);
592 I915_WRITE16(I915REG_INT_ENABLE_R, 0x0); 865 I915_WRITE16(I915REG_INT_ENABLE_R, 0x0);
593} 866}
594 867
595void i915_driver_irq_postinstall(struct drm_device * dev) 868int i915_driver_irq_postinstall(struct drm_device * dev)
596{ 869{
597 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 870 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
871 int ret, num_pipes = 2;
598 872
599 spin_lock_init(&dev_priv->swaps_lock); 873 spin_lock_init(&dev_priv->swaps_lock);
600 INIT_LIST_HEAD(&dev_priv->vbl_swaps.head); 874 INIT_LIST_HEAD(&dev_priv->vbl_swaps.head);
601 dev_priv->swaps_pending = 0; 875 dev_priv->swaps_pending = 0;
602 876
603 if (!dev_priv->vblank_pipe) 877 dev_priv->user_irq_refcount = 0;
604 dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A; 878 dev_priv->irq_enable_reg = 0;
879
880 ret = drm_vblank_init(dev, num_pipes);
881 if (ret)
882 return ret;
883
884 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
885
605 i915_enable_interrupt(dev); 886 i915_enable_interrupt(dev);
606 DRM_INIT_WAITQUEUE(&dev_priv->irq_queue); 887 DRM_INIT_WAITQUEUE(&dev_priv->irq_queue);
888
889 /*
890 * Initialize the hardware status page IRQ location.
891 */
892
893 I915_WRITE(I915REG_INSTPM, (1 << 5) | (1 << 21));
894 return 0;
607} 895}
608 896
609void i915_driver_irq_uninstall(struct drm_device * dev) 897void i915_driver_irq_uninstall(struct drm_device * dev)
610{ 898{
611 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 899 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
612 u16 temp; 900 u32 temp;
613 901
614 if (!dev_priv) 902 if (!dev_priv)
615 return; 903 return;
616 904
617 I915_WRITE16(I915REG_HWSTAM, 0xffff); 905 dev_priv->irq_enabled = 0;
618 I915_WRITE16(I915REG_INT_MASK_R, 0xffff); 906 I915_WRITE(I915REG_HWSTAM, 0xffffffff);
619 I915_WRITE16(I915REG_INT_ENABLE_R, 0x0); 907 I915_WRITE(I915REG_INT_MASK_R, 0xffffffff);
620 908 I915_WRITE(I915REG_INT_ENABLE_R, 0x0);
621 temp = I915_READ16(I915REG_INT_IDENTITY_R); 909
622 I915_WRITE16(I915REG_INT_IDENTITY_R, temp); 910 temp = I915_READ(I915REG_PIPEASTAT);
911 I915_WRITE(I915REG_PIPEASTAT, temp);
912 temp = I915_READ(I915REG_PIPEBSTAT);
913 I915_WRITE(I915REG_PIPEBSTAT, temp);
914 temp = I915_READ(I915REG_INT_IDENTITY_R);
915 I915_WRITE(I915REG_INT_IDENTITY_R, temp);
623} 916}