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authorDave Airlie <airlied@linux.ie>2007-11-04 21:50:58 -0500
committerDave Airlie <airlied@redhat.com>2008-02-07 00:09:38 -0500
commitbc5f4523f772cc7629c5c5a46cf4f2a07a5500b8 (patch)
tree8fa2f5194bb05d7e789e5d24a0fe3a7456568146 /drivers/char/drm/i915_drv.h
parent8562b3f25d6e23c9d9e48a32672944d1e8a2aa97 (diff)
drm: run cleanfile across drm tree
Signed-off-by: Dave Airlie <airlied@linux.ie>
Diffstat (limited to 'drivers/char/drm/i915_drv.h')
-rw-r--r--drivers/char/drm/i915_drv.h50
1 files changed, 25 insertions, 25 deletions
diff --git a/drivers/char/drm/i915_drv.h b/drivers/char/drm/i915_drv.h
index e064292e703a..f8cc71915c8e 100644
--- a/drivers/char/drm/i915_drv.h
+++ b/drivers/char/drm/i915_drv.h
@@ -163,7 +163,7 @@ extern void i915_mem_release(struct drm_device * dev,
163 163
164#define I915_READ(reg) DRM_READ32(dev_priv->mmio_map, (reg)) 164#define I915_READ(reg) DRM_READ32(dev_priv->mmio_map, (reg))
165#define I915_WRITE(reg,val) DRM_WRITE32(dev_priv->mmio_map, (reg), (val)) 165#define I915_WRITE(reg,val) DRM_WRITE32(dev_priv->mmio_map, (reg), (val))
166#define I915_READ16(reg) DRM_READ16(dev_priv->mmio_map, (reg)) 166#define I915_READ16(reg) DRM_READ16(dev_priv->mmio_map, (reg))
167#define I915_WRITE16(reg,val) DRM_WRITE16(dev_priv->mmio_map, (reg), (val)) 167#define I915_WRITE16(reg,val) DRM_WRITE16(dev_priv->mmio_map, (reg), (val))
168 168
169#define I915_VERBOSE 0 169#define I915_VERBOSE 0
@@ -200,7 +200,7 @@ extern void i915_mem_release(struct drm_device * dev,
200 200
201extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller); 201extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
202 202
203#define GFX_OP_USER_INTERRUPT ((0<<29)|(2<<23)) 203#define GFX_OP_USER_INTERRUPT ((0<<29)|(2<<23))
204#define GFX_OP_BREAKPOINT_INTERRUPT ((0<<29)|(1<<23)) 204#define GFX_OP_BREAKPOINT_INTERRUPT ((0<<29)|(1<<23))
205#define CMD_REPORT_HEAD (7<<23) 205#define CMD_REPORT_HEAD (7<<23)
206#define CMD_STORE_DWORD_IDX ((0x21<<23) | 0x1) 206#define CMD_STORE_DWORD_IDX ((0x21<<23) | 0x1)
@@ -217,7 +217,7 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
217 217
218#define I915REG_HWSTAM 0x02098 218#define I915REG_HWSTAM 0x02098
219#define I915REG_INT_IDENTITY_R 0x020a4 219#define I915REG_INT_IDENTITY_R 0x020a4
220#define I915REG_INT_MASK_R 0x020a8 220#define I915REG_INT_MASK_R 0x020a8
221#define I915REG_INT_ENABLE_R 0x020a0 221#define I915REG_INT_ENABLE_R 0x020a0
222 222
223#define I915REG_PIPEASTAT 0x70024 223#define I915REG_PIPEASTAT 0x70024
@@ -229,7 +229,7 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
229#define SRX_INDEX 0x3c4 229#define SRX_INDEX 0x3c4
230#define SRX_DATA 0x3c5 230#define SRX_DATA 0x3c5
231#define SR01 1 231#define SR01 1
232#define SR01_SCREEN_OFF (1<<5) 232#define SR01_SCREEN_OFF (1<<5)
233 233
234#define PPCR 0x61204 234#define PPCR 0x61204
235#define PPCR_ON (1<<0) 235#define PPCR_ON (1<<0)
@@ -249,25 +249,25 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
249#define ADPA_DPMS_OFF (3<<10) 249#define ADPA_DPMS_OFF (3<<10)
250 250
251#define NOPID 0x2094 251#define NOPID 0x2094
252#define LP_RING 0x2030 252#define LP_RING 0x2030
253#define HP_RING 0x2040 253#define HP_RING 0x2040
254#define RING_TAIL 0x00 254#define RING_TAIL 0x00
255#define TAIL_ADDR 0x001FFFF8 255#define TAIL_ADDR 0x001FFFF8
256#define RING_HEAD 0x04 256#define RING_HEAD 0x04
257#define HEAD_WRAP_COUNT 0xFFE00000 257#define HEAD_WRAP_COUNT 0xFFE00000
258#define HEAD_WRAP_ONE 0x00200000 258#define HEAD_WRAP_ONE 0x00200000
259#define HEAD_ADDR 0x001FFFFC 259#define HEAD_ADDR 0x001FFFFC
260#define RING_START 0x08 260#define RING_START 0x08
261#define START_ADDR 0x0xFFFFF000 261#define START_ADDR 0x0xFFFFF000
262#define RING_LEN 0x0C 262#define RING_LEN 0x0C
263#define RING_NR_PAGES 0x001FF000 263#define RING_NR_PAGES 0x001FF000
264#define RING_REPORT_MASK 0x00000006 264#define RING_REPORT_MASK 0x00000006
265#define RING_REPORT_64K 0x00000002 265#define RING_REPORT_64K 0x00000002
266#define RING_REPORT_128K 0x00000004 266#define RING_REPORT_128K 0x00000004
267#define RING_NO_REPORT 0x00000000 267#define RING_NO_REPORT 0x00000000
268#define RING_VALID_MASK 0x00000001 268#define RING_VALID_MASK 0x00000001
269#define RING_VALID 0x00000001 269#define RING_VALID 0x00000001
270#define RING_INVALID 0x00000000 270#define RING_INVALID 0x00000000
271 271
272#define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19)) 272#define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19))
273#define SC_UPDATE_SCISSOR (0x1<<1) 273#define SC_UPDATE_SCISSOR (0x1<<1)
@@ -294,9 +294,9 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
294#define XY_SRC_COPY_BLT_WRITE_ALPHA (1<<21) 294#define XY_SRC_COPY_BLT_WRITE_ALPHA (1<<21)
295#define XY_SRC_COPY_BLT_WRITE_RGB (1<<20) 295#define XY_SRC_COPY_BLT_WRITE_RGB (1<<20)
296 296
297#define MI_BATCH_BUFFER ((0x30<<23)|1) 297#define MI_BATCH_BUFFER ((0x30<<23)|1)
298#define MI_BATCH_BUFFER_START (0x31<<23) 298#define MI_BATCH_BUFFER_START (0x31<<23)
299#define MI_BATCH_BUFFER_END (0xA<<23) 299#define MI_BATCH_BUFFER_END (0xA<<23)
300#define MI_BATCH_NON_SECURE (1) 300#define MI_BATCH_NON_SECURE (1)
301#define MI_BATCH_NON_SECURE_I965 (1<<8) 301#define MI_BATCH_NON_SECURE_I965 (1<<8)
302 302