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authorWang Zhenyu <zhenyu.z.wang@intel.com>2007-06-10 01:58:19 -0400
committerDave Airlie <airlied@linux.ie>2007-06-10 01:58:19 -0400
commitdc7a93190c21edbf3ed23e678ad04f852b9cff28 (patch)
treecc05781518d289b91b4da869881273205fe7ccb1 /drivers/char/drm/i915_drm.h
parent2f4042b186b9bfe82f48fe801619c6c285c16bef (diff)
drm/i915: Add support for the G33, Q33, and Q35 chipsets.
These require that the status page be referenced by a pointer in GTT, rather than phsyical memory. So, we have the X Server allocate that memory and tell us the address, instead. Signed-off-by: Dave Airlie <airlied@linux.ie>
Diffstat (limited to 'drivers/char/drm/i915_drm.h')
-rw-r--r--drivers/char/drm/i915_drm.h5
1 files changed, 5 insertions, 0 deletions
diff --git a/drivers/char/drm/i915_drm.h b/drivers/char/drm/i915_drm.h
index 96a468886a7a..7b7b68b96f31 100644
--- a/drivers/char/drm/i915_drm.h
+++ b/drivers/char/drm/i915_drm.h
@@ -142,6 +142,7 @@ typedef struct _drm_i915_sarea {
142#define DRM_I915_SET_VBLANK_PIPE 0x0d 142#define DRM_I915_SET_VBLANK_PIPE 0x0d
143#define DRM_I915_GET_VBLANK_PIPE 0x0e 143#define DRM_I915_GET_VBLANK_PIPE 0x0e
144#define DRM_I915_VBLANK_SWAP 0x0f 144#define DRM_I915_VBLANK_SWAP 0x0f
145#define DRM_I915_HWS_ADDR 0x11
145 146
146#define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t) 147#define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
147#define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH) 148#define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
@@ -262,4 +263,8 @@ typedef struct drm_i915_vblank_swap {
262 unsigned int sequence; 263 unsigned int sequence;
263} drm_i915_vblank_swap_t; 264} drm_i915_vblank_swap_t;
264 265
266typedef struct drm_i915_hws_addr {
267 uint64_t addr;
268} drm_i915_hws_addr_t;
269
265#endif /* _I915_DRM_H_ */ 270#endif /* _I915_DRM_H_ */