diff options
author | Zhenyu Wang <zhenyu.z.wang@intel.com> | 2008-02-19 05:59:09 -0500 |
---|---|---|
committer | Dave Airlie <airlied@redhat.com> | 2008-02-19 18:37:09 -0500 |
commit | b39d50e53b1bb27f6c29f88a697a4af78427dffd (patch) | |
tree | 1a38bfdeb6c1de8df69eb11bb1a8f36cdf8f28fd /drivers/char/drm/i915_dma.c | |
parent | 60f92683943c5b7a85963b283d6f8a853aa09203 (diff) |
i915: wrap chipset types requiring hw status set ioctl
Also applys to recent added new chipset.
Signed-off-by: Zhenyu Wang <zhenyu.z.wang@intel.com>
Signed-off-by: Dave Airlie <airlied@linux.ie>
Diffstat (limited to 'drivers/char/drm/i915_dma.c')
-rw-r--r-- | drivers/char/drm/i915_dma.c | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/drivers/char/drm/i915_dma.c b/drivers/char/drm/i915_dma.c index 43986d81ae34..e9d6663bec73 100644 --- a/drivers/char/drm/i915_dma.c +++ b/drivers/char/drm/i915_dma.c | |||
@@ -171,7 +171,7 @@ static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init) | |||
171 | dev_priv->allow_batchbuffer = 1; | 171 | dev_priv->allow_batchbuffer = 1; |
172 | 172 | ||
173 | /* Program Hardware Status Page */ | 173 | /* Program Hardware Status Page */ |
174 | if (!IS_G33(dev)) { | 174 | if (!I915_NEED_GFX_HWS(dev)) { |
175 | dev_priv->status_page_dmah = | 175 | dev_priv->status_page_dmah = |
176 | drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE, 0xffffffff); | 176 | drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE, 0xffffffff); |
177 | 177 | ||
@@ -720,6 +720,9 @@ static int i915_set_status_page(struct drm_device *dev, void *data, | |||
720 | drm_i915_private_t *dev_priv = dev->dev_private; | 720 | drm_i915_private_t *dev_priv = dev->dev_private; |
721 | drm_i915_hws_addr_t *hws = data; | 721 | drm_i915_hws_addr_t *hws = data; |
722 | 722 | ||
723 | if (!I915_NEED_GFX_HWS(dev)) | ||
724 | return -EINVAL; | ||
725 | |||
723 | if (!dev_priv) { | 726 | if (!dev_priv) { |
724 | DRM_ERROR("called with no initialization\n"); | 727 | DRM_ERROR("called with no initialization\n"); |
725 | return -EINVAL; | 728 | return -EINVAL; |