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authorDave Airlie <airlied@starflyer.(none)>2005-09-25 00:28:13 -0400
committerDave Airlie <airlied@linux.ie>2005-09-25 00:28:13 -0400
commitb5e89ed53ed8d24f83ba1941c07382af00ed238e (patch)
tree747bae7a565f88a2e1d5974776eeb054a932c505 /drivers/char/drm/i810_drm.h
parent99a2657a29e2d623c3568cd86b27cac13fb63140 (diff)
drm: lindent the drm directory.
I've been threatening this for a while, so no point hanging around. This lindents the DRM code which was always really bad in tabbing department. I've also fixed some misnamed files in comments and removed some trailing whitespace. Signed-off-by: Dave Airlie <airlied@linux.ie>
Diffstat (limited to 'drivers/char/drm/i810_drm.h')
-rw-r--r--drivers/char/drm/i810_drm.h75
1 files changed, 36 insertions, 39 deletions
diff --git a/drivers/char/drm/i810_drm.h b/drivers/char/drm/i810_drm.h
index 73ac40563b1d..2deb925a94f3 100644
--- a/drivers/char/drm/i810_drm.h
+++ b/drivers/char/drm/i810_drm.h
@@ -19,21 +19,20 @@
19#define I810_LOG_MIN_TEX_REGION_SIZE 16 19#define I810_LOG_MIN_TEX_REGION_SIZE 16
20#endif 20#endif
21 21
22#define I810_UPLOAD_TEX0IMAGE 0x1 /* handled clientside */ 22#define I810_UPLOAD_TEX0IMAGE 0x1 /* handled clientside */
23#define I810_UPLOAD_TEX1IMAGE 0x2 /* handled clientside */ 23#define I810_UPLOAD_TEX1IMAGE 0x2 /* handled clientside */
24#define I810_UPLOAD_CTX 0x4 24#define I810_UPLOAD_CTX 0x4
25#define I810_UPLOAD_BUFFERS 0x8 25#define I810_UPLOAD_BUFFERS 0x8
26#define I810_UPLOAD_TEX0 0x10 26#define I810_UPLOAD_TEX0 0x10
27#define I810_UPLOAD_TEX1 0x20 27#define I810_UPLOAD_TEX1 0x20
28#define I810_UPLOAD_CLIPRECTS 0x40 28#define I810_UPLOAD_CLIPRECTS 0x40
29 29
30
31/* Indices into buf.Setup where various bits of state are mirrored per 30/* Indices into buf.Setup where various bits of state are mirrored per
32 * context and per buffer. These can be fired at the card as a unit, 31 * context and per buffer. These can be fired at the card as a unit,
33 * or in a piecewise fashion as required. 32 * or in a piecewise fashion as required.
34 */ 33 */
35 34
36/* Destbuffer state 35/* Destbuffer state
37 * - backbuffer linear offset and pitch -- invarient in the current dri 36 * - backbuffer linear offset and pitch -- invarient in the current dri
38 * - zbuffer linear offset and pitch -- also invarient 37 * - zbuffer linear offset and pitch -- also invarient
39 * - drawing origin in back and depth buffers. 38 * - drawing origin in back and depth buffers.
@@ -55,13 +54,13 @@
55/* Context state 54/* Context state
56 */ 55 */
57#define I810_CTXREG_CF0 0 /* GFX_OP_COLOR_FACTOR */ 56#define I810_CTXREG_CF0 0 /* GFX_OP_COLOR_FACTOR */
58#define I810_CTXREG_CF1 1 57#define I810_CTXREG_CF1 1
59#define I810_CTXREG_ST0 2 /* GFX_OP_STIPPLE */ 58#define I810_CTXREG_ST0 2 /* GFX_OP_STIPPLE */
60#define I810_CTXREG_ST1 3 59#define I810_CTXREG_ST1 3
61#define I810_CTXREG_VF 4 /* GFX_OP_VERTEX_FMT */ 60#define I810_CTXREG_VF 4 /* GFX_OP_VERTEX_FMT */
62#define I810_CTXREG_MT 5 /* GFX_OP_MAP_TEXELS */ 61#define I810_CTXREG_MT 5 /* GFX_OP_MAP_TEXELS */
63#define I810_CTXREG_MC0 6 /* GFX_OP_MAP_COLOR_STAGES - stage 0 */ 62#define I810_CTXREG_MC0 6 /* GFX_OP_MAP_COLOR_STAGES - stage 0 */
64#define I810_CTXREG_MC1 7 /* GFX_OP_MAP_COLOR_STAGES - stage 1 */ 63#define I810_CTXREG_MC1 7 /* GFX_OP_MAP_COLOR_STAGES - stage 1 */
65#define I810_CTXREG_MC2 8 /* GFX_OP_MAP_COLOR_STAGES - stage 2 */ 64#define I810_CTXREG_MC2 8 /* GFX_OP_MAP_COLOR_STAGES - stage 2 */
66#define I810_CTXREG_MA0 9 /* GFX_OP_MAP_ALPHA_STAGES - stage 0 */ 65#define I810_CTXREG_MA0 9 /* GFX_OP_MAP_ALPHA_STAGES - stage 0 */
67#define I810_CTXREG_MA1 10 /* GFX_OP_MAP_ALPHA_STAGES - stage 1 */ 66#define I810_CTXREG_MA1 10 /* GFX_OP_MAP_ALPHA_STAGES - stage 1 */
@@ -74,14 +73,14 @@
74#define I810_CTXREG_PV 17 /* GFX_OP_PV_RULE -- Invarient! */ 73#define I810_CTXREG_PV 17 /* GFX_OP_PV_RULE -- Invarient! */
75#define I810_CTXREG_ZA 18 /* GFX_OP_ZBIAS_ALPHAFUNC */ 74#define I810_CTXREG_ZA 18 /* GFX_OP_ZBIAS_ALPHAFUNC */
76#define I810_CTXREG_AA 19 /* GFX_OP_ANTIALIAS */ 75#define I810_CTXREG_AA 19 /* GFX_OP_ANTIALIAS */
77#define I810_CTX_SETUP_SIZE 20 76#define I810_CTX_SETUP_SIZE 20
78 77
79/* Texture state (per tex unit) 78/* Texture state (per tex unit)
80 */ 79 */
81#define I810_TEXREG_MI0 0 /* GFX_OP_MAP_INFO (4 dwords) */ 80#define I810_TEXREG_MI0 0 /* GFX_OP_MAP_INFO (4 dwords) */
82#define I810_TEXREG_MI1 1 81#define I810_TEXREG_MI1 1
83#define I810_TEXREG_MI2 2 82#define I810_TEXREG_MI2 2
84#define I810_TEXREG_MI3 3 83#define I810_TEXREG_MI3 3
85#define I810_TEXREG_MF 4 /* GFX_OP_MAP_FILTER */ 84#define I810_TEXREG_MF 4 /* GFX_OP_MAP_FILTER */
86#define I810_TEXREG_MLC 5 /* GFX_OP_MAP_LOD_CTL */ 85#define I810_TEXREG_MLC 5 /* GFX_OP_MAP_LOD_CTL */
87#define I810_TEXREG_MLL 6 /* GFX_OP_MAP_LOD_LIMITS */ 86#define I810_TEXREG_MLL 6 /* GFX_OP_MAP_LOD_LIMITS */
@@ -98,7 +97,7 @@ typedef enum _drm_i810_init_func {
98 I810_INIT_DMA = 0x01, 97 I810_INIT_DMA = 0x01,
99 I810_CLEANUP_DMA = 0x02, 98 I810_CLEANUP_DMA = 0x02,
100 I810_INIT_DMA_1_4 = 0x03 99 I810_INIT_DMA_1_4 = 0x03
101 } drm_i810_init_func_t; 100} drm_i810_init_func_t;
102 101
103/* This is the init structure after v1.2 */ 102/* This is the init structure after v1.2 */
104typedef struct _drm_i810_init { 103typedef struct _drm_i810_init {
@@ -122,7 +121,7 @@ typedef struct _drm_i810_init {
122 unsigned int w; 121 unsigned int w;
123 unsigned int h; 122 unsigned int h;
124 unsigned int pitch; 123 unsigned int pitch;
125 unsigned int pitch_bits; 124 unsigned int pitch_bits;
126} drm_i810_init_t; 125} drm_i810_init_t;
127 126
128/* This is the init structure prior to v1.2 */ 127/* This is the init structure prior to v1.2 */
@@ -140,23 +139,23 @@ typedef struct _drm_i810_pre12_init {
140 unsigned int w; 139 unsigned int w;
141 unsigned int h; 140 unsigned int h;
142 unsigned int pitch; 141 unsigned int pitch;
143 unsigned int pitch_bits; 142 unsigned int pitch_bits;
144} drm_i810_pre12_init_t; 143} drm_i810_pre12_init_t;
145 144
146/* Warning: If you change the SAREA structure you must change the Xserver 145/* Warning: If you change the SAREA structure you must change the Xserver
147 * structure as well */ 146 * structure as well */
148 147
149typedef struct _drm_i810_tex_region { 148typedef struct _drm_i810_tex_region {
150 unsigned char next, prev; /* indices to form a circular LRU */ 149 unsigned char next, prev; /* indices to form a circular LRU */
151 unsigned char in_use; /* owned by a client, or free? */ 150 unsigned char in_use; /* owned by a client, or free? */
152 int age; /* tracked by clients to update local LRU's */ 151 int age; /* tracked by clients to update local LRU's */
153} drm_i810_tex_region_t; 152} drm_i810_tex_region_t;
154 153
155typedef struct _drm_i810_sarea { 154typedef struct _drm_i810_sarea {
156 unsigned int ContextState[I810_CTX_SETUP_SIZE]; 155 unsigned int ContextState[I810_CTX_SETUP_SIZE];
157 unsigned int BufferState[I810_DEST_SETUP_SIZE]; 156 unsigned int BufferState[I810_DEST_SETUP_SIZE];
158 unsigned int TexState[2][I810_TEX_SETUP_SIZE]; 157 unsigned int TexState[2][I810_TEX_SETUP_SIZE];
159 unsigned int dirty; 158 unsigned int dirty;
160 159
161 unsigned int nbox; 160 unsigned int nbox;
162 drm_clip_rect_t boxes[I810_NR_SAREA_CLIPRECTS]; 161 drm_clip_rect_t boxes[I810_NR_SAREA_CLIPRECTS];
@@ -174,22 +173,22 @@ typedef struct _drm_i810_sarea {
174 * texture space, and can make informed decisions as to which 173 * texture space, and can make informed decisions as to which
175 * areas to kick out. There is no need to choose whether to 174 * areas to kick out. There is no need to choose whether to
176 * kick out your own texture or someone else's - simply eject 175 * kick out your own texture or someone else's - simply eject
177 * them all in LRU order. 176 * them all in LRU order.
178 */ 177 */
179 178
180 drm_i810_tex_region_t texList[I810_NR_TEX_REGIONS+1]; 179 drm_i810_tex_region_t texList[I810_NR_TEX_REGIONS + 1];
181 /* Last elt is sentinal */ 180 /* Last elt is sentinal */
182 int texAge; /* last time texture was uploaded */ 181 int texAge; /* last time texture was uploaded */
183 int last_enqueue; /* last time a buffer was enqueued */ 182 int last_enqueue; /* last time a buffer was enqueued */
184 int last_dispatch; /* age of the most recently dispatched buffer */ 183 int last_dispatch; /* age of the most recently dispatched buffer */
185 int last_quiescent; /* */ 184 int last_quiescent; /* */
186 int ctxOwner; /* last context to upload state */ 185 int ctxOwner; /* last context to upload state */
187 186
188 int vertex_prim; 187 int vertex_prim;
189 188
190 int pf_enabled; /* is pageflipping allowed? */ 189 int pf_enabled; /* is pageflipping allowed? */
191 int pf_active; 190 int pf_active;
192 int pf_current_page; /* which buffer is being displayed? */ 191 int pf_current_page; /* which buffer is being displayed? */
193} drm_i810_sarea_t; 192} drm_i810_sarea_t;
194 193
195/* WARNING: If you change any of these defines, make sure to change the 194/* WARNING: If you change any of these defines, make sure to change the
@@ -243,13 +242,13 @@ typedef struct _drm_i810_clear {
243 * new set of cliprects. 242 * new set of cliprects.
244 */ 243 */
245typedef struct _drm_i810_vertex { 244typedef struct _drm_i810_vertex {
246 int idx; /* buffer index */ 245 int idx; /* buffer index */
247 int used; /* nr bytes in use */ 246 int used; /* nr bytes in use */
248 int discard; /* client is finished with the buffer? */ 247 int discard; /* client is finished with the buffer? */
249} drm_i810_vertex_t; 248} drm_i810_vertex_t;
250 249
251typedef struct _drm_i810_copy_t { 250typedef struct _drm_i810_copy_t {
252 int idx; /* buffer index */ 251 int idx; /* buffer index */
253 int used; /* nr bytes in use */ 252 int used; /* nr bytes in use */
254 void *address; /* Address to copy from */ 253 void *address; /* Address to copy from */
255} drm_i810_copy_t; 254} drm_i810_copy_t;
@@ -264,7 +263,6 @@ typedef struct _drm_i810_copy_t {
264#define PR_RECTS (0x7<<18) 263#define PR_RECTS (0x7<<18)
265#define PR_MASK (0x7<<18) 264#define PR_MASK (0x7<<18)
266 265
267
268typedef struct drm_i810_dma { 266typedef struct drm_i810_dma {
269 void *virtual; 267 void *virtual;
270 int request_idx; 268 int request_idx;
@@ -273,17 +271,16 @@ typedef struct drm_i810_dma {
273} drm_i810_dma_t; 271} drm_i810_dma_t;
274 272
275typedef struct _drm_i810_overlay_t { 273typedef struct _drm_i810_overlay_t {
276 unsigned int offset; /* Address of the Overlay Regs */ 274 unsigned int offset; /* Address of the Overlay Regs */
277 unsigned int physical; 275 unsigned int physical;
278} drm_i810_overlay_t; 276} drm_i810_overlay_t;
279 277
280typedef struct _drm_i810_mc { 278typedef struct _drm_i810_mc {
281 int idx; /* buffer index */ 279 int idx; /* buffer index */
282 int used; /* nr bytes in use */ 280 int used; /* nr bytes in use */
283 int num_blocks; /* number of GFXBlocks */ 281 int num_blocks; /* number of GFXBlocks */
284 int *length; /* List of lengths for GFXBlocks (FUTURE)*/ 282 int *length; /* List of lengths for GFXBlocks (FUTURE) */
285 unsigned int last_render; /* Last Render Request */ 283 unsigned int last_render; /* Last Render Request */
286} drm_i810_mc_t; 284} drm_i810_mc_t;
287 285
288 286#endif /* _I810_DRM_H_ */
289#endif /* _I810_DRM_H_ */