diff options
author | Bjorn Helgaas <bhelgaas@google.com> | 2014-01-03 20:29:00 -0500 |
---|---|---|
committer | Bjorn Helgaas <bhelgaas@google.com> | 2014-01-07 13:37:12 -0500 |
commit | b5e350f919acb8ef6961bc1b62e395f53cea123a (patch) | |
tree | ef77989abe076f705ba5d27f87e2d9e4e6cfccaa /drivers/char/agp | |
parent | 5ef6d8f49533bb28a90ae9eec177ffd1ade54267 (diff) |
agp/intel: Use pci_bus_address() to get GTTADR bus address
Per the Intel 915G/915GV/... Chipset spec (document number 301467-005),
GTTADR is a standard PCI BAR.
The PCI core reads GTTADR at enumeration-time. Use pci_bus_address()
instead of reading it again in the driver. This works correctly for both
32-bit and 64-bit BARs. The spec above only mentions 32-bit GTTADR, but we
should still use the standard interface.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/char/agp')
-rw-r--r-- | drivers/char/agp/intel-agp.h | 2 | ||||
-rw-r--r-- | drivers/char/agp/intel-gtt.c | 7 |
2 files changed, 4 insertions, 5 deletions
diff --git a/drivers/char/agp/intel-agp.h b/drivers/char/agp/intel-agp.h index 18bbaafb8509..fda073dcd967 100644 --- a/drivers/char/agp/intel-agp.h +++ b/drivers/char/agp/intel-agp.h | |||
@@ -115,7 +115,7 @@ | |||
115 | /* intel 915G registers */ | 115 | /* intel 915G registers */ |
116 | #define I915_GMADR_BAR 2 | 116 | #define I915_GMADR_BAR 2 |
117 | #define I915_MMADR_BAR 0 | 117 | #define I915_MMADR_BAR 0 |
118 | #define I915_PTEADDR 0x1C | 118 | #define I915_PTE_BAR 3 |
119 | #define I915_GMCH_GMS_STOLEN_48M (0x6 << 4) | 119 | #define I915_GMCH_GMS_STOLEN_48M (0x6 << 4) |
120 | #define I915_GMCH_GMS_STOLEN_64M (0x7 << 4) | 120 | #define I915_GMCH_GMS_STOLEN_64M (0x7 << 4) |
121 | #define G33_GMCH_GMS_STOLEN_128M (0x8 << 4) | 121 | #define G33_GMCH_GMS_STOLEN_128M (0x8 << 4) |
diff --git a/drivers/char/agp/intel-gtt.c b/drivers/char/agp/intel-gtt.c index 58916f32c0f3..dd8b66a617dc 100644 --- a/drivers/char/agp/intel-gtt.c +++ b/drivers/char/agp/intel-gtt.c | |||
@@ -1102,7 +1102,7 @@ static void i965_write_entry(dma_addr_t addr, | |||
1102 | 1102 | ||
1103 | static int i9xx_setup(void) | 1103 | static int i9xx_setup(void) |
1104 | { | 1104 | { |
1105 | u32 reg_addr, gtt_addr; | 1105 | u32 reg_addr; |
1106 | int size = KB(512); | 1106 | int size = KB(512); |
1107 | 1107 | ||
1108 | reg_addr = pci_bus_address(intel_private.pcidev, I915_MMADR_BAR); | 1108 | reg_addr = pci_bus_address(intel_private.pcidev, I915_MMADR_BAR); |
@@ -1113,9 +1113,8 @@ static int i9xx_setup(void) | |||
1113 | 1113 | ||
1114 | switch (INTEL_GTT_GEN) { | 1114 | switch (INTEL_GTT_GEN) { |
1115 | case 3: | 1115 | case 3: |
1116 | pci_read_config_dword(intel_private.pcidev, | 1116 | intel_private.gtt_phys_addr = |
1117 | I915_PTEADDR, >t_addr); | 1117 | pci_bus_address(intel_private.pcidev, I915_PTE_BAR); |
1118 | intel_private.gtt_phys_addr = gtt_addr; | ||
1119 | break; | 1118 | break; |
1120 | case 5: | 1119 | case 5: |
1121 | intel_private.gtt_phys_addr = reg_addr + MB(2); | 1120 | intel_private.gtt_phys_addr = reg_addr + MB(2); |