Merge commit 'linux-2.6/master' (early part) into oprofile/core

This branch depends on these apic patches:

      apic, x86: Use BIOS settings for IBS and MCE threshold interrupt LVT offsets
      apic, x86: Check if EILVT APIC registers are available (AMD only)

Signed-off-by: Robert Richter <robert.richter@amd.com>

3 files changed, 30 insertions, 15 deletions

diff --git a/drivers/char/agp/Kconfig b/drivers/char/agp/Kconfig
index 4b66c69eaf57..5ddf67e76f8b 100644
--- a/drivers/char/agp/Kconfig
+++ b/drivers/char/agp/Kconfig
@@ -57,7 +57,7 @@ config AGP_AMD
 
 config AGP_AMD64
         tristate "AMD Opteron/Athlon64 on-CPU GART support"
-        depends on AGP && X86 && K8_NB
+        depends on AGP && X86 && AMD_NB
         help
           This option gives you AGP support for the GLX component of
           X using the on-CPU northbridge of the AMD Athlon64/Opteron CPUs.
diff --git a/drivers/char/agp/amd64-agp.c b/drivers/char/agp/amd64-agp.c
index 70312da4c968..42396df55556 100644
--- a/drivers/char/agp/amd64-agp.c
+++ b/drivers/char/agp/amd64-agp.c
@@ -15,7 +15,7 @@
 #include <linux/mmzone.h>
 #include <asm/page.h>           /* PAGE_SIZE */
 #include <asm/e820.h>
-#include <asm/k8.h>
+#include <asm/amd_nb.h>
 #include <asm/gart.h>
 #include "agp.h"
 
@@ -124,7 +124,7 @@ static int amd64_fetch_size(void)
         u32 temp;
         struct aper_size_info_32 *values;
 
-        dev = k8_northbridges[0];
+        dev = k8_northbridges.nb_misc[0];
         if (dev==NULL)
                 return 0;
 
@@ -181,10 +181,14 @@ static int amd_8151_configure(void)
         unsigned long gatt_bus = virt_to_phys(agp_bridge->gatt_table_real);
         int i;
 
+        if (!k8_northbridges.gart_supported)
+                return 0;
+
         /* Configure AGP regs in each x86-64 host bridge. */
-        for (i = 0; i < num_k8_northbridges; i++) {
+        for (i = 0; i < k8_northbridges.num; i++) {
                 agp_bridge->gart_bus_addr =
-                                amd64_configure(k8_northbridges[i], gatt_bus);
+                                amd64_configure(k8_northbridges.nb_misc[i],
+                                                gatt_bus);
         }
         k8_flush_garts();
         return 0;
@@ -195,11 +199,15 @@ static void amd64_cleanup(void)
 {
         u32 tmp;
         int i;
-        for (i = 0; i < num_k8_northbridges; i++) {
-                struct pci_dev *dev = k8_northbridges[i];
+
+        if (!k8_northbridges.gart_supported)
+                return;
+
+        for (i = 0; i < k8_northbridges.num; i++) {
+                struct pci_dev *dev = k8_northbridges.nb_misc[i];
                 /* disable gart translation */
                 pci_read_config_dword(dev, AMD64_GARTAPERTURECTL, &tmp);
-                tmp &= ~AMD64_GARTEN;
+                tmp &= ~GARTEN;
                 pci_write_config_dword(dev, AMD64_GARTAPERTURECTL, tmp);
         }
 }
@@ -313,22 +321,25 @@ static __devinit int fix_northbridge(struct pci_dev *nb, struct pci_dev *agp,
         if (order < 0 || !agp_aperture_valid(aper, (32*1024*1024)<<order))
                 return -1;
 
-        pci_write_config_dword(nb, AMD64_GARTAPERTURECTL, order << 1);
+        gart_set_size_and_enable(nb, order);
         pci_write_config_dword(nb, AMD64_GARTAPERTUREBASE, aper >> 25);
 
         return 0;
 }
 
-static __devinit int cache_nbs (struct pci_dev *pdev, u32 cap_ptr)
+static __devinit int cache_nbs(struct pci_dev *pdev, u32 cap_ptr)
 {
         int i;
 
         if (cache_k8_northbridges() < 0)
                 return -ENODEV;
 
+        if (!k8_northbridges.gart_supported)
+                return -ENODEV;
+
         i = 0;
-        for (i = 0; i < num_k8_northbridges; i++) {
-                struct pci_dev *dev = k8_northbridges[i];
+        for (i = 0; i < k8_northbridges.num; i++) {
+                struct pci_dev *dev = k8_northbridges.nb_misc[i];
                 if (fix_northbridge(dev, pdev, cap_ptr) < 0) {
                         dev_err(&dev->dev, "no usable aperture found\n");
 #ifdef __x86_64__
@@ -405,7 +416,8 @@ static int __devinit uli_agp_init(struct pci_dev *pdev)
         }
 
         /* shadow x86-64 registers into ULi registers */
-        pci_read_config_dword (k8_northbridges[0], AMD64_GARTAPERTUREBASE, &httfea);
+        pci_read_config_dword (k8_northbridges.nb_misc[0], AMD64_GARTAPERTUREBASE,
+                               &httfea);
 
         /* if x86-64 aperture base is beyond 4G, exit here */
         if ((httfea & 0x7fff) >> (32 - 25)) {
@@ -472,7 +484,8 @@ static int nforce3_agp_init(struct pci_dev *pdev)
         pci_write_config_dword(dev1, NVIDIA_X86_64_1_APSIZE, tmp);
 
         /* shadow x86-64 registers into NVIDIA registers */
-        pci_read_config_dword (k8_northbridges[0], AMD64_GARTAPERTUREBASE, &apbase);
+        pci_read_config_dword (k8_northbridges.nb_misc[0], AMD64_GARTAPERTUREBASE,
+                               &apbase);
 
         /* if x86-64 aperture base is beyond 4G, exit here */
         if ( (apbase & 0x7fff) >> (32 - 25) ) {
diff --git a/drivers/char/agp/generic.c b/drivers/char/agp/generic.c
index d2abf5143983..64255cef8a7d 100644
--- a/drivers/char/agp/generic.c
+++ b/drivers/char/agp/generic.c
@@ -984,7 +984,9 @@ int agp_generic_create_gatt_table(struct agp_bridge_data *bridge)
 
         bridge->driver->cache_flush();
 #ifdef CONFIG_X86
-        set_memory_uc((unsigned long)table, 1 << page_order);
+        if (set_memory_uc((unsigned long)table, 1 << page_order))
+                printk(KERN_WARNING "Could not set GATT table memory to UC!");
+
         bridge->gatt_table = (void *)table;
 #else
         bridge->gatt_table = ioremap_nocache(virt_to_phys(table),