diff options
author | Wang Zhenyu <zhenyu.z.wang@intel.com> | 2007-05-29 21:40:46 -0400 |
---|---|---|
committer | Dave Jones <davej@redhat.com> | 2007-06-06 17:10:02 -0400 |
commit | c4ca881796b7e14120851ddf6e04845ef94a314a (patch) | |
tree | bac606ea455f9c2f2f6e0c0952a5711d4530e200 /drivers/char/agp | |
parent | bbdfff86a8f0c91ad8b6dedf74bc14de4ba39679 (diff) |
[AGPGART] intel_agp: cleanup intel private data
Remove volatile type declare for IO mem variables.
A single private gart data is used by all drivers, this
makes it clean. Eric Anholt wrote the original patch.
Signed-off-by: Wang Zhenyu <zhenyu.z.wang@intel.com>
Signed-off-by: Dave Jones <davej@redhat.com>
Diffstat (limited to 'drivers/char/agp')
-rw-r--r-- | drivers/char/agp/intel-agp.c | 195 |
1 files changed, 91 insertions, 104 deletions
diff --git a/drivers/char/agp/intel-agp.c b/drivers/char/agp/intel-agp.c index 9c69f2e761f5..e12f579ecf46 100644 --- a/drivers/char/agp/intel-agp.c +++ b/drivers/char/agp/intel-agp.c | |||
@@ -86,11 +86,18 @@ static struct gatt_mask intel_i810_masks[] = | |||
86 | .type = INTEL_AGP_CACHED_MEMORY} | 86 | .type = INTEL_AGP_CACHED_MEMORY} |
87 | }; | 87 | }; |
88 | 88 | ||
89 | static struct _intel_i810_private { | 89 | static struct _intel_private { |
90 | struct pci_dev *i810_dev; /* device one */ | 90 | struct pci_dev *pcidev; /* device one */ |
91 | volatile u8 __iomem *registers; | 91 | u8 __iomem *registers; |
92 | u32 __iomem *gtt; /* I915G */ | ||
92 | int num_dcache_entries; | 93 | int num_dcache_entries; |
93 | } intel_i810_private; | 94 | /* gtt_entries is the number of gtt entries that are already mapped |
95 | * to stolen memory. Stolen memory is larger than the memory mapped | ||
96 | * through gtt_entries, as it includes some reserved space for the BIOS | ||
97 | * popup and for the GTT. | ||
98 | */ | ||
99 | int gtt_entries; /* i830+ */ | ||
100 | } intel_private; | ||
94 | 101 | ||
95 | static int intel_i810_fetch_size(void) | 102 | static int intel_i810_fetch_size(void) |
96 | { | 103 | { |
@@ -127,32 +134,32 @@ static int intel_i810_configure(void) | |||
127 | 134 | ||
128 | current_size = A_SIZE_FIX(agp_bridge->current_size); | 135 | current_size = A_SIZE_FIX(agp_bridge->current_size); |
129 | 136 | ||
130 | if (!intel_i810_private.registers) { | 137 | if (!intel_private.registers) { |
131 | pci_read_config_dword(intel_i810_private.i810_dev, I810_MMADDR, &temp); | 138 | pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &temp); |
132 | temp &= 0xfff80000; | 139 | temp &= 0xfff80000; |
133 | 140 | ||
134 | intel_i810_private.registers = ioremap(temp, 128 * 4096); | 141 | intel_private.registers = ioremap(temp, 128 * 4096); |
135 | if (!intel_i810_private.registers) { | 142 | if (!intel_private.registers) { |
136 | printk(KERN_ERR PFX "Unable to remap memory.\n"); | 143 | printk(KERN_ERR PFX "Unable to remap memory.\n"); |
137 | return -ENOMEM; | 144 | return -ENOMEM; |
138 | } | 145 | } |
139 | } | 146 | } |
140 | 147 | ||
141 | if ((readl(intel_i810_private.registers+I810_DRAM_CTL) | 148 | if ((readl(intel_private.registers+I810_DRAM_CTL) |
142 | & I810_DRAM_ROW_0) == I810_DRAM_ROW_0_SDRAM) { | 149 | & I810_DRAM_ROW_0) == I810_DRAM_ROW_0_SDRAM) { |
143 | /* This will need to be dynamically assigned */ | 150 | /* This will need to be dynamically assigned */ |
144 | printk(KERN_INFO PFX "detected 4MB dedicated video ram.\n"); | 151 | printk(KERN_INFO PFX "detected 4MB dedicated video ram.\n"); |
145 | intel_i810_private.num_dcache_entries = 1024; | 152 | intel_private.num_dcache_entries = 1024; |
146 | } | 153 | } |
147 | pci_read_config_dword(intel_i810_private.i810_dev, I810_GMADDR, &temp); | 154 | pci_read_config_dword(intel_private.pcidev, I810_GMADDR, &temp); |
148 | agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); | 155 | agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); |
149 | writel(agp_bridge->gatt_bus_addr | I810_PGETBL_ENABLED, intel_i810_private.registers+I810_PGETBL_CTL); | 156 | writel(agp_bridge->gatt_bus_addr | I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL); |
150 | readl(intel_i810_private.registers+I810_PGETBL_CTL); /* PCI Posting. */ | 157 | readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */ |
151 | 158 | ||
152 | if (agp_bridge->driver->needs_scratch_page) { | 159 | if (agp_bridge->driver->needs_scratch_page) { |
153 | for (i = 0; i < current_size->num_entries; i++) { | 160 | for (i = 0; i < current_size->num_entries; i++) { |
154 | writel(agp_bridge->scratch_page, intel_i810_private.registers+I810_PTE_BASE+(i*4)); | 161 | writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4)); |
155 | readl(intel_i810_private.registers+I810_PTE_BASE+(i*4)); /* PCI posting. */ | 162 | readl(intel_private.registers+I810_PTE_BASE+(i*4)); /* PCI posting. */ |
156 | } | 163 | } |
157 | } | 164 | } |
158 | global_cache_flush(); | 165 | global_cache_flush(); |
@@ -161,9 +168,9 @@ static int intel_i810_configure(void) | |||
161 | 168 | ||
162 | static void intel_i810_cleanup(void) | 169 | static void intel_i810_cleanup(void) |
163 | { | 170 | { |
164 | writel(0, intel_i810_private.registers+I810_PGETBL_CTL); | 171 | writel(0, intel_private.registers+I810_PGETBL_CTL); |
165 | readl(intel_i810_private.registers); /* PCI Posting. */ | 172 | readl(intel_private.registers); /* PCI Posting. */ |
166 | iounmap(intel_i810_private.registers); | 173 | iounmap(intel_private.registers); |
167 | } | 174 | } |
168 | 175 | ||
169 | static void intel_i810_tlbflush(struct agp_memory *mem) | 176 | static void intel_i810_tlbflush(struct agp_memory *mem) |
@@ -261,9 +268,9 @@ static int intel_i810_insert_entries(struct agp_memory *mem, off_t pg_start, | |||
261 | global_cache_flush(); | 268 | global_cache_flush(); |
262 | for (i = pg_start; i < (pg_start + mem->page_count); i++) { | 269 | for (i = pg_start; i < (pg_start + mem->page_count); i++) { |
263 | writel((i*4096)|I810_PTE_LOCAL|I810_PTE_VALID, | 270 | writel((i*4096)|I810_PTE_LOCAL|I810_PTE_VALID, |
264 | intel_i810_private.registers+I810_PTE_BASE+(i*4)); | 271 | intel_private.registers+I810_PTE_BASE+(i*4)); |
265 | } | 272 | } |
266 | readl(intel_i810_private.registers+I810_PTE_BASE+((i-1)*4)); | 273 | readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); |
267 | break; | 274 | break; |
268 | case AGP_PHYS_MEMORY: | 275 | case AGP_PHYS_MEMORY: |
269 | case AGP_NORMAL_MEMORY: | 276 | case AGP_NORMAL_MEMORY: |
@@ -273,9 +280,9 @@ static int intel_i810_insert_entries(struct agp_memory *mem, off_t pg_start, | |||
273 | writel(agp_bridge->driver->mask_memory(agp_bridge, | 280 | writel(agp_bridge->driver->mask_memory(agp_bridge, |
274 | mem->memory[i], | 281 | mem->memory[i], |
275 | mask_type), | 282 | mask_type), |
276 | intel_i810_private.registers+I810_PTE_BASE+(j*4)); | 283 | intel_private.registers+I810_PTE_BASE+(j*4)); |
277 | } | 284 | } |
278 | readl(intel_i810_private.registers+I810_PTE_BASE+((j-1)*4)); | 285 | readl(intel_private.registers+I810_PTE_BASE+((j-1)*4)); |
279 | break; | 286 | break; |
280 | default: | 287 | default: |
281 | goto out_err; | 288 | goto out_err; |
@@ -298,9 +305,9 @@ static int intel_i810_remove_entries(struct agp_memory *mem, off_t pg_start, | |||
298 | return 0; | 305 | return 0; |
299 | 306 | ||
300 | for (i = pg_start; i < (mem->page_count + pg_start); i++) { | 307 | for (i = pg_start; i < (mem->page_count + pg_start); i++) { |
301 | writel(agp_bridge->scratch_page, intel_i810_private.registers+I810_PTE_BASE+(i*4)); | 308 | writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4)); |
302 | } | 309 | } |
303 | readl(intel_i810_private.registers+I810_PTE_BASE+((i-1)*4)); | 310 | readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); |
304 | 311 | ||
305 | agp_bridge->driver->tlb_flush(mem); | 312 | agp_bridge->driver->tlb_flush(mem); |
306 | return 0; | 313 | return 0; |
@@ -354,7 +361,7 @@ static struct agp_memory *intel_i810_alloc_by_type(size_t pg_count, int type) | |||
354 | struct agp_memory *new; | 361 | struct agp_memory *new; |
355 | 362 | ||
356 | if (type == AGP_DCACHE_MEMORY) { | 363 | if (type == AGP_DCACHE_MEMORY) { |
357 | if (pg_count != intel_i810_private.num_dcache_entries) | 364 | if (pg_count != intel_private.num_dcache_entries) |
358 | return NULL; | 365 | return NULL; |
359 | 366 | ||
360 | new = agp_create_memory(1); | 367 | new = agp_create_memory(1); |
@@ -404,18 +411,6 @@ static struct aper_size_info_fixed intel_i830_sizes[] = | |||
404 | {512, 131072, 7}, | 411 | {512, 131072, 7}, |
405 | }; | 412 | }; |
406 | 413 | ||
407 | static struct _intel_i830_private { | ||
408 | struct pci_dev *i830_dev; /* device one */ | ||
409 | volatile u8 __iomem *registers; | ||
410 | volatile u32 __iomem *gtt; /* I915G */ | ||
411 | /* gtt_entries is the number of gtt entries that are already mapped | ||
412 | * to stolen memory. Stolen memory is larger than the memory mapped | ||
413 | * through gtt_entries, as it includes some reserved space for the BIOS | ||
414 | * popup and for the GTT. | ||
415 | */ | ||
416 | int gtt_entries; | ||
417 | } intel_i830_private; | ||
418 | |||
419 | static void intel_i830_init_gtt_entries(void) | 414 | static void intel_i830_init_gtt_entries(void) |
420 | { | 415 | { |
421 | u16 gmch_ctrl; | 416 | u16 gmch_ctrl; |
@@ -429,7 +424,7 @@ static void intel_i830_init_gtt_entries(void) | |||
429 | 424 | ||
430 | if (IS_I965) { | 425 | if (IS_I965) { |
431 | u32 pgetbl_ctl; | 426 | u32 pgetbl_ctl; |
432 | pgetbl_ctl = readl(intel_i830_private.registers+I810_PGETBL_CTL); | 427 | pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL); |
433 | 428 | ||
434 | /* The 965 has a field telling us the size of the GTT, | 429 | /* The 965 has a field telling us the size of the GTT, |
435 | * which may be larger than what is necessary to map the | 430 | * which may be larger than what is necessary to map the |
@@ -471,7 +466,7 @@ static void intel_i830_init_gtt_entries(void) | |||
471 | gtt_entries = MB(8) - KB(size); | 466 | gtt_entries = MB(8) - KB(size); |
472 | break; | 467 | break; |
473 | case I830_GMCH_GMS_LOCAL: | 468 | case I830_GMCH_GMS_LOCAL: |
474 | rdct = readb(intel_i830_private.registers+I830_RDRAM_CHANNEL_TYPE); | 469 | rdct = readb(intel_private.registers+I830_RDRAM_CHANNEL_TYPE); |
475 | gtt_entries = (I830_RDRAM_ND(rdct) + 1) * | 470 | gtt_entries = (I830_RDRAM_ND(rdct) + 1) * |
476 | MB(ddt[I830_RDRAM_DDT(rdct)]); | 471 | MB(ddt[I830_RDRAM_DDT(rdct)]); |
477 | local = 1; | 472 | local = 1; |
@@ -529,7 +524,7 @@ static void intel_i830_init_gtt_entries(void) | |||
529 | "No pre-allocated video memory detected.\n"); | 524 | "No pre-allocated video memory detected.\n"); |
530 | gtt_entries /= KB(4); | 525 | gtt_entries /= KB(4); |
531 | 526 | ||
532 | intel_i830_private.gtt_entries = gtt_entries; | 527 | intel_private.gtt_entries = gtt_entries; |
533 | } | 528 | } |
534 | 529 | ||
535 | /* The intel i830 automatically initializes the agp aperture during POST. | 530 | /* The intel i830 automatically initializes the agp aperture during POST. |
@@ -547,14 +542,14 @@ static int intel_i830_create_gatt_table(struct agp_bridge_data *bridge) | |||
547 | num_entries = size->num_entries; | 542 | num_entries = size->num_entries; |
548 | agp_bridge->gatt_table_real = NULL; | 543 | agp_bridge->gatt_table_real = NULL; |
549 | 544 | ||
550 | pci_read_config_dword(intel_i830_private.i830_dev,I810_MMADDR,&temp); | 545 | pci_read_config_dword(intel_private.pcidev,I810_MMADDR,&temp); |
551 | temp &= 0xfff80000; | 546 | temp &= 0xfff80000; |
552 | 547 | ||
553 | intel_i830_private.registers = ioremap(temp,128 * 4096); | 548 | intel_private.registers = ioremap(temp,128 * 4096); |
554 | if (!intel_i830_private.registers) | 549 | if (!intel_private.registers) |
555 | return -ENOMEM; | 550 | return -ENOMEM; |
556 | 551 | ||
557 | temp = readl(intel_i830_private.registers+I810_PGETBL_CTL) & 0xfffff000; | 552 | temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000; |
558 | global_cache_flush(); /* FIXME: ?? */ | 553 | global_cache_flush(); /* FIXME: ?? */ |
559 | 554 | ||
560 | /* we have to call this as early as possible after the MMIO base address is known */ | 555 | /* we have to call this as early as possible after the MMIO base address is known */ |
@@ -614,20 +609,20 @@ static int intel_i830_configure(void) | |||
614 | 609 | ||
615 | current_size = A_SIZE_FIX(agp_bridge->current_size); | 610 | current_size = A_SIZE_FIX(agp_bridge->current_size); |
616 | 611 | ||
617 | pci_read_config_dword(intel_i830_private.i830_dev,I810_GMADDR,&temp); | 612 | pci_read_config_dword(intel_private.pcidev,I810_GMADDR,&temp); |
618 | agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); | 613 | agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); |
619 | 614 | ||
620 | pci_read_config_word(agp_bridge->dev,I830_GMCH_CTRL,&gmch_ctrl); | 615 | pci_read_config_word(agp_bridge->dev,I830_GMCH_CTRL,&gmch_ctrl); |
621 | gmch_ctrl |= I830_GMCH_ENABLED; | 616 | gmch_ctrl |= I830_GMCH_ENABLED; |
622 | pci_write_config_word(agp_bridge->dev,I830_GMCH_CTRL,gmch_ctrl); | 617 | pci_write_config_word(agp_bridge->dev,I830_GMCH_CTRL,gmch_ctrl); |
623 | 618 | ||
624 | writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_i830_private.registers+I810_PGETBL_CTL); | 619 | writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL); |
625 | readl(intel_i830_private.registers+I810_PGETBL_CTL); /* PCI Posting. */ | 620 | readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */ |
626 | 621 | ||
627 | if (agp_bridge->driver->needs_scratch_page) { | 622 | if (agp_bridge->driver->needs_scratch_page) { |
628 | for (i = intel_i830_private.gtt_entries; i < current_size->num_entries; i++) { | 623 | for (i = intel_private.gtt_entries; i < current_size->num_entries; i++) { |
629 | writel(agp_bridge->scratch_page, intel_i830_private.registers+I810_PTE_BASE+(i*4)); | 624 | writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4)); |
630 | readl(intel_i830_private.registers+I810_PTE_BASE+(i*4)); /* PCI Posting. */ | 625 | readl(intel_private.registers+I810_PTE_BASE+(i*4)); /* PCI Posting. */ |
631 | } | 626 | } |
632 | } | 627 | } |
633 | 628 | ||
@@ -637,7 +632,7 @@ static int intel_i830_configure(void) | |||
637 | 632 | ||
638 | static void intel_i830_cleanup(void) | 633 | static void intel_i830_cleanup(void) |
639 | { | 634 | { |
640 | iounmap(intel_i830_private.registers); | 635 | iounmap(intel_private.registers); |
641 | } | 636 | } |
642 | 637 | ||
643 | static int intel_i830_insert_entries(struct agp_memory *mem,off_t pg_start, int type) | 638 | static int intel_i830_insert_entries(struct agp_memory *mem,off_t pg_start, int type) |
@@ -653,9 +648,9 @@ static int intel_i830_insert_entries(struct agp_memory *mem,off_t pg_start, int | |||
653 | temp = agp_bridge->current_size; | 648 | temp = agp_bridge->current_size; |
654 | num_entries = A_SIZE_FIX(temp)->num_entries; | 649 | num_entries = A_SIZE_FIX(temp)->num_entries; |
655 | 650 | ||
656 | if (pg_start < intel_i830_private.gtt_entries) { | 651 | if (pg_start < intel_private.gtt_entries) { |
657 | printk (KERN_DEBUG PFX "pg_start == 0x%.8lx,intel_i830_private.gtt_entries == 0x%.8x\n", | 652 | printk (KERN_DEBUG PFX "pg_start == 0x%.8lx,intel_private.gtt_entries == 0x%.8x\n", |
658 | pg_start,intel_i830_private.gtt_entries); | 653 | pg_start,intel_private.gtt_entries); |
659 | 654 | ||
660 | printk (KERN_INFO PFX "Trying to insert into local/stolen memory\n"); | 655 | printk (KERN_INFO PFX "Trying to insert into local/stolen memory\n"); |
661 | goto out_err; | 656 | goto out_err; |
@@ -683,9 +678,9 @@ static int intel_i830_insert_entries(struct agp_memory *mem,off_t pg_start, int | |||
683 | for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { | 678 | for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { |
684 | writel(agp_bridge->driver->mask_memory(agp_bridge, | 679 | writel(agp_bridge->driver->mask_memory(agp_bridge, |
685 | mem->memory[i], mask_type), | 680 | mem->memory[i], mask_type), |
686 | intel_i830_private.registers+I810_PTE_BASE+(j*4)); | 681 | intel_private.registers+I810_PTE_BASE+(j*4)); |
687 | } | 682 | } |
688 | readl(intel_i830_private.registers+I810_PTE_BASE+((j-1)*4)); | 683 | readl(intel_private.registers+I810_PTE_BASE+((j-1)*4)); |
689 | agp_bridge->driver->tlb_flush(mem); | 684 | agp_bridge->driver->tlb_flush(mem); |
690 | 685 | ||
691 | out: | 686 | out: |
@@ -703,15 +698,15 @@ static int intel_i830_remove_entries(struct agp_memory *mem,off_t pg_start, | |||
703 | if (mem->page_count == 0) | 698 | if (mem->page_count == 0) |
704 | return 0; | 699 | return 0; |
705 | 700 | ||
706 | if (pg_start < intel_i830_private.gtt_entries) { | 701 | if (pg_start < intel_private.gtt_entries) { |
707 | printk (KERN_INFO PFX "Trying to disable local/stolen memory\n"); | 702 | printk (KERN_INFO PFX "Trying to disable local/stolen memory\n"); |
708 | return -EINVAL; | 703 | return -EINVAL; |
709 | } | 704 | } |
710 | 705 | ||
711 | for (i = pg_start; i < (mem->page_count + pg_start); i++) { | 706 | for (i = pg_start; i < (mem->page_count + pg_start); i++) { |
712 | writel(agp_bridge->scratch_page, intel_i830_private.registers+I810_PTE_BASE+(i*4)); | 707 | writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4)); |
713 | } | 708 | } |
714 | readl(intel_i830_private.registers+I810_PTE_BASE+((i-1)*4)); | 709 | readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); |
715 | 710 | ||
716 | agp_bridge->driver->tlb_flush(mem); | 711 | agp_bridge->driver->tlb_flush(mem); |
717 | return 0; | 712 | return 0; |
@@ -734,7 +729,7 @@ static int intel_i915_configure(void) | |||
734 | 729 | ||
735 | current_size = A_SIZE_FIX(agp_bridge->current_size); | 730 | current_size = A_SIZE_FIX(agp_bridge->current_size); |
736 | 731 | ||
737 | pci_read_config_dword(intel_i830_private.i830_dev, I915_GMADDR, &temp); | 732 | pci_read_config_dword(intel_private.pcidev, I915_GMADDR, &temp); |
738 | 733 | ||
739 | agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); | 734 | agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); |
740 | 735 | ||
@@ -742,13 +737,13 @@ static int intel_i915_configure(void) | |||
742 | gmch_ctrl |= I830_GMCH_ENABLED; | 737 | gmch_ctrl |= I830_GMCH_ENABLED; |
743 | pci_write_config_word(agp_bridge->dev,I830_GMCH_CTRL,gmch_ctrl); | 738 | pci_write_config_word(agp_bridge->dev,I830_GMCH_CTRL,gmch_ctrl); |
744 | 739 | ||
745 | writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_i830_private.registers+I810_PGETBL_CTL); | 740 | writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL); |
746 | readl(intel_i830_private.registers+I810_PGETBL_CTL); /* PCI Posting. */ | 741 | readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */ |
747 | 742 | ||
748 | if (agp_bridge->driver->needs_scratch_page) { | 743 | if (agp_bridge->driver->needs_scratch_page) { |
749 | for (i = intel_i830_private.gtt_entries; i < current_size->num_entries; i++) { | 744 | for (i = intel_private.gtt_entries; i < current_size->num_entries; i++) { |
750 | writel(agp_bridge->scratch_page, intel_i830_private.gtt+i); | 745 | writel(agp_bridge->scratch_page, intel_private.gtt+i); |
751 | readl(intel_i830_private.gtt+i); /* PCI Posting. */ | 746 | readl(intel_private.gtt+i); /* PCI Posting. */ |
752 | } | 747 | } |
753 | } | 748 | } |
754 | 749 | ||
@@ -758,8 +753,8 @@ static int intel_i915_configure(void) | |||
758 | 753 | ||
759 | static void intel_i915_cleanup(void) | 754 | static void intel_i915_cleanup(void) |
760 | { | 755 | { |
761 | iounmap(intel_i830_private.gtt); | 756 | iounmap(intel_private.gtt); |
762 | iounmap(intel_i830_private.registers); | 757 | iounmap(intel_private.registers); |
763 | } | 758 | } |
764 | 759 | ||
765 | static int intel_i915_insert_entries(struct agp_memory *mem,off_t pg_start, | 760 | static int intel_i915_insert_entries(struct agp_memory *mem,off_t pg_start, |
@@ -776,9 +771,9 @@ static int intel_i915_insert_entries(struct agp_memory *mem,off_t pg_start, | |||
776 | temp = agp_bridge->current_size; | 771 | temp = agp_bridge->current_size; |
777 | num_entries = A_SIZE_FIX(temp)->num_entries; | 772 | num_entries = A_SIZE_FIX(temp)->num_entries; |
778 | 773 | ||
779 | if (pg_start < intel_i830_private.gtt_entries) { | 774 | if (pg_start < intel_private.gtt_entries) { |
780 | printk (KERN_DEBUG PFX "pg_start == 0x%.8lx,intel_i830_private.gtt_entries == 0x%.8x\n", | 775 | printk (KERN_DEBUG PFX "pg_start == 0x%.8lx,intel_private.gtt_entries == 0x%.8x\n", |
781 | pg_start,intel_i830_private.gtt_entries); | 776 | pg_start,intel_private.gtt_entries); |
782 | 777 | ||
783 | printk (KERN_INFO PFX "Trying to insert into local/stolen memory\n"); | 778 | printk (KERN_INFO PFX "Trying to insert into local/stolen memory\n"); |
784 | goto out_err; | 779 | goto out_err; |
@@ -805,10 +800,10 @@ static int intel_i915_insert_entries(struct agp_memory *mem,off_t pg_start, | |||
805 | 800 | ||
806 | for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { | 801 | for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { |
807 | writel(agp_bridge->driver->mask_memory(agp_bridge, | 802 | writel(agp_bridge->driver->mask_memory(agp_bridge, |
808 | mem->memory[i], mask_type), intel_i830_private.gtt+j); | 803 | mem->memory[i], mask_type), intel_private.gtt+j); |
809 | } | 804 | } |
810 | 805 | ||
811 | readl(intel_i830_private.gtt+j-1); | 806 | readl(intel_private.gtt+j-1); |
812 | agp_bridge->driver->tlb_flush(mem); | 807 | agp_bridge->driver->tlb_flush(mem); |
813 | 808 | ||
814 | out: | 809 | out: |
@@ -826,15 +821,15 @@ static int intel_i915_remove_entries(struct agp_memory *mem,off_t pg_start, | |||
826 | if (mem->page_count == 0) | 821 | if (mem->page_count == 0) |
827 | return 0; | 822 | return 0; |
828 | 823 | ||
829 | if (pg_start < intel_i830_private.gtt_entries) { | 824 | if (pg_start < intel_private.gtt_entries) { |
830 | printk (KERN_INFO PFX "Trying to disable local/stolen memory\n"); | 825 | printk (KERN_INFO PFX "Trying to disable local/stolen memory\n"); |
831 | return -EINVAL; | 826 | return -EINVAL; |
832 | } | 827 | } |
833 | 828 | ||
834 | for (i = pg_start; i < (mem->page_count + pg_start); i++) { | 829 | for (i = pg_start; i < (mem->page_count + pg_start); i++) { |
835 | writel(agp_bridge->scratch_page, intel_i830_private.gtt+i); | 830 | writel(agp_bridge->scratch_page, intel_private.gtt+i); |
836 | } | 831 | } |
837 | readl(intel_i830_private.gtt+i-1); | 832 | readl(intel_private.gtt+i-1); |
838 | 833 | ||
839 | agp_bridge->driver->tlb_flush(mem); | 834 | agp_bridge->driver->tlb_flush(mem); |
840 | return 0; | 835 | return 0; |
@@ -850,7 +845,7 @@ static int intel_i9xx_fetch_size(void) | |||
850 | int aper_size; /* size in megabytes */ | 845 | int aper_size; /* size in megabytes */ |
851 | int i; | 846 | int i; |
852 | 847 | ||
853 | aper_size = pci_resource_len(intel_i830_private.i830_dev, 2) / MB(1); | 848 | aper_size = pci_resource_len(intel_private.pcidev, 2) / MB(1); |
854 | 849 | ||
855 | for (i = 0; i < num_sizes; i++) { | 850 | for (i = 0; i < num_sizes; i++) { |
856 | if (aper_size == intel_i830_sizes[i].size) { | 851 | if (aper_size == intel_i830_sizes[i].size) { |
@@ -878,20 +873,20 @@ static int intel_i915_create_gatt_table(struct agp_bridge_data *bridge) | |||
878 | num_entries = size->num_entries; | 873 | num_entries = size->num_entries; |
879 | agp_bridge->gatt_table_real = NULL; | 874 | agp_bridge->gatt_table_real = NULL; |
880 | 875 | ||
881 | pci_read_config_dword(intel_i830_private.i830_dev, I915_MMADDR, &temp); | 876 | pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &temp); |
882 | pci_read_config_dword(intel_i830_private.i830_dev, I915_PTEADDR,&temp2); | 877 | pci_read_config_dword(intel_private.pcidev, I915_PTEADDR,&temp2); |
883 | 878 | ||
884 | intel_i830_private.gtt = ioremap(temp2, 256 * 1024); | 879 | intel_private.gtt = ioremap(temp2, 256 * 1024); |
885 | if (!intel_i830_private.gtt) | 880 | if (!intel_private.gtt) |
886 | return -ENOMEM; | 881 | return -ENOMEM; |
887 | 882 | ||
888 | temp &= 0xfff80000; | 883 | temp &= 0xfff80000; |
889 | 884 | ||
890 | intel_i830_private.registers = ioremap(temp,128 * 4096); | 885 | intel_private.registers = ioremap(temp,128 * 4096); |
891 | if (!intel_i830_private.registers) | 886 | if (!intel_private.registers) |
892 | return -ENOMEM; | 887 | return -ENOMEM; |
893 | 888 | ||
894 | temp = readl(intel_i830_private.registers+I810_PGETBL_CTL) & 0xfffff000; | 889 | temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000; |
895 | global_cache_flush(); /* FIXME: ? */ | 890 | global_cache_flush(); /* FIXME: ? */ |
896 | 891 | ||
897 | /* we have to call this as early as possible after the MMIO base address is known */ | 892 | /* we have to call this as early as possible after the MMIO base address is known */ |
@@ -938,20 +933,20 @@ static int intel_i965_create_gatt_table(struct agp_bridge_data *bridge) | |||
938 | num_entries = size->num_entries; | 933 | num_entries = size->num_entries; |
939 | agp_bridge->gatt_table_real = NULL; | 934 | agp_bridge->gatt_table_real = NULL; |
940 | 935 | ||
941 | pci_read_config_dword(intel_i830_private.i830_dev, I915_MMADDR, &temp); | 936 | pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &temp); |
942 | 937 | ||
943 | temp &= 0xfff00000; | 938 | temp &= 0xfff00000; |
944 | intel_i830_private.gtt = ioremap((temp + (512 * 1024)) , 512 * 1024); | 939 | intel_private.gtt = ioremap((temp + (512 * 1024)) , 512 * 1024); |
945 | 940 | ||
946 | if (!intel_i830_private.gtt) | 941 | if (!intel_private.gtt) |
947 | return -ENOMEM; | 942 | return -ENOMEM; |
948 | 943 | ||
949 | 944 | ||
950 | intel_i830_private.registers = ioremap(temp,128 * 4096); | 945 | intel_private.registers = ioremap(temp,128 * 4096); |
951 | if (!intel_i830_private.registers) | 946 | if (!intel_private.registers) |
952 | return -ENOMEM; | 947 | return -ENOMEM; |
953 | 948 | ||
954 | temp = readl(intel_i830_private.registers+I810_PGETBL_CTL) & 0xfffff000; | 949 | temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000; |
955 | global_cache_flush(); /* FIXME: ? */ | 950 | global_cache_flush(); /* FIXME: ? */ |
956 | 951 | ||
957 | /* we have to call this as early as possible after the MMIO base address is known */ | 952 | /* we have to call this as early as possible after the MMIO base address is known */ |
@@ -1729,7 +1724,7 @@ static int find_i810(u16 device) | |||
1729 | i810_dev = pci_get_device(PCI_VENDOR_ID_INTEL, device, NULL); | 1724 | i810_dev = pci_get_device(PCI_VENDOR_ID_INTEL, device, NULL); |
1730 | if (!i810_dev) | 1725 | if (!i810_dev) |
1731 | return 0; | 1726 | return 0; |
1732 | intel_i810_private.i810_dev = i810_dev; | 1727 | intel_private.pcidev = i810_dev; |
1733 | return 1; | 1728 | return 1; |
1734 | } | 1729 | } |
1735 | 1730 | ||
@@ -1746,7 +1741,7 @@ static int find_i830(u16 device) | |||
1746 | if (!i830_dev) | 1741 | if (!i830_dev) |
1747 | return 0; | 1742 | return 0; |
1748 | 1743 | ||
1749 | intel_i830_private.i830_dev = i830_dev; | 1744 | intel_private.pcidev = i830_dev; |
1750 | return 1; | 1745 | return 1; |
1751 | } | 1746 | } |
1752 | 1747 | ||
@@ -1946,11 +1941,7 @@ static int __devinit agp_intel_probe(struct pci_dev *pdev, | |||
1946 | 1941 | ||
1947 | bridge->dev = pdev; | 1942 | bridge->dev = pdev; |
1948 | bridge->capndx = cap_ptr; | 1943 | bridge->capndx = cap_ptr; |
1949 | 1944 | bridge->dev_private_data = &intel_private; | |
1950 | if (bridge->driver == &intel_810_driver) | ||
1951 | bridge->dev_private_data = &intel_i810_private; | ||
1952 | else if (bridge->driver == &intel_830_driver) | ||
1953 | bridge->dev_private_data = &intel_i830_private; | ||
1954 | 1945 | ||
1955 | printk(KERN_INFO PFX "Detected an Intel %s Chipset.\n", name); | 1946 | printk(KERN_INFO PFX "Detected an Intel %s Chipset.\n", name); |
1956 | 1947 | ||
@@ -2002,10 +1993,8 @@ static void __devexit agp_intel_remove(struct pci_dev *pdev) | |||
2002 | 1993 | ||
2003 | agp_remove_bridge(bridge); | 1994 | agp_remove_bridge(bridge); |
2004 | 1995 | ||
2005 | if (intel_i810_private.i810_dev) | 1996 | if (intel_private.pcidev) |
2006 | pci_dev_put(intel_i810_private.i810_dev); | 1997 | pci_dev_put(intel_private.pcidev); |
2007 | if (intel_i830_private.i830_dev) | ||
2008 | pci_dev_put(intel_i830_private.i830_dev); | ||
2009 | 1998 | ||
2010 | agp_put_bridge(bridge); | 1999 | agp_put_bridge(bridge); |
2011 | } | 2000 | } |
@@ -2021,10 +2010,8 @@ static int agp_intel_resume(struct pci_dev *pdev) | |||
2021 | * as host bridge (00:00) resumes before graphics device (02:00), | 2010 | * as host bridge (00:00) resumes before graphics device (02:00), |
2022 | * then our access to its pci space can work right. | 2011 | * then our access to its pci space can work right. |
2023 | */ | 2012 | */ |
2024 | if (intel_i810_private.i810_dev) | 2013 | if (intel_private.pcidev) |
2025 | pci_restore_state(intel_i810_private.i810_dev); | 2014 | pci_restore_state(intel_private.pcidev); |
2026 | if (intel_i830_private.i830_dev) | ||
2027 | pci_restore_state(intel_i830_private.i830_dev); | ||
2028 | 2015 | ||
2029 | if (bridge->driver == &intel_generic_driver) | 2016 | if (bridge->driver == &intel_generic_driver) |
2030 | intel_configure(); | 2017 | intel_configure(); |