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authorWang Zhenyu <zhenyu.z.wang@intel.com>2007-04-09 21:42:48 -0400
committerDave Jones <davej@redhat.com>2007-04-09 22:09:58 -0400
commit52ea0718ea506df0915eacedb439e65c5f214e0e (patch)
tree01e68ba08924faa8b458159c861b394a6f8053ad /drivers/char/agp
parent4598af33d9143942f00cf7692b247027aba35316 (diff)
[AGPGART] intel_agp: fix G965 GTT size detect
On G965, I810_PGETBL_CTL is a mmio offset, but we wrongly take it as pci config space offset in detecting GTT size. This one line patch fixs this. Signed-off-by: Wang Zhenyu <zhenyu.z.wang@intel.com> Signed-off-by: Dave Jones <davej@redhat.com>
Diffstat (limited to 'drivers/char/agp')
-rw-r--r--drivers/char/agp/intel-agp.c3
1 files changed, 1 insertions, 2 deletions
diff --git a/drivers/char/agp/intel-agp.c b/drivers/char/agp/intel-agp.c
index a9fdbf9126ca..55392a45a14b 100644
--- a/drivers/char/agp/intel-agp.c
+++ b/drivers/char/agp/intel-agp.c
@@ -431,9 +431,8 @@ static void intel_i830_init_gtt_entries(void)
431 431
432 if (IS_I965) { 432 if (IS_I965) {
433 u32 pgetbl_ctl; 433 u32 pgetbl_ctl;
434 pgetbl_ctl = readl(intel_i830_private.registers+I810_PGETBL_CTL);
434 435
435 pci_read_config_dword(agp_bridge->dev, I810_PGETBL_CTL,
436 &pgetbl_ctl);
437 /* The 965 has a field telling us the size of the GTT, 436 /* The 965 has a field telling us the size of the GTT,
438 * which may be larger than what is necessary to map the 437 * which may be larger than what is necessary to map the
439 * aperture. 438 * aperture.