agp/intel: fix cache control for sandybridge

This is broken from 97ef1bdd0bc75bce7b2058e9c432b6c277dcf4d3.
Let's set the correct bit for LLC+MLC and LLC only.

Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>

1 files changed, 2 insertions, 2 deletions

diff --git a/drivers/char/agp/intel-gtt.c b/drivers/char/agp/intel-gtt.c
index f800e9cfc368..c51efe6f2c7f 100644
--- a/drivers/char/agp/intel-gtt.c
+++ b/drivers/char/agp/intel-gtt.c
@@ -1291,11 +1291,11 @@ static void gen6_write_entry(dma_addr_t addr, unsigned int entry,
         if (type_mask == AGP_USER_UNCACHED_MEMORY)
                 pte_flags = GEN6_PTE_UNCACHED | I810_PTE_VALID;
         else if (type_mask == AGP_USER_CACHED_MEMORY_LLC_MLC) {
-                pte_flags = GEN6_PTE_LLC | I810_PTE_VALID;
+                pte_flags = GEN6_PTE_LLC_MLC | I810_PTE_VALID;
                 if (gfdt)
                         pte_flags |= GEN6_PTE_GFDT;
         } else { /* set 'normal'/'cached' to LLC by default */
-                pte_flags = GEN6_PTE_LLC_MLC | I810_PTE_VALID;
+                pte_flags = GEN6_PTE_LLC | I810_PTE_VALID;
                 if (gfdt)
                         pte_flags |= GEN6_PTE_GFDT;
         }