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authorPavel Machek <pavel@ucw.cz>2008-04-15 06:43:57 -0400
committerIngo Molnar <mingo@elte.hu>2008-05-12 15:28:10 -0400
commit3bb6fbf9969a8bbe4892968659239273d092e78a (patch)
tree26ede22e0622abfbb585cd83199b2615b4b4542d /drivers/char/agp/amd64-agp.c
parent330fce23dab6e6a3d1979e55f27aba4c0c301331 (diff)
x86 gart: factor out common code
Cleanup gart handling on amd64 a bit: move common code into enable_gart_translation , and use symbolic register names where appropriate. Signed-off-by: Pavel Machek <pavel@suse.cz> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Diffstat (limited to 'drivers/char/agp/amd64-agp.c')
-rw-r--r--drivers/char/agp/amd64-agp.c29
1 files changed, 9 insertions, 20 deletions
diff --git a/drivers/char/agp/amd64-agp.c b/drivers/char/agp/amd64-agp.c
index 9c24470a8252..e3c7ea07f57c 100644
--- a/drivers/char/agp/amd64-agp.c
+++ b/drivers/char/agp/amd64-agp.c
@@ -150,25 +150,14 @@ static u64 amd64_configure(struct pci_dev *hammer, u64 gatt_table)
150{ 150{
151 u64 aperturebase; 151 u64 aperturebase;
152 u32 tmp; 152 u32 tmp;
153 u64 addr, aper_base; 153 u64 aper_base;
154 154
155 /* Address to map to */ 155 /* Address to map to */
156 pci_read_config_dword (hammer, AMD64_GARTAPERTUREBASE, &tmp); 156 pci_read_config_dword(hammer, AMD64_GARTAPERTUREBASE, &tmp);
157 aperturebase = tmp << 25; 157 aperturebase = tmp << 25;
158 aper_base = (aperturebase & PCI_BASE_ADDRESS_MEM_MASK); 158 aper_base = (aperturebase & PCI_BASE_ADDRESS_MEM_MASK);
159 159
160 /* address of the mappings table */ 160 enable_gart_translation(hammer, gatt_table);
161 addr = (u64) gatt_table;
162 addr >>= 12;
163 tmp = (u32) addr<<4;
164 tmp &= ~0xf;
165 pci_write_config_dword(hammer, AMD64_GARTTABLEBASE, tmp);
166
167 /* Enable GART translation for this hammer. */
168 pci_read_config_dword(hammer, AMD64_GARTAPERTURECTL, &tmp);
169 tmp |= GARTEN;
170 tmp &= ~(DISGARTCPU | DISGARTIO);
171 pci_write_config_dword(hammer, AMD64_GARTAPERTURECTL, tmp);
172 161
173 return aper_base; 162 return aper_base;
174} 163}
@@ -207,9 +196,9 @@ static void amd64_cleanup(void)
207 for (i = 0; i < num_k8_northbridges; i++) { 196 for (i = 0; i < num_k8_northbridges; i++) {
208 struct pci_dev *dev = k8_northbridges[i]; 197 struct pci_dev *dev = k8_northbridges[i];
209 /* disable gart translation */ 198 /* disable gart translation */
210 pci_read_config_dword (dev, AMD64_GARTAPERTURECTL, &tmp); 199 pci_read_config_dword(dev, AMD64_GARTAPERTURECTL, &tmp);
211 tmp &= ~AMD64_GARTEN; 200 tmp &= ~AMD64_GARTEN;
212 pci_write_config_dword (dev, AMD64_GARTAPERTURECTL, tmp); 201 pci_write_config_dword(dev, AMD64_GARTAPERTURECTL, tmp);
213 } 202 }
214} 203}
215 204
@@ -289,9 +278,9 @@ static __devinit int fix_northbridge(struct pci_dev *nb, struct pci_dev *agp,
289 u32 nb_order, nb_base; 278 u32 nb_order, nb_base;
290 u16 apsize; 279 u16 apsize;
291 280
292 pci_read_config_dword(nb, 0x90, &nb_order); 281 pci_read_config_dword(nb, AMD64_GARTAPERTURECTL, &nb_order);
293 nb_order = (nb_order >> 1) & 7; 282 nb_order = (nb_order >> 1) & 7;
294 pci_read_config_dword(nb, 0x94, &nb_base); 283 pci_read_config_dword(nb, AMD64_GARTAPERTUREBASE, &nb_base);
295 nb_aper = nb_base << 25; 284 nb_aper = nb_base << 25;
296 if (aperture_valid(nb_aper, (32*1024*1024)<<nb_order)) { 285 if (aperture_valid(nb_aper, (32*1024*1024)<<nb_order)) {
297 return 0; 286 return 0;
@@ -327,8 +316,8 @@ static __devinit int fix_northbridge(struct pci_dev *nb, struct pci_dev *agp,
327 if (order < 0 || !aperture_valid(aper, (32*1024*1024)<<order)) 316 if (order < 0 || !aperture_valid(aper, (32*1024*1024)<<order))
328 return -1; 317 return -1;
329 318
330 pci_write_config_dword(nb, 0x90, order << 1); 319 pci_write_config_dword(nb, AMD64_GARTAPERTURECTL, order << 1);
331 pci_write_config_dword(nb, 0x94, aper >> 25); 320 pci_write_config_dword(nb, AMD64_GARTAPERTUREBASE, aper >> 25);
332 321
333 return 0; 322 return 0;
334} 323}