diff options
author | Pavel Machek <pavel@ucw.cz> | 2008-04-08 04:49:03 -0400 |
---|---|---|
committer | Ingo Molnar <mingo@elte.hu> | 2008-05-12 15:28:10 -0400 |
commit | aa134f1b09df6beaa4d031a50d5fda1f3cebce6c (patch) | |
tree | 3bd632e6fa8490cf5b472271d57c8c70abaa62b4 /drivers/char/agp/amd64-agp.c | |
parent | 492c2e476eac010962850006c49df326919b284c (diff) |
x86: iommu: use symbolic constants, not hardcoded numbers
Move symbolic constants into gart.h, and use them instead of hardcoded
constant.
Signed-off-by: Pavel Machek <pavel@suse.cz>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Diffstat (limited to 'drivers/char/agp/amd64-agp.c')
-rw-r--r-- | drivers/char/agp/amd64-agp.c | 25 |
1 files changed, 3 insertions, 22 deletions
diff --git a/drivers/char/agp/amd64-agp.c b/drivers/char/agp/amd64-agp.c index d8200ac8f8cb..25d64224cdbb 100644 --- a/drivers/char/agp/amd64-agp.c +++ b/drivers/char/agp/amd64-agp.c | |||
@@ -16,28 +16,9 @@ | |||
16 | #include <asm/page.h> /* PAGE_SIZE */ | 16 | #include <asm/page.h> /* PAGE_SIZE */ |
17 | #include <asm/e820.h> | 17 | #include <asm/e820.h> |
18 | #include <asm/k8.h> | 18 | #include <asm/k8.h> |
19 | #include <asm/gart.h> | ||
19 | #include "agp.h" | 20 | #include "agp.h" |
20 | 21 | ||
21 | /* PTE bits. */ | ||
22 | #define GPTE_VALID 1 | ||
23 | #define GPTE_COHERENT 2 | ||
24 | |||
25 | /* Aperture control register bits. */ | ||
26 | #define GARTEN (1<<0) | ||
27 | #define DISGARTCPU (1<<4) | ||
28 | #define DISGARTIO (1<<5) | ||
29 | |||
30 | /* GART cache control register bits. */ | ||
31 | #define INVGART (1<<0) | ||
32 | #define GARTPTEERR (1<<1) | ||
33 | |||
34 | /* K8 On-cpu GART registers */ | ||
35 | #define AMD64_GARTAPERTURECTL 0x90 | ||
36 | #define AMD64_GARTAPERTUREBASE 0x94 | ||
37 | #define AMD64_GARTTABLEBASE 0x98 | ||
38 | #define AMD64_GARTCACHECTL 0x9c | ||
39 | #define AMD64_GARTEN (1<<0) | ||
40 | |||
41 | /* NVIDIA K8 registers */ | 22 | /* NVIDIA K8 registers */ |
42 | #define NVIDIA_X86_64_0_APBASE 0x10 | 23 | #define NVIDIA_X86_64_0_APBASE 0x10 |
43 | #define NVIDIA_X86_64_1_APBASE1 0x50 | 24 | #define NVIDIA_X86_64_1_APBASE1 0x50 |
@@ -165,7 +146,7 @@ static int amd64_fetch_size(void) | |||
165 | * In a multiprocessor x86-64 system, this function gets | 146 | * In a multiprocessor x86-64 system, this function gets |
166 | * called once for each CPU. | 147 | * called once for each CPU. |
167 | */ | 148 | */ |
168 | static u64 amd64_configure (struct pci_dev *hammer, u64 gatt_table) | 149 | static u64 amd64_configure(struct pci_dev *hammer, u64 gatt_table) |
169 | { | 150 | { |
170 | u64 aperturebase; | 151 | u64 aperturebase; |
171 | u32 tmp; | 152 | u32 tmp; |
@@ -181,7 +162,7 @@ static u64 amd64_configure (struct pci_dev *hammer, u64 gatt_table) | |||
181 | addr >>= 12; | 162 | addr >>= 12; |
182 | tmp = (u32) addr<<4; | 163 | tmp = (u32) addr<<4; |
183 | tmp &= ~0xf; | 164 | tmp &= ~0xf; |
184 | pci_write_config_dword (hammer, AMD64_GARTTABLEBASE, tmp); | 165 | pci_write_config_dword(hammer, AMD64_GARTTABLEBASE, tmp); |
185 | 166 | ||
186 | /* Enable GART translation for this hammer. */ | 167 | /* Enable GART translation for this hammer. */ |
187 | pci_read_config_dword(hammer, AMD64_GARTAPERTURECTL, &tmp); | 168 | pci_read_config_dword(hammer, AMD64_GARTAPERTURECTL, &tmp); |