Merge branch 'x86-amd-nb-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip

* 'x86-amd-nb-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip:
  x86, amd_nb: Enable GART support for AMD family 0x15 CPUs
  x86, amd: Use compute unit information to determine thread siblings
  x86, amd: Extract compute unit information for AMD CPUs
  x86, amd: Add support for CPUID topology extension of AMD CPUs
  x86, nmi: Support NMI watchdog on newer AMD CPU families
  x86, mtrr: Assume SYS_CFG[Tom2ForceMemTypeWB] exists on all future AMD CPUs
  x86, k8: Rename k8.[ch] to amd_nb.[ch] and CONFIG_K8_NB to CONFIG_AMD_NB
  x86, k8-gart: Decouple handling of garts and northbridges
  x86, cacheinfo: Fix dependency of AMD L3 CID
  x86, kvm: add new AMD SVM feature bits
  x86, cpu: Fix allowed CPUID bits for KVM guests
  x86, cpu: Update AMD CPUID feature bits
  x86, cpu: Fix renamed, not-yet-shipping AMD CPUID feature bit
  x86, AMD: Remove needless CPU family check (for L3 cache info)
  x86, tsc: Remove CPU frequency calibration on AMD

1 files changed, 24 insertions, 11 deletions

diff --git a/drivers/char/agp/amd64-agp.c b/drivers/char/agp/amd64-agp.c
index 564808a5c3c0..42396df55556 100644
--- a/drivers/char/agp/amd64-agp.c
+++ b/drivers/char/agp/amd64-agp.c
@@ -15,7 +15,7 @@
 #include <linux/mmzone.h>
 #include <asm/page.h>           /* PAGE_SIZE */
 #include <asm/e820.h>
-#include <asm/k8.h>
+#include <asm/amd_nb.h>
 #include <asm/gart.h>
 #include "agp.h"
 
@@ -124,7 +124,7 @@ static int amd64_fetch_size(void)
         u32 temp;
         struct aper_size_info_32 *values;
 
-        dev = k8_northbridges[0];
+        dev = k8_northbridges.nb_misc[0];
         if (dev==NULL)
                 return 0;
 
@@ -181,10 +181,14 @@ static int amd_8151_configure(void)
         unsigned long gatt_bus = virt_to_phys(agp_bridge->gatt_table_real);
         int i;
 
+        if (!k8_northbridges.gart_supported)
+                return 0;
+
         /* Configure AGP regs in each x86-64 host bridge. */
-        for (i = 0; i < num_k8_northbridges; i++) {
+        for (i = 0; i < k8_northbridges.num; i++) {
                 agp_bridge->gart_bus_addr =
-                                amd64_configure(k8_northbridges[i], gatt_bus);
+                                amd64_configure(k8_northbridges.nb_misc[i],
+                                                gatt_bus);
         }
         k8_flush_garts();
         return 0;
@@ -195,8 +199,12 @@ static void amd64_cleanup(void)
 {
         u32 tmp;
         int i;
-        for (i = 0; i < num_k8_northbridges; i++) {
-                struct pci_dev *dev = k8_northbridges[i];
+
+        if (!k8_northbridges.gart_supported)
+                return;
+
+        for (i = 0; i < k8_northbridges.num; i++) {
+                struct pci_dev *dev = k8_northbridges.nb_misc[i];
                 /* disable gart translation */
                 pci_read_config_dword(dev, AMD64_GARTAPERTURECTL, &tmp);
                 tmp &= ~GARTEN;
@@ -319,16 +327,19 @@ static __devinit int fix_northbridge(struct pci_dev *nb, struct pci_dev *agp,
         return 0;
 }
 
-static __devinit int cache_nbs (struct pci_dev *pdev, u32 cap_ptr)
+static __devinit int cache_nbs(struct pci_dev *pdev, u32 cap_ptr)
 {
         int i;
 
         if (cache_k8_northbridges() < 0)
                 return -ENODEV;
 
+        if (!k8_northbridges.gart_supported)
+                return -ENODEV;
+
         i = 0;
-        for (i = 0; i < num_k8_northbridges; i++) {
-                struct pci_dev *dev = k8_northbridges[i];
+        for (i = 0; i < k8_northbridges.num; i++) {
+                struct pci_dev *dev = k8_northbridges.nb_misc[i];
                 if (fix_northbridge(dev, pdev, cap_ptr) < 0) {
                         dev_err(&dev->dev, "no usable aperture found\n");
 #ifdef __x86_64__
@@ -405,7 +416,8 @@ static int __devinit uli_agp_init(struct pci_dev *pdev)
         }
 
         /* shadow x86-64 registers into ULi registers */
-        pci_read_config_dword (k8_northbridges[0], AMD64_GARTAPERTUREBASE, &httfea);
+        pci_read_config_dword (k8_northbridges.nb_misc[0], AMD64_GARTAPERTUREBASE,
+                               &httfea);
 
         /* if x86-64 aperture base is beyond 4G, exit here */
         if ((httfea & 0x7fff) >> (32 - 25)) {
@@ -472,7 +484,8 @@ static int nforce3_agp_init(struct pci_dev *pdev)
         pci_write_config_dword(dev1, NVIDIA_X86_64_1_APSIZE, tmp);
 
         /* shadow x86-64 registers into NVIDIA registers */
-        pci_read_config_dword (k8_northbridges[0], AMD64_GARTAPERTUREBASE, &apbase);
+        pci_read_config_dword (k8_northbridges.nb_misc[0], AMD64_GARTAPERTUREBASE,
+                               &apbase);
 
         /* if x86-64 aperture base is beyond 4G, exit here */
         if ( (apbase & 0x7fff) >> (32 - 25) ) {