[AGPGART] intel_agp: Add support for G33, Q33 and Q35 chipsets

This patch adds pci ids for G33, Q33 and Q35 chips, and update with new
GTT size and stolen mem size detect method on these chips.

Signed-off-by: Wang Zhenyu <zhenyu.z.wang@intel.com>
Signed-off-by: Dave Jones <davej@redhat.com>

1 files changed, 5 insertions, 1 deletions

diff --git a/drivers/char/agp/agp.h b/drivers/char/agp/agp.h
index fdbca25a3948..35ab1a9f8e8b 100644
--- a/drivers/char/agp/agp.h
+++ b/drivers/char/agp/agp.h
@@ -176,7 +176,7 @@ struct agp_bridge_data {
 #define I830_GMCH_MEM_MASK              0x1
 #define I830_GMCH_MEM_64M               0x1
 #define I830_GMCH_MEM_128M              0
-#define I830_GMCH_GMS_MASK              0x70
+#define I830_GMCH_GMS_MASK              0xF0
 #define I830_GMCH_GMS_DISABLED          0x00
 #define I830_GMCH_GMS_LOCAL             0x10
 #define I830_GMCH_GMS_STOLEN_512        0x20
@@ -231,6 +231,10 @@ struct agp_bridge_data {
 #define I965_PGETBL_SIZE_512KB  (0 << 1)
 #define I965_PGETBL_SIZE_256KB  (1 << 1)
 #define I965_PGETBL_SIZE_128KB  (2 << 1)
+#define G33_PGETBL_SIZE_MASK    (3 << 8)
+#define G33_PGETBL_SIZE_1M      (1 << 8)
+#define G33_PGETBL_SIZE_2M      (2 << 8)
+
 #define I810_DRAM_CTL           0x3000
 #define I810_DRAM_ROW_0         0x00000001
 #define I810_DRAM_ROW_0_SDRAM   0x00000001