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authorNishanth Menon <nm@ti.com>2014-04-11 12:21:47 -0400
committerNishanth Menon <nm@ti.com>2014-05-05 15:33:01 -0400
commit9e224c8ff19e4c4a9c9272171d5a0169d5cb1bef (patch)
tree0fe14e60cea7421c84523de400ce17ba5de11bdc /drivers/bus
parentca6a34935c2c95482b901d76116f785ea356412c (diff)
bus: omap_l3_noc: switch over to relaxed variants of readl/writel
Currently we use __raw_readl and writel in this driver. Considering there is no specific need for a memory barrier, replacing writel with endian-neutral writel_relaxed and replacing __raw_readls with the corresponding endian-neutral readl_relaxed allows us to have a standard set of register operations for the driver. While at it, simplify address computation using variables for register. Signed-off-by: Nishanth Menon <nm@ti.com> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Felipe Balbi <balbi@ti.com> Acked-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Tested-by: Darren Etheridge <detheridge@ti.com> Tested-by: Sekhar Nori <nsekhar@ti.com>
Diffstat (limited to 'drivers/bus')
-rw-r--r--drivers/bus/omap_l3_noc.c26
1 files changed, 14 insertions, 12 deletions
diff --git a/drivers/bus/omap_l3_noc.c b/drivers/bus/omap_l3_noc.c
index 37d71b715053..c8facb00bb53 100644
--- a/drivers/bus/omap_l3_noc.c
+++ b/drivers/bus/omap_l3_noc.c
@@ -55,6 +55,7 @@ static irqreturn_t l3_interrupt_handler(int irq, void *_l3)
55 int err_src = 0; 55 int err_src = 0;
56 u32 std_err_main, err_reg, clear, masterid; 56 u32 std_err_main, err_reg, clear, masterid;
57 void __iomem *base, *l3_targ_base; 57 void __iomem *base, *l3_targ_base;
58 void __iomem *l3_targ_stderr, *l3_targ_slvofslsb, *l3_targ_mstaddr;
58 char *target_name, *master_name = "UN IDENTIFIED"; 59 char *target_name, *master_name = "UN IDENTIFIED";
59 60
60 /* Get the Type of interrupt */ 61 /* Get the Type of interrupt */
@@ -66,8 +67,8 @@ static irqreturn_t l3_interrupt_handler(int irq, void *_l3)
66 * to determine the source 67 * to determine the source
67 */ 68 */
68 base = l3->l3_base[i]; 69 base = l3->l3_base[i];
69 err_reg = __raw_readl(base + l3_flagmux[i] + 70 err_reg = readl_relaxed(base + l3_flagmux[i] +
70 + L3_FLAGMUX_REGERR0 + (inttype << 3)); 71 L3_FLAGMUX_REGERR0 + (inttype << 3));
71 72
72 /* Get the corresponding error and analyse */ 73 /* Get the corresponding error and analyse */
73 if (err_reg) { 74 if (err_reg) {
@@ -76,10 +77,14 @@ static irqreturn_t l3_interrupt_handler(int irq, void *_l3)
76 77
77 /* Read the stderrlog_main_source from clk domain */ 78 /* Read the stderrlog_main_source from clk domain */
78 l3_targ_base = base + *(l3_targ[i] + err_src); 79 l3_targ_base = base + *(l3_targ[i] + err_src);
79 std_err_main = __raw_readl(l3_targ_base + 80 l3_targ_stderr = l3_targ_base + L3_TARG_STDERRLOG_MAIN;
80 L3_TARG_STDERRLOG_MAIN); 81 l3_targ_slvofslsb = l3_targ_base +
81 masterid = __raw_readl(l3_targ_base + 82 L3_TARG_STDERRLOG_SLVOFSLSB;
82 L3_TARG_STDERRLOG_MSTADDR); 83 l3_targ_mstaddr = l3_targ_base +
84 L3_TARG_STDERRLOG_MSTADDR;
85
86 std_err_main = readl_relaxed(l3_targ_stderr);
87 masterid = readl_relaxed(l3_targ_mstaddr);
83 88
84 switch (std_err_main & CUSTOM_ERROR) { 89 switch (std_err_main & CUSTOM_ERROR) {
85 case STANDARD_ERROR: 90 case STANDARD_ERROR:
@@ -87,12 +92,10 @@ static irqreturn_t l3_interrupt_handler(int irq, void *_l3)
87 l3_targ_inst_name[i][err_src]; 92 l3_targ_inst_name[i][err_src];
88 WARN(true, "L3 standard error: TARGET:%s at address 0x%x\n", 93 WARN(true, "L3 standard error: TARGET:%s at address 0x%x\n",
89 target_name, 94 target_name,
90 __raw_readl(l3_targ_base + 95 readl_relaxed(l3_targ_slvofslsb));
91 L3_TARG_STDERRLOG_SLVOFSLSB));
92 /* clear the std error log*/ 96 /* clear the std error log*/
93 clear = std_err_main | CLEAR_STDERR_LOG; 97 clear = std_err_main | CLEAR_STDERR_LOG;
94 writel(clear, l3_targ_base + 98 writel_relaxed(clear, l3_targ_stderr);
95 L3_TARG_STDERRLOG_MAIN);
96 break; 99 break;
97 100
98 case CUSTOM_ERROR: 101 case CUSTOM_ERROR:
@@ -107,8 +110,7 @@ static irqreturn_t l3_interrupt_handler(int irq, void *_l3)
107 master_name, target_name); 110 master_name, target_name);
108 /* clear the std error log*/ 111 /* clear the std error log*/
109 clear = std_err_main | CLEAR_STDERR_LOG; 112 clear = std_err_main | CLEAR_STDERR_LOG;
110 writel(clear, l3_targ_base + 113 writel_relaxed(clear, l3_targ_stderr);
111 L3_TARG_STDERRLOG_MAIN);
112 break; 114 break;
113 115
114 default: 116 default: