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authorNishanth Menon <nm@ti.com>2014-04-14 10:57:50 -0400
committerNishanth Menon <nm@ti.com>2014-05-05 15:33:40 -0400
commit97708c08c9955306742872ff7f2e47faec864ee7 (patch)
treec5dcf17ecfeeee0472ab7ddfe082fdf6bd43d020 /drivers/bus
parent0659452dd2b2602058b80cfdcc673e98f2a67184 (diff)
bus: omap_l3_noc: convert flagmux information into a structure
This allows us to encompass target information and flag mux offset that points to the target information into a singular structure. This saves us the need to look up two different arrays indexed by module ID for information. This allows us to reduce the static target information allocation to just the ones that are documented. Signed-off-by: Nishanth Menon <nm@ti.com> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Tested-by: Darren Etheridge <detheridge@ti.com> Tested-by: Sekhar Nori <nsekhar@ti.com>
Diffstat (limited to 'drivers/bus')
-rw-r--r--drivers/bus/omap_l3_noc.c16
-rw-r--r--drivers/bus/omap_l3_noc.h70
2 files changed, 56 insertions, 30 deletions
diff --git a/drivers/bus/omap_l3_noc.c b/drivers/bus/omap_l3_noc.c
index 7e0a988ad579..9524452ee12c 100644
--- a/drivers/bus/omap_l3_noc.c
+++ b/drivers/bus/omap_l3_noc.c
@@ -60,6 +60,7 @@ static irqreturn_t l3_interrupt_handler(int irq, void *_l3)
60 void __iomem *l3_targ_stderr, *l3_targ_slvofslsb, *l3_targ_mstaddr; 60 void __iomem *l3_targ_stderr, *l3_targ_slvofslsb, *l3_targ_mstaddr;
61 char *target_name, *master_name = "UN IDENTIFIED"; 61 char *target_name, *master_name = "UN IDENTIFIED";
62 struct l3_target_data *l3_targ_inst; 62 struct l3_target_data *l3_targ_inst;
63 struct l3_flagmux_data *flag_mux;
63 struct l3_masters_data *master; 64 struct l3_masters_data *master;
64 65
65 /* Get the Type of interrupt */ 66 /* Get the Type of interrupt */
@@ -71,7 +72,8 @@ static irqreturn_t l3_interrupt_handler(int irq, void *_l3)
71 * to determine the source 72 * to determine the source
72 */ 73 */
73 base = l3->l3_base[i]; 74 base = l3->l3_base[i];
74 err_reg = readl_relaxed(base + l3->l3_flagmux[i] + 75 flag_mux = l3->l3_flagmux[i];
76 err_reg = readl_relaxed(base + flag_mux->offset +
75 L3_FLAGMUX_REGERR0 + (inttype << 3)); 77 L3_FLAGMUX_REGERR0 + (inttype << 3));
76 78
77 /* Get the corresponding error and analyse */ 79 /* Get the corresponding error and analyse */
@@ -82,9 +84,13 @@ static irqreturn_t l3_interrupt_handler(int irq, void *_l3)
82 /* We DONOT expect err_src to go out of bounds */ 84 /* We DONOT expect err_src to go out of bounds */
83 BUG_ON(err_src > MAX_CLKDM_TARGETS); 85 BUG_ON(err_src > MAX_CLKDM_TARGETS);
84 86
85 l3_targ_inst = &l3->l3_targ[i][err_src]; 87 if (err_src < flag_mux->num_targ_data) {
86 target_name = l3_targ_inst->name; 88 l3_targ_inst = &flag_mux->l3_targ[err_src];
87 l3_targ_base = base + l3_targ_inst->offset; 89 target_name = l3_targ_inst->name;
90 l3_targ_base = base + l3_targ_inst->offset;
91 } else {
92 target_name = L3_TARGET_NOT_SUPPORTED;
93 }
88 94
89 /* 95 /*
90 * If we do not know of a register offset to decode 96 * If we do not know of a register offset to decode
@@ -104,7 +110,7 @@ static irqreturn_t l3_interrupt_handler(int irq, void *_l3)
104 inttype ? "debug" : "application", 110 inttype ? "debug" : "application",
105 err_src, i, "(unclearable)"); 111 err_src, i, "(unclearable)");
106 112
107 mask_reg = base + l3->l3_flagmux[i] + 113 mask_reg = base + flag_mux->offset +
108 L3_FLAGMUX_MASK0 + (inttype << 3); 114 L3_FLAGMUX_MASK0 + (inttype << 3);
109 mask_val = readl_relaxed(mask_reg); 115 mask_val = readl_relaxed(mask_reg);
110 mask_val &= ~(1 << err_src); 116 mask_val &= ~(1 << err_src);
diff --git a/drivers/bus/omap_l3_noc.h b/drivers/bus/omap_l3_noc.h
index e60865fe5965..64869fe656e5 100644
--- a/drivers/bus/omap_l3_noc.h
+++ b/drivers/bus/omap_l3_noc.h
@@ -17,8 +17,8 @@
17#ifndef __OMAP_L3_NOC_H 17#ifndef __OMAP_L3_NOC_H
18#define __OMAP_L3_NOC_H 18#define __OMAP_L3_NOC_H
19 19
20#define OMAP_L3_MODULES 3
21#define MAX_L3_MODULES 3 20#define MAX_L3_MODULES 3
21#define MAX_CLKDM_TARGETS 31
22 22
23#define CLEAR_STDERR_LOG (1 << 31) 23#define CLEAR_STDERR_LOG (1 << 31)
24#define CUSTOM_ERROR 0x2 24#define CUSTOM_ERROR 0x2
@@ -36,8 +36,6 @@
36 36
37#define L3_TARGET_NOT_SUPPORTED NULL 37#define L3_TARGET_NOT_SUPPORTED NULL
38 38
39#define MAX_CLKDM_TARGETS 31
40
41/** 39/**
42 * struct l3_masters_data - L3 Master information 40 * struct l3_masters_data - L3 Master information
43 * @id: ID of the L3 Master 41 * @id: ID of the L3 Master
@@ -60,21 +58,32 @@ struct l3_target_data {
60 char *name; 58 char *name;
61}; 59};
62 60
61/**
62 * struct l3_flagmux_data - Flag Mux information
63 * @offset: offset from base for flagmux register
64 * @l3_targ: array indexed by flagmux index (bit offset) pointing to the
65 * target data. unsupported ones are marked with
66 * L3_TARGET_NOT_SUPPORTED
67 * @num_targ_data: number of entries in target data
68 */
69struct l3_flagmux_data {
70 u32 offset;
71 struct l3_target_data *l3_targ;
72 u8 num_targ_data;
73};
74
63 75
64/** 76/**
65 * struct omap_l3 - Description of data relevant for L3 bus. 77 * struct omap_l3 - Description of data relevant for L3 bus.
66 * @dev: device representing the bus (populated runtime) 78 * @dev: device representing the bus (populated runtime)
67 * @l3_base: base addresses of modules (populated runtime) 79 * @l3_base: base addresses of modules (populated runtime)
68 * @l3_flag_mux: array containing offsets to flag mux per module 80 * @l3_flag_mux: array containing flag mux data per module
69 * offset from corresponding module base indexed per 81 * offset from corresponding module base indexed per
70 * module. 82 * module.
71 * @num_modules: number of clock domains / modules. 83 * @num_modules: number of clock domains / modules.
72 * @l3_masters: array pointing to master data containing name and register 84 * @l3_masters: array pointing to master data containing name and register
73 * offset for the master. 85 * offset for the master.
74 * @num_master: number of masters 86 * @num_master: number of masters
75 * @l3_targ: array indexed by flagmux index (bit offset) pointing to the
76 * target data. unsupported ones are marked with
77 * L3_TARGET_NOT_SUPPORTED
78 * @debug_irq: irq number of the debug interrupt (populated runtime) 87 * @debug_irq: irq number of the debug interrupt (populated runtime)
79 * @app_irq: irq number of the application interrupt (populated runtime) 88 * @app_irq: irq number of the application interrupt (populated runtime)
80 */ 89 */
@@ -82,25 +91,17 @@ struct omap_l3 {
82 struct device *dev; 91 struct device *dev;
83 92
84 void __iomem *l3_base[MAX_L3_MODULES]; 93 void __iomem *l3_base[MAX_L3_MODULES];
85 u32 *l3_flagmux; 94 struct l3_flagmux_data **l3_flagmux;
86 int num_modules; 95 int num_modules;
87 96
88 struct l3_masters_data *l3_masters; 97 struct l3_masters_data *l3_masters;
89 int num_masters; 98 int num_masters;
90 99
91 struct l3_target_data **l3_targ;
92
93 int debug_irq; 100 int debug_irq;
94 int app_irq; 101 int app_irq;
95}; 102};
96 103
97static u32 omap_l3_flagmux[OMAP_L3_MODULES] = { 104static struct l3_target_data omap_l3_target_data_clk1[] = {
98 0x500,
99 0x1000,
100 0X0200
101};
102
103static struct l3_target_data omap_l3_target_data_clk1[MAX_CLKDM_TARGETS] = {
104 {0x100, "DMM1",}, 105 {0x100, "DMM1",},
105 {0x200, "DMM2",}, 106 {0x200, "DMM2",},
106 {0x300, "ABE",}, 107 {0x300, "ABE",},
@@ -110,7 +111,14 @@ static struct l3_target_data omap_l3_target_data_clk1[MAX_CLKDM_TARGETS] = {
110 {0x900, "L4WAKEUP",}, 111 {0x900, "L4WAKEUP",},
111}; 112};
112 113
113static struct l3_target_data omap_l3_target_data_clk2[MAX_CLKDM_TARGETS] = { 114static struct l3_flagmux_data omap_l3_flagmux_clk1 = {
115 .offset = 0x500,
116 .l3_targ = omap_l3_target_data_clk1,
117 .num_targ_data = ARRAY_SIZE(omap_l3_target_data_clk1),
118};
119
120
121static struct l3_target_data omap_l3_target_data_clk2[] = {
114 {0x500, "CORTEXM3",}, 122 {0x500, "CORTEXM3",},
115 {0x300, "DSS",}, 123 {0x300, "DSS",},
116 {0x100, "GPMC",}, 124 {0x100, "GPMC",},
@@ -134,12 +142,25 @@ static struct l3_target_data omap_l3_target_data_clk2[MAX_CLKDM_TARGETS] = {
134 {0x1700, "LLI",}, 142 {0x1700, "LLI",},
135}; 143};
136 144
137static struct l3_target_data omap_l3_target_data_clk3[MAX_CLKDM_TARGETS] = { 145static struct l3_flagmux_data omap_l3_flagmux_clk2 = {
146 .offset = 0x1000,
147 .l3_targ = omap_l3_target_data_clk2,
148 .num_targ_data = ARRAY_SIZE(omap_l3_target_data_clk2),
149};
150
151
152static struct l3_target_data omap_l3_target_data_clk3[] = {
138 {0x0100, "EMUSS",}, 153 {0x0100, "EMUSS",},
139 {0x0300, "DEBUG SOURCE",}, 154 {0x0300, "DEBUG SOURCE",},
140 {0x0, "HOST CLK3",}, 155 {0x0, "HOST CLK3",},
141}; 156};
142 157
158static struct l3_flagmux_data omap_l3_flagmux_clk3 = {
159 .offset = 0x0200,
160 .l3_targ = omap_l3_target_data_clk3,
161 .num_targ_data = ARRAY_SIZE(omap_l3_target_data_clk3),
162};
163
143static struct l3_masters_data omap_l3_masters[] = { 164static struct l3_masters_data omap_l3_masters[] = {
144 { 0x0 , "MPU"}, 165 { 0x0 , "MPU"},
145 { 0x10, "CS_ADP"}, 166 { 0x10, "CS_ADP"},
@@ -168,18 +189,17 @@ static struct l3_masters_data omap_l3_masters[] = {
168 { 0xC8, "USBHOSTFS"} 189 { 0xC8, "USBHOSTFS"}
169}; 190};
170 191
171static struct l3_target_data *omap_l3_targ[OMAP_L3_MODULES] = { 192static struct l3_flagmux_data *omap_l3_flagmux[] = {
172 omap_l3_target_data_clk1, 193 &omap_l3_flagmux_clk1,
173 omap_l3_target_data_clk2, 194 &omap_l3_flagmux_clk2,
174 omap_l3_target_data_clk3, 195 &omap_l3_flagmux_clk3,
175}; 196};
176 197
177static const struct omap_l3 omap_l3_data = { 198static const struct omap_l3 omap_l3_data = {
178 .l3_flagmux = omap_l3_flagmux, 199 .l3_flagmux = omap_l3_flagmux,
179 .num_modules = OMAP_L3_MODULES, 200 .num_modules = ARRAY_SIZE(omap_l3_flagmux),
180 .l3_masters = omap_l3_masters, 201 .l3_masters = omap_l3_masters,
181 .num_masters = ARRAY_SIZE(omap_l3_masters), 202 .num_masters = ARRAY_SIZE(omap_l3_masters),
182 .l3_targ = omap_l3_targ,
183}; 203};
184 204
185#endif /* __OMAP_L3_NOC_H */ 205#endif /* __OMAP_L3_NOC_H */