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authorLinus Torvalds <torvalds@linux-foundation.org>2015-04-22 12:18:17 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2015-04-22 12:18:17 -0400
commit7d2b6ef19cf0f98cef17aa5185de3631a618710a (patch)
treed4e87f3c47837fef59ef15273f89f68b73d963af /drivers/bus
parent5c73cc4b6c83e88863a5de869cc5df3b913aef4a (diff)
parent7415d97ee2b809119270fc3a365968ff8d4f544b (diff)
Merge tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC driver updates from Olof Johansson: "Driver updates for v4.1. Some of these are for drivers/soc, where we find more and more SoC-specific drivers these days. Some are for other driver subsystems where we have received acks from the appropriate maintainers. The larger parts of this branch are: - MediaTek support for their PMIC wrapper interface, a high-level interface for talking to the system PMIC over a dedicated I2C interface. - Qualcomm SCM driver has been moved to drivers/firmware. It's used for CPU up/down and needs to be in a shared location for arm/arm64 common code. - cleanup of ARM-CCI PMU code. - another set of cleanusp to the OMAP GPMC code" * tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (43 commits) soc/mediatek: Remove unused variables clocksource: atmel-st: select MFD_SYSCON soc: mediatek: Add PMIC wrapper for MT8135 and MT8173 SoCs arm-cci: Fix CCI PMU event validation arm-cci: Split the code for PMU vs driver support arm-cci: Get rid of secure transactions for PMU driver arm-cci: Abstract the CCI400 PMU specific definitions arm-cci: Rearrange code for splitting PMU vs driver code drivers: cci: reject groups spanning multiple HW PMUs ARM: at91: remove useless include clocksource: atmel-st: remove mach/hardware dependency clocksource: atmel-st: use syscon/regmap ARM: at91: time: move the system timer driver to drivers/clocksource ARM: at91: properly initialize timer ARM: at91: at91rm9200: remove deprecated arm_pm_restart watchdog: at91rm9200: implement restart handler watchdog: at91rm9200: use the system timer syscon mfd: syscon: Add atmel system timer registers definition ARM: at91/dt: declare atmel,at91rm9200-st as a syscon soc: qcom: gsbi: Add support for ADM CRCI muxing ...
Diffstat (limited to 'drivers/bus')
-rw-r--r--drivers/bus/Kconfig73
-rw-r--r--drivers/bus/Makefile17
-rw-r--r--drivers/bus/arm-cci.c517
-rw-r--r--drivers/bus/simple-pm-bus.c58
4 files changed, 410 insertions, 255 deletions
diff --git a/drivers/bus/Kconfig b/drivers/bus/Kconfig
index cbddbaddb347..a1d4af6df3f5 100644
--- a/drivers/bus/Kconfig
+++ b/drivers/bus/Kconfig
@@ -4,6 +4,41 @@
4 4
5menu "Bus devices" 5menu "Bus devices"
6 6
7config ARM_CCI
8 bool
9
10config ARM_CCI400_COMMON
11 bool
12 select ARM_CCI
13
14config ARM_CCI400_PMU
15 bool "ARM CCI400 PMU support"
16 default y
17 depends on ARM || ARM64
18 depends on HW_PERF_EVENTS
19 select ARM_CCI400_COMMON
20 help
21 Support for PMU events monitoring on the ARM CCI cache coherent
22 interconnect.
23
24 If unsure, say Y
25
26config ARM_CCI400_PORT_CTRL
27 bool
28 depends on ARM && OF && CPU_V7
29 select ARM_CCI400_COMMON
30 help
31 Low level power management driver for CCI400 cache coherent
32 interconnect for ARM platforms.
33
34config ARM_CCN
35 bool "ARM CCN driver support"
36 depends on ARM || ARM64
37 depends on PERF_EVENTS
38 help
39 PMU (perf) driver supporting the ARM CCN (Cache Coherent Network)
40 interconnect.
41
7config BRCMSTB_GISB_ARB 42config BRCMSTB_GISB_ARB
8 bool "Broadcom STB GISB bus arbiter" 43 bool "Broadcom STB GISB bus arbiter"
9 depends on ARM || MIPS 44 depends on ARM || MIPS
@@ -40,15 +75,6 @@ config MVEBU_MBUS
40 Driver needed for the MBus configuration on Marvell EBU SoCs 75 Driver needed for the MBus configuration on Marvell EBU SoCs
41 (Kirkwood, Dove, Orion5x, MV78XX0 and Armada 370/XP). 76 (Kirkwood, Dove, Orion5x, MV78XX0 and Armada 370/XP).
42 77
43config OMAP_OCP2SCP
44 tristate "OMAP OCP2SCP DRIVER"
45 depends on ARCH_OMAP2PLUS
46 help
47 Driver to enable ocp2scp module which transforms ocp interface
48 protocol to scp protocol. In OMAP4, USB PHY is connected via
49 OCP2SCP and in OMAP5, both USB PHY and SATA PHY is connected via
50 OCP2SCP.
51
52config OMAP_INTERCONNECT 78config OMAP_INTERCONNECT
53 tristate "OMAP INTERCONNECT DRIVER" 79 tristate "OMAP INTERCONNECT DRIVER"
54 depends on ARCH_OMAP2PLUS 80 depends on ARCH_OMAP2PLUS
@@ -56,20 +82,27 @@ config OMAP_INTERCONNECT
56 help 82 help
57 Driver to enable OMAP interconnect error handling driver. 83 Driver to enable OMAP interconnect error handling driver.
58 84
59config ARM_CCI 85config OMAP_OCP2SCP
60 bool "ARM CCI driver support" 86 tristate "OMAP OCP2SCP DRIVER"
61 depends on ARM && OF && CPU_V7 87 depends on ARCH_OMAP2PLUS
62 help 88 help
63 Driver supporting the CCI cache coherent interconnect for ARM 89 Driver to enable ocp2scp module which transforms ocp interface
64 platforms. 90 protocol to scp protocol. In OMAP4, USB PHY is connected via
91 OCP2SCP and in OMAP5, both USB PHY and SATA PHY is connected via
92 OCP2SCP.
65 93
66config ARM_CCN 94config SIMPLE_PM_BUS
67 bool "ARM CCN driver support" 95 bool "Simple Power-Managed Bus Driver"
68 depends on ARM || ARM64 96 depends on OF && PM
69 depends on PERF_EVENTS 97 depends on ARCH_SHMOBILE || COMPILE_TEST
70 help 98 help
71 PMU (perf) driver supporting the ARM CCN (Cache Coherent Network) 99 Driver for transparent busses that don't need a real driver, but
72 interconnect. 100 where the bus controller is part of a PM domain, or under the control
101 of a functional clock, and thus relies on runtime PM for managing
102 this PM domain and/or clock.
103 An example of such a bus controller is the Renesas Bus State
104 Controller (BSC, sometimes called "LBSC within Bus Bridge", or
105 "External Bus Interface") as found on several Renesas ARM SoCs.
73 106
74config VEXPRESS_CONFIG 107config VEXPRESS_CONFIG
75 bool "Versatile Express configuration bus" 108 bool "Versatile Express configuration bus"
diff --git a/drivers/bus/Makefile b/drivers/bus/Makefile
index 807dd17ef2f8..790e7b933fb2 100644
--- a/drivers/bus/Makefile
+++ b/drivers/bus/Makefile
@@ -2,17 +2,18 @@
2# Makefile for the bus drivers. 2# Makefile for the bus drivers.
3# 3#
4 4
5# Interconnect bus drivers for ARM platforms
6obj-$(CONFIG_ARM_CCI) += arm-cci.o
7obj-$(CONFIG_ARM_CCN) += arm-ccn.o
8
5obj-$(CONFIG_BRCMSTB_GISB_ARB) += brcmstb_gisb.o 9obj-$(CONFIG_BRCMSTB_GISB_ARB) += brcmstb_gisb.o
6obj-$(CONFIG_IMX_WEIM) += imx-weim.o 10obj-$(CONFIG_IMX_WEIM) += imx-weim.o
7obj-$(CONFIG_MIPS_CDMM) += mips_cdmm.o 11obj-$(CONFIG_MIPS_CDMM) += mips_cdmm.o
8obj-$(CONFIG_MVEBU_MBUS) += mvebu-mbus.o 12obj-$(CONFIG_MVEBU_MBUS) += mvebu-mbus.o
9obj-$(CONFIG_OMAP_OCP2SCP) += omap-ocp2scp.o
10 13
11# Interconnect bus driver for OMAP SoCs. 14# Interconnect bus driver for OMAP SoCs.
12obj-$(CONFIG_OMAP_INTERCONNECT) += omap_l3_smx.o omap_l3_noc.o 15obj-$(CONFIG_OMAP_INTERCONNECT) += omap_l3_smx.o omap_l3_noc.o
13 16
14# Interconnect bus drivers for ARM platforms 17obj-$(CONFIG_OMAP_OCP2SCP) += omap-ocp2scp.o
15obj-$(CONFIG_ARM_CCI) += arm-cci.o 18obj-$(CONFIG_SIMPLE_PM_BUS) += simple-pm-bus.o
16obj-$(CONFIG_ARM_CCN) += arm-ccn.o
17
18obj-$(CONFIG_VEXPRESS_CONFIG) += vexpress-config.o 19obj-$(CONFIG_VEXPRESS_CONFIG) += vexpress-config.o
diff --git a/drivers/bus/arm-cci.c b/drivers/bus/arm-cci.c
index 84fd66057dad..b854125e4831 100644
--- a/drivers/bus/arm-cci.c
+++ b/drivers/bus/arm-cci.c
@@ -29,41 +29,36 @@
29#include <asm/cacheflush.h> 29#include <asm/cacheflush.h>
30#include <asm/smp_plat.h> 30#include <asm/smp_plat.h>
31 31
32#define DRIVER_NAME "CCI-400" 32static void __iomem *cci_ctrl_base;
33#define DRIVER_NAME_PMU DRIVER_NAME " PMU" 33static unsigned long cci_ctrl_phys;
34
35#define CCI_PORT_CTRL 0x0
36#define CCI_CTRL_STATUS 0xc
37
38#define CCI_ENABLE_SNOOP_REQ 0x1
39#define CCI_ENABLE_DVM_REQ 0x2
40#define CCI_ENABLE_REQ (CCI_ENABLE_SNOOP_REQ | CCI_ENABLE_DVM_REQ)
41 34
35#ifdef CONFIG_ARM_CCI400_PORT_CTRL
42struct cci_nb_ports { 36struct cci_nb_ports {
43 unsigned int nb_ace; 37 unsigned int nb_ace;
44 unsigned int nb_ace_lite; 38 unsigned int nb_ace_lite;
45}; 39};
46 40
47enum cci_ace_port_type { 41static const struct cci_nb_ports cci400_ports = {
48 ACE_INVALID_PORT = 0x0, 42 .nb_ace = 2,
49 ACE_PORT, 43 .nb_ace_lite = 3
50 ACE_LITE_PORT,
51}; 44};
52 45
53struct cci_ace_port { 46#define CCI400_PORTS_DATA (&cci400_ports)
54 void __iomem *base; 47#else
55 unsigned long phys; 48#define CCI400_PORTS_DATA (NULL)
56 enum cci_ace_port_type type; 49#endif
57 struct device_node *dn;
58};
59 50
60static struct cci_ace_port *ports; 51static const struct of_device_id arm_cci_matches[] = {
61static unsigned int nb_cci_ports; 52#ifdef CONFIG_ARM_CCI400_COMMON
53