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authorKevin Gan <ganhy@marvell.com>2011-04-08 21:19:33 -0400
committerGustavo F. Padovan <padovan@profusion.mobi>2011-04-13 11:20:05 -0400
commit9f72c1d977e47a7d182d49ea131067cba0a96ab8 (patch)
tree2f0f2627c3cad459994639617bd55e050fd1d17a /drivers/bluetooth/btmrvl_sdio.h
parentb86ed368f1f0b19de1918c57e4b056e73d5613a0 (diff)
Bluetooth: btmrvl: support Marvell Bluetooth device SD8787
The SD8787 firmware image is shared with mwifiex driver. Whoever gets loaded first will be responsible for firmware downloading. Signed-off-by: Kevin Gan <ganhy@marvell.com> Signed-off-by: Tristan Xu <xurf@marvell.com> Signed-off-by: Bing Zhao <bzhao@marvell.com> Signed-off-by: Gustavo F. Padovan <padovan@profusion.mobi>
Diffstat (limited to 'drivers/bluetooth/btmrvl_sdio.h')
-rw-r--r--drivers/bluetooth/btmrvl_sdio.h68
1 files changed, 36 insertions, 32 deletions
diff --git a/drivers/bluetooth/btmrvl_sdio.h b/drivers/bluetooth/btmrvl_sdio.h
index 27329f107e5a..43d35a609ca9 100644
--- a/drivers/bluetooth/btmrvl_sdio.h
+++ b/drivers/bluetooth/btmrvl_sdio.h
@@ -47,44 +47,46 @@
47/* Max retry number of CMD53 write */ 47/* Max retry number of CMD53 write */
48#define MAX_WRITE_IOMEM_RETRY 2 48#define MAX_WRITE_IOMEM_RETRY 2
49 49
50/* Host Control Registers */ 50/* register bitmasks */
51#define IO_PORT_0_REG 0x00 51#define HOST_POWER_UP BIT(1)
52#define IO_PORT_1_REG 0x01 52#define HOST_CMD53_FIN BIT(2)
53#define IO_PORT_2_REG 0x02 53
54 54#define HIM_DISABLE 0xff
55#define CONFIG_REG 0x03 55#define HIM_ENABLE (BIT(0) | BIT(1))
56#define HOST_POWER_UP BIT(1) 56
57#define HOST_CMD53_FIN BIT(2) 57#define UP_LD_HOST_INT_STATUS BIT(0)
58 58#define DN_LD_HOST_INT_STATUS BIT(1)
59#define HOST_INT_MASK_REG 0x04 59
60#define HIM_DISABLE 0xff 60#define DN_LD_CARD_RDY BIT(0)
61#define HIM_ENABLE (BIT(0) | BIT(1)) 61#define CARD_IO_READY BIT(3)
62 62
63#define HOST_INTSTATUS_REG 0x05 63#define FIRMWARE_READY 0xfedc
64#define UP_LD_HOST_INT_STATUS BIT(0) 64
65#define DN_LD_HOST_INT_STATUS BIT(1) 65
66 66struct btmrvl_sdio_card_reg {
67/* Card Control Registers */ 67 u8 cfg;
68#define SQ_READ_BASE_ADDRESS_A0_REG 0x10 68 u8 host_int_mask;
69#define SQ_READ_BASE_ADDRESS_A1_REG 0x11 69 u8 host_intstatus;
70 70 u8 card_status;
71#define CARD_STATUS_REG 0x20 71 u8 sq_read_base_addr_a0;
72#define DN_LD_CARD_RDY BIT(0) 72 u8 sq_read_base_addr_a1;
73#define CARD_IO_READY BIT(3) 73 u8 card_revision;
74 74 u8 card_fw_status0;
75#define CARD_FW_STATUS0_REG 0x40 75 u8 card_fw_status1;
76#define CARD_FW_STATUS1_REG 0x41 76 u8 card_rx_len;
77#define FIRMWARE_READY 0xfedc 77 u8 card_rx_unit;
78 78 u8 io_port_0;
79#define CARD_RX_LEN_REG 0x42 79 u8 io_port_1;
80#define CARD_RX_UNIT_REG 0x43 80 u8 io_port_2;
81 81};
82 82
83struct btmrvl_sdio_card { 83struct btmrvl_sdio_card {
84 struct sdio_func *func; 84 struct sdio_func *func;
85 u32 ioport; 85 u32 ioport;
86 const char *helper; 86 const char *helper;
87 const char *firmware; 87 const char *firmware;
88 const struct btmrvl_sdio_card_reg *reg;
89 u16 sd_blksz_fw_dl;
88 u8 rx_unit; 90 u8 rx_unit;
89 struct btmrvl_private *priv; 91 struct btmrvl_private *priv;
90}; 92};
@@ -92,6 +94,8 @@ struct btmrvl_sdio_card {
92struct btmrvl_sdio_device { 94struct btmrvl_sdio_device {
93 const char *helper; 95 const char *helper;
94 const char *firmware; 96 const char *firmware;
97 const struct btmrvl_sdio_card_reg *reg;
98 u16 sd_blksz_fw_dl;
95}; 99};
96 100
97 101