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authorJames Bottomley <jejb@titanic.(none)>2005-05-20 16:27:44 -0400
committerJames Bottomley <jejb@titanic.(none)>2005-05-20 16:27:44 -0400
commitad34ea2cc3845ef4dcd7d12fb0fa8484734bd672 (patch)
treead434400f5ecaa33b433c8f830e40792d8d6c05c /drivers/block
parent90356ac3194bf91a441a5f9c3067af386ef62462 (diff)
parent88d7bd8cb9eb8d64bf7997600b0d64f7834047c5 (diff)
merge by hand - fix up rejections in Documentation/DocBook/Makefile
Diffstat (limited to 'drivers/block')
-rw-r--r--drivers/block/DAC960.c132
-rw-r--r--drivers/block/DAC960.h317
-rw-r--r--drivers/block/Kconfig4
-rw-r--r--drivers/block/aoe/aoe.h2
-rw-r--r--drivers/block/aoe/aoeblk.c13
-rw-r--r--drivers/block/aoe/aoedev.c11
-rw-r--r--drivers/block/aoe/aoenet.c17
-rw-r--r--drivers/block/floppy.c2
-rw-r--r--drivers/block/genhd.c4
-rw-r--r--drivers/block/nbd.c16
-rw-r--r--drivers/block/noop-iosched.c27
11 files changed, 504 insertions, 41 deletions
diff --git a/drivers/block/DAC960.c b/drivers/block/DAC960.c
index 423bbf2000d2..3760edfdc65c 100644
--- a/drivers/block/DAC960.c
+++ b/drivers/block/DAC960.c
@@ -3,6 +3,7 @@
3 Linux Driver for Mylex DAC960/AcceleRAID/eXtremeRAID PCI RAID Controllers 3 Linux Driver for Mylex DAC960/AcceleRAID/eXtremeRAID PCI RAID Controllers
4 4
5 Copyright 1998-2001 by Leonard N. Zubkoff <lnz@dandelion.com> 5 Copyright 1998-2001 by Leonard N. Zubkoff <lnz@dandelion.com>
6 Portions Copyright 2002 by Mylex (An IBM Business Unit)
6 7
7 This program is free software; you may redistribute and/or modify it under 8 This program is free software; you may redistribute and/or modify it under
8 the terms of the GNU General Public License Version 2 as published by the 9 the terms of the GNU General Public License Version 2 as published by the
@@ -532,6 +533,34 @@ static void DAC960_WaitForCommand(DAC960_Controller_T *Controller)
532 spin_lock_irq(&Controller->queue_lock); 533 spin_lock_irq(&Controller->queue_lock);
533} 534}
534 535
536/*
537 DAC960_GEM_QueueCommand queues Command for DAC960 GEM Series Controllers.
538*/
539
540static void DAC960_GEM_QueueCommand(DAC960_Command_T *Command)
541{
542 DAC960_Controller_T *Controller = Command->Controller;
543 void __iomem *ControllerBaseAddress = Controller->BaseAddress;
544 DAC960_V2_CommandMailbox_T *CommandMailbox = &Command->V2.CommandMailbox;
545 DAC960_V2_CommandMailbox_T *NextCommandMailbox =
546 Controller->V2.NextCommandMailbox;
547
548 CommandMailbox->Common.CommandIdentifier = Command->CommandIdentifier;
549 DAC960_GEM_WriteCommandMailbox(NextCommandMailbox, CommandMailbox);
550
551 if (Controller->V2.PreviousCommandMailbox1->Words[0] == 0 ||
552 Controller->V2.PreviousCommandMailbox2->Words[0] == 0)
553 DAC960_GEM_MemoryMailboxNewCommand(ControllerBaseAddress);
554
555 Controller->V2.PreviousCommandMailbox2 =
556 Controller->V2.PreviousCommandMailbox1;
557 Controller->V2.PreviousCommandMailbox1 = NextCommandMailbox;
558
559 if (++NextCommandMailbox > Controller->V2.LastCommandMailbox)
560 NextCommandMailbox = Controller->V2.FirstCommandMailbox;
561
562 Controller->V2.NextCommandMailbox = NextCommandMailbox;
563}
535 564
536/* 565/*
537 DAC960_BA_QueueCommand queues Command for DAC960 BA Series Controllers. 566 DAC960_BA_QueueCommand queues Command for DAC960 BA Series Controllers.
@@ -1464,6 +1493,17 @@ static boolean DAC960_V2_EnableMemoryMailboxInterface(DAC960_Controller_T
1464 Controller->V2.FirstStatusMailboxDMA; 1493 Controller->V2.FirstStatusMailboxDMA;
1465 switch (Controller->HardwareType) 1494 switch (Controller->HardwareType)
1466 { 1495 {
1496 case DAC960_GEM_Controller:
1497 while (DAC960_GEM_HardwareMailboxFullP(ControllerBaseAddress))
1498 udelay(1);
1499 DAC960_GEM_WriteHardwareMailbox(ControllerBaseAddress, CommandMailboxDMA);
1500 DAC960_GEM_HardwareMailboxNewCommand(ControllerBaseAddress);
1501 while (!DAC960_GEM_HardwareMailboxStatusAvailableP(ControllerBaseAddress))
1502 udelay(1);
1503 CommandStatus = DAC960_GEM_ReadCommandStatus(ControllerBaseAddress);
1504 DAC960_GEM_AcknowledgeHardwareMailboxInterrupt(ControllerBaseAddress);
1505 DAC960_GEM_AcknowledgeHardwareMailboxStatus(ControllerBaseAddress);
1506 break;
1467 case DAC960_BA_Controller: 1507 case DAC960_BA_Controller:
1468 while (DAC960_BA_HardwareMailboxFullP(ControllerBaseAddress)) 1508 while (DAC960_BA_HardwareMailboxFullP(ControllerBaseAddress))
1469 udelay(1); 1509 udelay(1);
@@ -2627,6 +2667,9 @@ static void DAC960_DetectCleanup(DAC960_Controller_T *Controller)
2627 if (Controller->MemoryMappedAddress) { 2667 if (Controller->MemoryMappedAddress) {
2628 switch(Controller->HardwareType) 2668 switch(Controller->HardwareType)
2629 { 2669 {
2670 case DAC960_GEM_Controller:
2671 DAC960_GEM_DisableInterrupts(Controller->BaseAddress);
2672 break;
2630 case DAC960_BA_Controller: 2673 case DAC960_BA_Controller:
2631 DAC960_BA_DisableInterrupts(Controller->BaseAddress); 2674 DAC960_BA_DisableInterrupts(Controller->BaseAddress);
2632 break; 2675 break;
@@ -2705,6 +2748,9 @@ DAC960_DetectController(struct pci_dev *PCI_Device,
2705 2748
2706 switch (Controller->HardwareType) 2749 switch (Controller->HardwareType)
2707 { 2750 {
2751 case DAC960_GEM_Controller:
2752 Controller->PCI_Address = pci_resource_start(PCI_Device, 0);
2753 break;
2708 case DAC960_BA_Controller: 2754 case DAC960_BA_Controller:
2709 Controller->PCI_Address = pci_resource_start(PCI_Device, 0); 2755 Controller->PCI_Address = pci_resource_start(PCI_Device, 0);
2710 break; 2756 break;
@@ -2756,6 +2802,36 @@ DAC960_DetectController(struct pci_dev *PCI_Device,
2756 BaseAddress = Controller->BaseAddress; 2802 BaseAddress = Controller->BaseAddress;
2757 switch (Controller->HardwareType) 2803 switch (Controller->HardwareType)
2758 { 2804 {
2805 case DAC960_GEM_Controller:
2806 DAC960_GEM_DisableInterrupts(BaseAddress);
2807 DAC960_GEM_AcknowledgeHardwareMailboxStatus(BaseAddress);
2808 udelay(1000);
2809 while (DAC960_GEM_InitializationInProgressP(BaseAddress))
2810 {
2811 if (DAC960_GEM_ReadErrorStatus(BaseAddress, &ErrorStatus,
2812 &Parameter0, &Parameter1) &&
2813 DAC960_ReportErrorStatus(Controller, ErrorStatus,
2814 Parameter0, Parameter1))
2815 goto Failure;
2816 udelay(10);
2817 }
2818 if (!DAC960_V2_EnableMemoryMailboxInterface(Controller))
2819 {
2820 DAC960_Error("Unable to Enable Memory Mailbox Interface "
2821 "for Controller at\n", Controller);
2822 goto Failure;
2823 }
2824 DAC960_GEM_EnableInterrupts(BaseAddress);
2825 Controller->QueueCommand = DAC960_GEM_QueueCommand;
2826 Controller->ReadControllerConfiguration =
2827 DAC960_V2_ReadControllerConfiguration;
2828 Controller->ReadDeviceConfiguration =
2829 DAC960_V2_ReadDeviceConfiguration;
2830 Controller->ReportDeviceConfiguration =
2831 DAC960_V2_ReportDeviceConfiguration;
2832 Controller->QueueReadWriteCommand =
2833 DAC960_V2_QueueReadWriteCommand;
2834 break;
2759 case DAC960_BA_Controller: 2835 case DAC960_BA_Controller:
2760 DAC960_BA_DisableInterrupts(BaseAddress); 2836 DAC960_BA_DisableInterrupts(BaseAddress);
2761 DAC960_BA_AcknowledgeHardwareMailboxStatus(BaseAddress); 2837 DAC960_BA_AcknowledgeHardwareMailboxStatus(BaseAddress);
@@ -5189,6 +5265,47 @@ static void DAC960_V2_ProcessCompletedCommand(DAC960_Command_T *Command)
5189 wake_up(&Controller->CommandWaitQueue); 5265 wake_up(&Controller->CommandWaitQueue);
5190} 5266}
5191 5267
5268/*
5269 DAC960_GEM_InterruptHandler handles hardware interrupts from DAC960 GEM Series
5270 Controllers.
5271*/
5272
5273static irqreturn_t DAC960_GEM_InterruptHandler(int IRQ_Channel,
5274 void *DeviceIdentifier,
5275 struct pt_regs *InterruptRegisters)
5276{
5277 DAC960_Controller_T *Controller = (DAC960_Controller_T *) DeviceIdentifier;
5278 void __iomem *ControllerBaseAddress = Controller->BaseAddress;
5279 DAC960_V2_StatusMailbox_T *NextStatusMailbox;
5280 unsigned long flags;
5281
5282 spin_lock_irqsave(&Controller->queue_lock, flags);
5283 DAC960_GEM_AcknowledgeInterrupt(ControllerBaseAddress);
5284 NextStatusMailbox = Controller->V2.NextStatusMailbox;
5285 while (NextStatusMailbox->Fields.CommandIdentifier > 0)
5286 {
5287 DAC960_V2_CommandIdentifier_T CommandIdentifier =
5288 NextStatusMailbox->Fields.CommandIdentifier;
5289 DAC960_Command_T *Command = Controller->Commands[CommandIdentifier-1];
5290 Command->V2.CommandStatus = NextStatusMailbox->Fields.CommandStatus;
5291 Command->V2.RequestSenseLength =
5292 NextStatusMailbox->Fields.RequestSenseLength;
5293 Command->V2.DataTransferResidue =
5294 NextStatusMailbox->Fields.DataTransferResidue;
5295 NextStatusMailbox->Words[0] = 0;
5296 if (++NextStatusMailbox > Controller->V2.LastStatusMailbox)
5297 NextStatusMailbox = Controller->V2.FirstStatusMailbox;
5298 DAC960_V2_ProcessCompletedCommand(Command);
5299 }
5300 Controller->V2.NextStatusMailbox = NextStatusMailbox;
5301 /*
5302 Attempt to remove additional I/O Requests from the Controller's
5303 I/O Request Queue and queue them to the Controller.
5304 */
5305 DAC960_ProcessRequest(Controller);
5306 spin_unlock_irqrestore(&Controller->queue_lock, flags);
5307 return IRQ_HANDLED;
5308}
5192 5309
5193/* 5310/*
5194 DAC960_BA_InterruptHandler handles hardware interrupts from DAC960 BA Series 5311 DAC960_BA_InterruptHandler handles hardware interrupts from DAC960 BA Series
@@ -6962,6 +7079,14 @@ static void DAC960_gam_cleanup(void)
6962 7079
6963#endif /* DAC960_GAM_MINOR */ 7080#endif /* DAC960_GAM_MINOR */
6964 7081
7082static struct DAC960_privdata DAC960_GEM_privdata = {
7083 .HardwareType = DAC960_GEM_Controller,
7084 .FirmwareType = DAC960_V2_Controller,
7085 .InterruptHandler = DAC960_GEM_InterruptHandler,
7086 .MemoryWindowSize = DAC960_GEM_RegisterWindowSize,
7087};
7088
7089
6965static struct DAC960_privdata DAC960_BA_privdata = { 7090static struct DAC960_privdata DAC960_BA_privdata = {
6966 .HardwareType = DAC960_BA_Controller, 7091 .HardwareType = DAC960_BA_Controller,
6967 .FirmwareType = DAC960_V2_Controller, 7092 .FirmwareType = DAC960_V2_Controller,
@@ -7007,6 +7132,13 @@ static struct DAC960_privdata DAC960_P_privdata = {
7007static struct pci_device_id DAC960_id_table[] = { 7132static struct pci_device_id DAC960_id_table[] = {
7008 { 7133 {
7009 .vendor = PCI_VENDOR_ID_MYLEX, 7134 .vendor = PCI_VENDOR_ID_MYLEX,
7135 .device = PCI_DEVICE_ID_MYLEX_DAC960_GEM,
7136 .subvendor = PCI_ANY_ID,
7137 .subdevice = PCI_ANY_ID,
7138 .driver_data = (unsigned long) &DAC960_GEM_privdata,
7139 },
7140 {
7141 .vendor = PCI_VENDOR_ID_MYLEX,
7010 .device = PCI_DEVICE_ID_MYLEX_DAC960_BA, 7142 .device = PCI_DEVICE_ID_MYLEX_DAC960_BA,
7011 .subvendor = PCI_ANY_ID, 7143 .subvendor = PCI_ANY_ID,
7012 .subdevice = PCI_ANY_ID, 7144 .subdevice = PCI_ANY_ID,
diff --git a/drivers/block/DAC960.h b/drivers/block/DAC960.h
index d5e8e7190c90..a82f37f749a5 100644
--- a/drivers/block/DAC960.h
+++ b/drivers/block/DAC960.h
@@ -2114,7 +2114,8 @@ typedef enum
2114 DAC960_LA_Controller = 3, /* DAC1164P */ 2114 DAC960_LA_Controller = 3, /* DAC1164P */
2115 DAC960_PG_Controller = 4, /* DAC960PTL/PJ/PG */ 2115 DAC960_PG_Controller = 4, /* DAC960PTL/PJ/PG */
2116 DAC960_PD_Controller = 5, /* DAC960PU/PD/PL/P */ 2116 DAC960_PD_Controller = 5, /* DAC960PU/PD/PL/P */
2117 DAC960_P_Controller = 6 /* DAC960PU/PD/PL/P */ 2117 DAC960_P_Controller = 6, /* DAC960PU/PD/PL/P */
2118 DAC960_GEM_Controller = 7, /* AcceleRAID 4/5/600 */
2118} 2119}
2119DAC960_HardwareType_T; 2120DAC960_HardwareType_T;
2120 2121
@@ -2541,6 +2542,320 @@ void dma_addr_writeql(dma_addr_t addr, void __iomem *write_address)
2541} 2542}
2542 2543
2543/* 2544/*
2545 Define the DAC960 GEM Series Controller Interface Register Offsets.
2546 */
2547
2548#define DAC960_GEM_RegisterWindowSize 0x600
2549
2550typedef enum
2551{
2552 DAC960_GEM_InboundDoorBellRegisterReadSetOffset = 0x214,
2553 DAC960_GEM_InboundDoorBellRegisterClearOffset = 0x218,
2554 DAC960_GEM_OutboundDoorBellRegisterReadSetOffset = 0x224,
2555 DAC960_GEM_OutboundDoorBellRegisterClearOffset = 0x228,
2556 DAC960_GEM_InterruptStatusRegisterOffset = 0x208,
2557 DAC960_GEM_InterruptMaskRegisterReadSetOffset = 0x22C,
2558 DAC960_GEM_InterruptMaskRegisterClearOffset = 0x230,
2559 DAC960_GEM_CommandMailboxBusAddressOffset = 0x510,
2560 DAC960_GEM_CommandStatusOffset = 0x518,
2561 DAC960_GEM_ErrorStatusRegisterReadSetOffset = 0x224,
2562 DAC960_GEM_ErrorStatusRegisterClearOffset = 0x228,
2563}
2564DAC960_GEM_RegisterOffsets_T;
2565
2566/*
2567 Define the structure of the DAC960 GEM Series Inbound Door Bell
2568 */
2569
2570typedef union DAC960_GEM_InboundDoorBellRegister
2571{
2572 unsigned int All;
2573 struct {
2574 unsigned int :24;
2575 boolean HardwareMailboxNewCommand:1;
2576 boolean AcknowledgeHardwareMailboxStatus:1;
2577 boolean GenerateInterrupt:1;
2578 boolean ControllerReset:1;
2579 boolean MemoryMailboxNewCommand:1;
2580 unsigned int :3;
2581 } Write;
2582 struct {
2583 unsigned int :24;
2584 boolean HardwareMailboxFull:1;
2585 boolean InitializationInProgress:1;
2586 unsigned int :6;
2587 } Read;
2588}
2589DAC960_GEM_InboundDoorBellRegister_T;
2590
2591/*
2592 Define the structure of the DAC960 GEM Series Outbound Door Bell Register.
2593 */
2594typedef union DAC960_GEM_OutboundDoorBellRegister
2595{
2596 unsigned int All;
2597 struct {
2598 unsigned int :24;
2599 boolean AcknowledgeHardwareMailboxInterrupt:1;
2600 boolean AcknowledgeMemoryMailboxInterrupt:1;
2601 unsigned int :6;
2602 } Write;
2603 struct {
2604 unsigned int :24;
2605 boolean HardwareMailboxStatusAvailable:1;
2606 boolean MemoryMailboxStatusAvailable:1;
2607 unsigned int :6;
2608 } Read;
2609}
2610DAC960_GEM_OutboundDoorBellRegister_T;
2611
2612/*
2613 Define the structure of the DAC960 GEM Series Interrupt Mask Register.
2614 */
2615typedef union DAC960_GEM_InterruptMaskRegister
2616{
2617 unsigned int All;
2618 struct {
2619 unsigned int :16;
2620 unsigned int :8;
2621 unsigned int HardwareMailboxInterrupt:1;
2622 unsigned int MemoryMailboxInterrupt:1;
2623 unsigned int :6;
2624 } Bits;
2625}
2626DAC960_GEM_InterruptMaskRegister_T;
2627
2628/*
2629 Define the structure of the DAC960 GEM Series Error Status Register.
2630 */
2631
2632typedef union DAC960_GEM_ErrorStatusRegister
2633{
2634 unsigned int All;
2635 struct {
2636 unsigned int :24;
2637 unsigned int :5;
2638 boolean ErrorStatusPending:1;
2639 unsigned int :2;
2640 } Bits;
2641}
2642DAC960_GEM_ErrorStatusRegister_T;
2643
2644/*
2645 Define inline functions to provide an abstraction for reading and writing the
2646 DAC960 GEM Series Controller Interface Registers.
2647*/
2648
2649static inline
2650void DAC960_GEM_HardwareMailboxNewCommand(void __iomem *ControllerBaseAddress)
2651{
2652 DAC960_GEM_InboundDoorBellRegister_T InboundDoorBellRegister;
2653 InboundDoorBellRegister.All = 0;
2654 InboundDoorBellRegister.Write.HardwareMailboxNewCommand = true;
2655 writel(InboundDoorBellRegister.All,
2656 ControllerBaseAddress + DAC960_GEM_InboundDoorBellRegisterReadSetOffset);
2657}
2658
2659static inline
2660void DAC960_GEM_AcknowledgeHardwareMailboxStatus(void __iomem *ControllerBaseAddress)
2661{
2662 DAC960_GEM_InboundDoorBellRegister_T InboundDoorBellRegister;
2663 InboundDoorBellRegister.All = 0;
2664 InboundDoorBellRegister.Write.AcknowledgeHardwareMailboxStatus = true;
2665 writel(InboundDoorBellRegister.All,
2666 ControllerBaseAddress + DAC960_GEM_InboundDoorBellRegisterClearOffset);
2667}
2668
2669static inline
2670void DAC960_GEM_GenerateInterrupt(void __iomem *ControllerBaseAddress)
2671{
2672 DAC960_GEM_InboundDoorBellRegister_T InboundDoorBellRegister;
2673 InboundDoorBellRegister.All = 0;
2674 InboundDoorBellRegister.Write.GenerateInterrupt = true;
2675 writel(InboundDoorBellRegister.All,
2676 ControllerBaseAddress + DAC960_GEM_InboundDoorBellRegisterReadSetOffset);
2677}
2678
2679static inline
2680void DAC960_GEM_ControllerReset(void __iomem *ControllerBaseAddress)
2681{
2682 DAC960_GEM_InboundDoorBellRegister_T InboundDoorBellRegister;
2683 InboundDoorBellRegister.All = 0;
2684 InboundDoorBellRegister.Write.ControllerReset = true;
2685 writel(InboundDoorBellRegister.All,
2686 ControllerBaseAddress + DAC960_GEM_InboundDoorBellRegisterReadSetOffset);
2687}
2688
2689static inline
2690void DAC960_GEM_MemoryMailboxNewCommand(void __iomem *ControllerBaseAddress)
2691{
2692 DAC960_GEM_InboundDoorBellRegister_T InboundDoorBellRegister;
2693 InboundDoorBellRegister.All = 0;
2694 InboundDoorBellRegister.Write.MemoryMailboxNewCommand = true;
2695 writel(InboundDoorBellRegister.All,
2696 ControllerBaseAddress + DAC960_GEM_InboundDoorBellRegisterReadSetOffset);
2697}
2698
2699static inline
2700boolean DAC960_GEM_HardwareMailboxFullP(void __iomem *ControllerBaseAddress)
2701{
2702 DAC960_GEM_InboundDoorBellRegister_T InboundDoorBellRegister;
2703 InboundDoorBellRegister.All =
2704 readl(ControllerBaseAddress +
2705 DAC960_GEM_InboundDoorBellRegisterReadSetOffset);
2706 return InboundDoorBellRegister.Read.HardwareMailboxFull;
2707}
2708
2709static inline
2710boolean DAC960_GEM_InitializationInProgressP(void __iomem *ControllerBaseAddress)
2711{
2712 DAC960_GEM_InboundDoorBellRegister_T InboundDoorBellRegister;
2713 InboundDoorBellRegister.All =
2714 readl(ControllerBaseAddress +
2715 DAC960_GEM_InboundDoorBellRegisterReadSetOffset);
2716 return InboundDoorBellRegister.Read.InitializationInProgress;
2717}
2718
2719static inline
2720void DAC960_GEM_AcknowledgeHardwareMailboxInterrupt(void __iomem *ControllerBaseAddress)
2721{
2722 DAC960_GEM_OutboundDoorBellRegister_T OutboundDoorBellRegister;
2723 OutboundDoorBellRegister.All = 0;
2724 OutboundDoorBellRegister.Write.AcknowledgeHardwareMailboxInterrupt = true;
2725 writel(OutboundDoorBellRegister.All,
2726 ControllerBaseAddress + DAC960_GEM_OutboundDoorBellRegisterClearOffset);
2727}
2728
2729static inline
2730void DAC960_GEM_AcknowledgeMemoryMailboxInterrupt(void __iomem *ControllerBaseAddress)
2731{
2732 DAC960_GEM_OutboundDoorBellRegister_T OutboundDoorBellRegister;
2733 OutboundDoorBellRegister.All = 0;
2734 OutboundDoorBellRegister.Write.AcknowledgeMemoryMailboxInterrupt = true;
2735 writel(OutboundDoorBellRegister.All,
2736 ControllerBaseAddress + DAC960_GEM_OutboundDoorBellRegisterClearOffset);
2737}
2738
2739static inline
2740void DAC960_GEM_AcknowledgeInterrupt(void __iomem *ControllerBaseAddress)
2741{
2742 DAC960_GEM_OutboundDoorBellRegister_T OutboundDoorBellRegister;
2743 OutboundDoorBellRegister.All = 0;
2744 OutboundDoorBellRegister.Write.AcknowledgeHardwareMailboxInterrupt = true;
2745 OutboundDoorBellRegister.Write.AcknowledgeMemoryMailboxInterrupt = true;
2746 writel(OutboundDoorBellRegister.All,
2747 ControllerBaseAddress + DAC960_GEM_OutboundDoorBellRegisterClearOffset);
2748}
2749
2750static inline
2751boolean DAC960_GEM_HardwareMailboxStatusAvailableP(void __iomem *ControllerBaseAddress)
2752{
2753 DAC960_GEM_OutboundDoorBellRegister_T OutboundDoorBellRegister;
2754 OutboundDoorBellRegister.All =
2755 readl(ControllerBaseAddress +
2756 DAC960_GEM_OutboundDoorBellRegisterReadSetOffset);
2757 return OutboundDoorBellRegister.Read.HardwareMailboxStatusAvailable;
2758}
2759
2760static inline
2761boolean DAC960_GEM_MemoryMailboxStatusAvailableP(void __iomem *ControllerBaseAddress)
2762{
2763 DAC960_GEM_OutboundDoorBellRegister_T OutboundDoorBellRegister;
2764 OutboundDoorBellRegister.All =
2765 readl(ControllerBaseAddress +
2766 DAC960_GEM_OutboundDoorBellRegisterReadSetOffset);
2767 return OutboundDoorBellRegister.Read.MemoryMailboxStatusAvailable;
2768}
2769
2770static inline
2771void DAC960_GEM_EnableInterrupts(void __iomem *ControllerBaseAddress)
2772{
2773 DAC960_GEM_InterruptMaskRegister_T InterruptMaskRegister;
2774 InterruptMaskRegister.All = 0;
2775 InterruptMaskRegister.Bits.HardwareMailboxInterrupt = true;
2776 InterruptMaskRegister.Bits.MemoryMailboxInterrupt = true;
2777 writel(InterruptMaskRegister.All,
2778 ControllerBaseAddress + DAC960_GEM_InterruptMaskRegisterClearOffset);
2779}
2780
2781static inline
2782void DAC960_GEM_DisableInterrupts(void __iomem *ControllerBaseAddress)
2783{
2784 DAC960_GEM_InterruptMaskRegister_T InterruptMaskRegister;
2785 InterruptMaskRegister.All = 0;
2786 InterruptMaskRegister.Bits.HardwareMailboxInterrupt = true;
2787 InterruptMaskRegister.Bits.MemoryMailboxInterrupt = true;
2788 writel(InterruptMaskRegister.All,
2789 ControllerBaseAddress + DAC960_GEM_InterruptMaskRegisterReadSetOffset);
2790}
2791
2792static inline
2793boolean DAC960_GEM_InterruptsEnabledP(void __iomem *ControllerBaseAddress)
2794{
2795 DAC960_GEM_InterruptMaskRegister_T InterruptMaskRegister;
2796 InterruptMaskRegister.All =
2797 readl(ControllerBaseAddress +
2798 DAC960_GEM_InterruptMaskRegisterReadSetOffset);
2799 return !(InterruptMaskRegister.Bits.HardwareMailboxInterrupt ||
2800 InterruptMaskRegister.Bits.MemoryMailboxInterrupt);
2801}
2802
2803static inline
2804void DAC960_GEM_WriteCommandMailbox(DAC960_V2_CommandMailbox_T
2805 *MemoryCommandMailbox,
2806 DAC960_V2_CommandMailbox_T
2807 *CommandMailbox)
2808{
2809 memcpy(&MemoryCommandMailbox->Words[1], &CommandMailbox->Words[1],
2810 sizeof(DAC960_V2_CommandMailbox_T) - sizeof(unsigned int));
2811 wmb();
2812 MemoryCommandMailbox->Words[0] = CommandMailbox->Words[0];
2813 mb();
2814}
2815
2816static inline
2817void DAC960_GEM_WriteHardwareMailbox(void __iomem *ControllerBaseAddress,
2818 dma_addr_t CommandMailboxDMA)
2819{
2820 dma_addr_writeql(CommandMailboxDMA,
2821 ControllerBaseAddress +
2822 DAC960_GEM_CommandMailboxBusAddressOffset);
2823}
2824
2825static inline DAC960_V2_CommandIdentifier_T
2826DAC960_GEM_ReadCommandIdentifier(void __iomem *ControllerBaseAddress)
2827{
2828 return readw(ControllerBaseAddress + DAC960_GEM_CommandStatusOffset);
2829}
2830
2831static inline DAC960_V2_CommandStatus_T
2832DAC960_GEM_ReadCommandStatus(void __iomem *ControllerBaseAddress)
2833{
2834 return readw(ControllerBaseAddress + DAC960_GEM_CommandStatusOffset + 2);
2835}
2836
2837static inline boolean
2838DAC960_GEM_ReadErrorStatus(void __iomem *ControllerBaseAddress,
2839 unsigned char *ErrorStatus,
2840 unsigned char *Parameter0,
2841 unsigned char *Parameter1)
2842{
2843 DAC960_GEM_ErrorStatusRegister_T ErrorStatusRegister;
2844 ErrorStatusRegister.All =
2845 readl(ControllerBaseAddress + DAC960_GEM_ErrorStatusRegisterReadSetOffset);
2846 if (!ErrorStatusRegister.Bits.ErrorStatusPending) return false;
2847 ErrorStatusRegister.Bits.ErrorStatusPending = false;
2848 *ErrorStatus = ErrorStatusRegister.All;
2849 *Parameter0 =
2850 readb(ControllerBaseAddress + DAC960_GEM_CommandMailboxBusAddressOffset + 0);
2851 *Parameter1 =
2852 readb(ControllerBaseAddress + DAC960_GEM_CommandMailboxBusAddressOffset + 1);
2853 writel(0x03000000, ControllerBaseAddress +
2854 DAC960_GEM_ErrorStatusRegisterClearOffset);
2855 return true;
2856}
2857
2858/*
2544 Define the DAC960 BA Series Controller Interface Register Offsets. 2859 Define the DAC960 BA Series Controller Interface Register Offsets.
2545*/ 2860*/
2546 2861
diff --git a/drivers/block/Kconfig b/drivers/block/Kconfig
index e830be1a3ae6..b594768b0241 100644
--- a/drivers/block/Kconfig
+++ b/drivers/block/Kconfig
@@ -6,7 +6,7 @@ menu "Block devices"
6 6
7config BLK_DEV_FD 7config BLK_DEV_FD
8 tristate "Normal floppy disk support" 8 tristate "Normal floppy disk support"
9 depends on (!ARCH_S390 && !M68K && !IA64 && !UML) || Q40 || (SUN3X && BROKEN) || ARCH_RPC || ARCH_EBSA285 9 depends on (!ARCH_S390 && !M68K && !IA64 && !UML && !ARM) || Q40 || (SUN3X && BROKEN) || ARCH_RPC || ARCH_EBSA285
10 ---help--- 10 ---help---
11 If you want to use the floppy disk drive(s) of your PC under Linux, 11 If you want to use the floppy disk drive(s) of your PC under Linux,
12 say Y. Information about this driver, especially important for IBM 12 say Y. Information about this driver, especially important for IBM
@@ -105,7 +105,7 @@ config ATARI_SLM
105 105
106config BLK_DEV_XD 106config BLK_DEV_XD
107 tristate "XT hard disk support" 107 tristate "XT hard disk support"
108 depends on ISA 108 depends on ISA && ISA_DMA_API
109 help 109 help
110 Very old 8 bit hard disk controllers used in the IBM XT computer 110 Very old 8 bit hard disk controllers used in the IBM XT computer
111 will be supported if you say Y here. 111 will be supported if you say Y here.
diff --git a/drivers/block/aoe/aoe.h b/drivers/block/aoe/aoe.h
index aa8b547ffafa..721ba8086043 100644
--- a/drivers/block/aoe/aoe.h
+++ b/drivers/block/aoe/aoe.h
@@ -1,5 +1,5 @@
1/* Copyright (c) 2004 Coraid, Inc. See COPYING for GPL terms. */ 1/* Copyright (c) 2004 Coraid, Inc. See COPYING for GPL terms. */
2#define VERSION "6" 2#define VERSION "10"
3#define AOE_MAJOR 152 3#define AOE_MAJOR 152
4#define DEVICE_NAME "aoe" 4#define DEVICE_NAME "aoe"
5 5
diff --git a/drivers/block/aoe/aoeblk.c b/drivers/block/aoe/aoeblk.c
index 4780f7926d42..0e97fcb9f3a1 100644
--- a/drivers/block/aoe/aoeblk.c
+++ b/drivers/block/aoe/aoeblk.c
@@ -37,6 +37,13 @@ static ssize_t aoedisk_show_netif(struct gendisk * disk, char *page)
37 37
38 return snprintf(page, PAGE_SIZE, "%s\n", d->ifp->name); 38 return snprintf(page, PAGE_SIZE, "%s\n", d->ifp->name);
39} 39}
40/* firmware version */
41static ssize_t aoedisk_show_fwver(struct gendisk * disk, char *page)
42{
43 struct aoedev *d = disk->private_data;
44
45 return snprintf(page, PAGE_SIZE, "0x%04x\n", (unsigned int) d->fw_ver);
46}
40 47
41static struct disk_attribute disk_attr_state = { 48static struct disk_attribute disk_attr_state = {
42 .attr = {.name = "state", .mode = S_IRUGO }, 49 .attr = {.name = "state", .mode = S_IRUGO },
@@ -50,6 +57,10 @@ static struct disk_attribute disk_attr_netif = {
50 .attr = {.name = "netif", .mode = S_IRUGO }, 57 .attr = {.name = "netif", .mode = S_IRUGO },
51 .show = aoedisk_show_netif 58 .show = aoedisk_show_netif
52}; 59};
60static struct disk_attribute disk_attr_fwver = {
61 .attr = {.name = "firmware-version", .mode = S_IRUGO },
62 .show = aoedisk_show_fwver
63};
53 64
54static void 65static void
55aoedisk_add_sysfs(struct aoedev *d) 66aoedisk_add_sysfs(struct aoedev *d)
@@ -57,6 +68,7 @@ aoedisk_add_sysfs(struct aoedev *d)
57 sysfs_create_file(&d->gd->kobj, &disk_attr_state.attr); 68 sysfs_create_file(&d->gd->kobj, &disk_attr_state.attr);
58 sysfs_create_file(&d->gd->kobj, &disk_attr_mac.attr); 69 sysfs_create_file(&d->gd->kobj, &disk_attr_mac.attr);
59 sysfs_create_file(&d->gd->kobj, &disk_attr_netif.attr); 70 sysfs_create_file(&d->gd->kobj, &disk_attr_netif.attr);
71 sysfs_create_file(&d->gd->kobj, &disk_attr_fwver.attr);
60} 72}
61void 73void
62aoedisk_rm_sysfs(struct aoedev *d) 74aoedisk_rm_sysfs(struct aoedev *d)
@@ -64,6 +76,7 @@ aoedisk_rm_sysfs(struct aoedev *d)
64 sysfs_remove_link(&d->gd->kobj, "state"); 76 sysfs_remove_link(&d->gd->kobj, "state");
65 sysfs_remove_link(&d->gd->kobj, "mac"); 77 sysfs_remove_link(&d->gd->kobj, "mac");
66 sysfs_remove_link(&d->gd->kobj, "netif"); 78 sysfs_remove_link(&d->gd->kobj, "netif");
79 sysfs_remove_link(&d->gd->kobj, "firmware-version");
67} 80}
68 81
69static int 82static int
diff --git a/drivers/block/aoe/aoedev.c b/drivers/block/aoe/aoedev.c
index ec16c64dd114..6e231c5a1199 100644
--- a/drivers/block/aoe/aoedev.c
+++ b/drivers/block/aoe/aoedev.c
@@ -109,25 +109,22 @@ aoedev_set(ulong sysminor, unsigned char *addr, struct net_device *ifp, ulong bu
109 spin_lock_irqsave(&devlist_lock, flags); 109 spin_lock_irqsave(&devlist_lock, flags);
110 110
111 for (d=devlist; d; d=d->next) 111 for (d=devlist; d; d=d->next)
112 if (d->sysminor == sysminor 112 if (d->sysminor == sysminor)
113 || memcmp(d->addr, addr, sizeof d->addr) == 0)
114 break; 113 break;
115 114
116 if (d == NULL && (d = aoedev_newdev(bufcnt)) == NULL) { 115 if (d == NULL && (d = aoedev_newdev(bufcnt)) == NULL) {
117 spin_unlock_irqrestore(&devlist_lock, flags); 116 spin_unlock_irqrestore(&devlist_lock, flags);
118 printk(KERN_INFO "aoe: aoedev_set: aoedev_newdev failure.\n"); 117 printk(KERN_INFO "aoe: aoedev_set: aoedev_newdev failure.\n");
119 return NULL; 118 return NULL;
120 } 119 } /* if newdev, (d->flags & DEVFL_UP) == 0 for below */
121 120
122 spin_unlock_irqrestore(&devlist_lock, flags); 121 spin_unlock_irqrestore(&devlist_lock, flags);
123 spin_lock_irqsave(&d->lock, flags); 122 spin_lock_irqsave(&d->lock, flags);
124 123
125 d->ifp = ifp; 124 d->ifp = ifp;
126 125 memcpy(d->addr, addr, sizeof d->addr);
127 if (d->sysminor != sysminor 126 if ((d->flags & DEVFL_UP) == 0) {
128 || (d->flags & DEVFL_UP) == 0) {
129 aoedev_downdev(d); /* flushes outstanding frames */ 127 aoedev_downdev(d); /* flushes outstanding frames */
130 memcpy(d->addr, addr, sizeof d->addr);
131 d->sysminor = sysminor; 128 d->sysminor = sysminor;
132 d->aoemajor = AOEMAJOR(sysminor); 129 d->aoemajor = AOEMAJOR(sysminor);
133 d->aoeminor = AOEMINOR(sysminor); 130 d->aoeminor = AOEMINOR(sysminor);
diff --git a/drivers/block/aoe/aoenet.c b/drivers/block/aoe/aoenet.c
index bc92aacb6dad..9e6f51c528b0 100644
--- a/drivers/block/aoe/aoenet.c
+++ b/drivers/block/aoe/aoenet.c
@@ -7,6 +7,7 @@
7#include <linux/hdreg.h> 7#include <linux/hdreg.h>
8#include <linux/blkdev.h> 8#include <linux/blkdev.h>
9#include <linux/netdevice.h> 9#include <linux/netdevice.h>
10#include <linux/moduleparam.h>
10#include "aoe.h" 11#include "aoe.h"
11 12
12#define NECODES 5 13#define NECODES 5
@@ -26,6 +27,19 @@ enum {
26}; 27};
27 28
28static char aoe_iflist[IFLISTSZ]; 29static char aoe_iflist[IFLISTSZ];
30module_param_string(aoe_iflist, aoe_iflist, IFLISTSZ, 0600);
31MODULE_PARM_DESC(aoe_iflist, "aoe_iflist=\"dev1 [dev2 ...]\"\n");
32
33#ifndef MODULE
34static int __init aoe_iflist_setup(char *str)
35{
36 strncpy(aoe_iflist, str, IFLISTSZ);
37 aoe_iflist[IFLISTSZ - 1] = '\0';
38 return 1;
39}
40
41__setup("aoe_iflist=", aoe_iflist_setup);
42#endif
29 43
30int 44int
31is_aoe_netif(struct net_device *ifp) 45is_aoe_netif(struct net_device *ifp)
@@ -36,7 +50,8 @@ is_aoe_netif(struct net_device *ifp)
36 if (aoe_iflist[0] == '\0') 50 if (aoe_iflist[0] == '\0')
37 return 1; 51 return 1;
38 52
39 for (p = aoe_iflist; *p; p = q + strspn(q, WHITESPACE)) { 53 p = aoe_iflist + strspn(aoe_iflist, WHITESPACE);
54 for (; *p; p = q + strspn(q, WHITESPACE)) {
40 q = p + strcspn(p, WHITESPACE); 55 q = p + strcspn(p, WHITESPACE);
41 if (q != p) 56 if (q != p)
42 len = q - p; 57 len = q - p;
diff --git a/drivers/block/floppy.c b/drivers/block/floppy.c
index 42dfa281a880..f0c1084b840f 100644
--- a/drivers/block/floppy.c
+++ b/drivers/block/floppy.c
@@ -3345,7 +3345,7 @@ static inline int set_geometry(unsigned int cmd, struct floppy_struct *g,
3345 struct block_device *bdev = opened_bdev[cnt]; 3345 struct block_device *bdev = opened_bdev[cnt];
3346 if (!bdev || ITYPE(drive_state[cnt].fd_device) != type) 3346 if (!bdev || ITYPE(drive_state[cnt].fd_device) != type)
3347 continue; 3347 continue;
3348 __invalidate_device(bdev, 0); 3348 __invalidate_device(bdev);
3349 } 3349 }
3350 up(&open_lock); 3350 up(&open_lock);
3351 } else { 3351 } else {
diff --git a/drivers/block/genhd.c b/drivers/block/genhd.c
index ab4db71375e0..8bbe01d4b487 100644
--- a/drivers/block/genhd.c
+++ b/drivers/block/genhd.c
@@ -14,6 +14,7 @@
14#include <linux/slab.h> 14#include <linux/slab.h>
15#include <linux/kmod.h> 15#include <linux/kmod.h>
16#include <linux/kobj_map.h> 16#include <linux/kobj_map.h>
17#include <linux/buffer_head.h>
17 18
18#define MAX_PROBE_HASH 255 /* random */ 19#define MAX_PROBE_HASH 255 /* random */
19 20
@@ -676,7 +677,8 @@ int invalidate_partition(struct gendisk *disk, int index)
676 int res = 0; 677 int res = 0;
677 struct block_device *bdev = bdget_disk(disk, index); 678 struct block_device *bdev = bdget_disk(disk, index);
678 if (bdev) { 679 if (bdev) {
679 res = __invalidate_device(bdev, 1); 680 fsync_bdev(bdev);
681 res = __invalidate_device(bdev);
680 bdput(bdev); 682 bdput(bdev);
681 } 683 }
682 return res; 684 return res;
diff --git a/drivers/block/nbd.c b/drivers/block/nbd.c
index efdf04450bf7..9e268ddedfbd 100644
--- a/drivers/block/nbd.c
+++ b/drivers/block/nbd.c
@@ -78,6 +78,7 @@
78#define DBG_RX 0x0200 78#define DBG_RX 0x0200
79#define DBG_TX 0x0400 79#define DBG_TX 0x0400
80static unsigned int debugflags; 80static unsigned int debugflags;
81static unsigned int nbds_max = 16;
81#endif /* NDEBUG */ 82#endif /* NDEBUG */
82 83
83static struct nbd_device nbd_dev[MAX_NBD]; 84static struct nbd_device nbd_dev[MAX_NBD];
@@ -647,7 +648,13 @@ static int __init nbd_init(void)
647 return -EIO; 648 return -EIO;
648 } 649 }
649 650
650 for (i = 0; i < MAX_NBD; i++) { 651 if (nbds_max > MAX_NBD) {
652 printk(KERN_CRIT "nbd: cannot allocate more than %u nbds; %u requested.\n", MAX_NBD,
653 nbds_max);
654 return -EINVAL;
655 }
656
657 for (i = 0; i < nbds_max; i++) {
651 struct gendisk *disk = alloc_disk(1); 658 struct gendisk *disk = alloc_disk(1);
652 if (!disk) 659 if (!disk)
653 goto out; 660 goto out;
@@ -673,7 +680,7 @@ static int __init nbd_init(void)
673 dprintk(DBG_INIT, "nbd: debugflags=0x%x\n", debugflags); 680 dprintk(DBG_INIT, "nbd: debugflags=0x%x\n", debugflags);
674 681
675 devfs_mk_dir("nbd"); 682 devfs_mk_dir("nbd");
676 for (i = 0; i < MAX_NBD; i++) { 683 for (i = 0; i < nbds_max; i++) {
677 struct gendisk *disk = nbd_dev[i].disk; 684 struct gendisk *disk = nbd_dev[i].disk;
678 nbd_dev[i].file = NULL; 685 nbd_dev[i].file = NULL;
679 nbd_dev[i].magic = LO_MAGIC; 686 nbd_dev[i].magic = LO_MAGIC;
@@ -706,8 +713,9 @@ out:
706static void __exit nbd_cleanup(void) 713static void __exit nbd_cleanup(void)
707{ 714{
708 int i; 715 int i;
709 for (i = 0; i < MAX_NBD; i++) { 716 for (i = 0; i < nbds_max; i++) {
710 struct gendisk *disk = nbd_dev[i].disk; 717 struct gendisk *disk = nbd_dev[i].disk;
718 nbd_dev[i].magic = 0;
711 if (disk) { 719 if (disk) {
712 del_gendisk(disk); 720 del_gendisk(disk);
713 blk_cleanup_queue(disk->queue); 721 blk_cleanup_queue(disk->queue);
@@ -725,6 +733,8 @@ module_exit(nbd_cleanup);
725MODULE_DESCRIPTION("Network Block Device"); 733MODULE_DESCRIPTION("Network Block Device");
726MODULE_LICENSE("GPL"); 734MODULE_LICENSE("GPL");
727 735
736module_param(nbds_max, int, 0444);
737MODULE_PARM_DESC(nbds_max, "How many network block devices to initialize.");
728#ifndef NDEBUG 738#ifndef NDEBUG
729module_param(debugflags, int, 0644); 739module_param(debugflags, int, 0644);
730MODULE_PARM_DESC(debugflags, "flags for controlling debug output"); 740MODULE_PARM_DESC(debugflags, "flags for controlling debug output");
diff --git a/drivers/block/noop-iosched.c b/drivers/block/noop-iosched.c
index 888c477e02b3..b1730b62c37e 100644
--- a/drivers/block/noop-iosched.c
+++ b/drivers/block/noop-iosched.c
@@ -13,34 +13,13 @@
13static int elevator_noop_merge(request_queue_t *q, struct request **req, 13static int elevator_noop_merge(request_queue_t *q, struct request **req,
14 struct bio *bio) 14 struct bio *bio)
15{ 15{
16 struct list_head *entry = &q->queue_head;
17 struct request *__rq;
18 int ret; 16 int ret;
19 17
20 if ((ret = elv_try_last_merge(q, bio))) { 18 ret = elv_try_last_merge(q, bio);
19 if (ret != ELEVATOR_NO_MERGE)
21 *req = q->last_merge; 20 *req = q->last_merge;
22 return ret;
23 }
24 21
25 while ((entry = entry->prev) != &q->queue_head) { 22 return ret;
26 __rq = list_entry_rq(entry);
27
28 if (__rq->flags & (REQ_SOFTBARRIER | REQ_HARDBARRIER))
29 break;
30 else if (__rq->flags & REQ_STARTED)
31 break;
32
33 if (!blk_fs_request(__rq))
34 continue;
35
36 if ((ret = elv_try_merge(__rq, bio))) {
37 *req = __rq;
38 q->last_merge = __rq;
39 return ret;
40 }
41 }
42
43 return ELEVATOR_NO_MERGE;
44} 23}
45 24
46static void elevator_noop_merge_requests(request_queue_t *q, struct request *req, 25static void elevator_noop_merge_requests(request_queue_t *q, struct request *req,