aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/block/cciss.h
diff options
context:
space:
mode:
authorStephen M. Cameron <scameron@beardog.cce.hp.com>2011-05-03 15:52:54 -0400
committerJens Axboe <jaxboe@fusionio.com>2011-05-06 10:23:45 -0400
commit9bd3c20487b7c13d397dc11dd51e30256bf4c9b3 (patch)
tree5fc22ec358e15644c5a86970c6366aea9cc7f693 /drivers/block/cciss.h
parent490b94be0282c3b67f56453628ff0aaae827a670 (diff)
cciss: add readl after writel in interrupt mask setting code
This is to ensure the board interrupts are really off when these functions return. Signed-off-by: Stephen M. Cameron <scameron@beardog.cce.hp.com> Signed-off-by: Jens Axboe <jaxboe@fusionio.com>
Diffstat (limited to 'drivers/block/cciss.h')
-rw-r--r--drivers/block/cciss.h6
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/block/cciss.h b/drivers/block/cciss.h
index 554bbd907d14..9b494392e5d5 100644
--- a/drivers/block/cciss.h
+++ b/drivers/block/cciss.h
@@ -239,11 +239,13 @@ static void SA5_intr_mask(ctlr_info_t *h, unsigned long val)
239 { /* Turn interrupts on */ 239 { /* Turn interrupts on */
240 h->interrupts_enabled = 1; 240 h->interrupts_enabled = 1;
241 writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); 241 writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
242 (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
242 } else /* Turn them off */ 243 } else /* Turn them off */
243 { 244 {
244 h->interrupts_enabled = 0; 245 h->interrupts_enabled = 0;
245 writel( SA5_INTR_OFF, 246 writel( SA5_INTR_OFF,
246 h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); 247 h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
248 (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
247 } 249 }
248} 250}
249/* 251/*
@@ -257,11 +259,13 @@ static void SA5B_intr_mask(ctlr_info_t *h, unsigned long val)
257 { /* Turn interrupts on */ 259 { /* Turn interrupts on */
258 h->interrupts_enabled = 1; 260 h->interrupts_enabled = 1;
259 writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); 261 writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
262 (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
260 } else /* Turn them off */ 263 } else /* Turn them off */
261 { 264 {
262 h->interrupts_enabled = 0; 265 h->interrupts_enabled = 0;
263 writel( SA5B_INTR_OFF, 266 writel( SA5B_INTR_OFF,
264 h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); 267 h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
268 (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
265 } 269 }
266} 270}
267 271
@@ -271,10 +275,12 @@ static void SA5_performant_intr_mask(ctlr_info_t *h, unsigned long val)
271 if (val) { /* turn on interrupts */ 275 if (val) { /* turn on interrupts */
272 h->interrupts_enabled = 1; 276 h->interrupts_enabled = 1;
273 writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); 277 writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
278 (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
274 } else { 279 } else {
275 h->interrupts_enabled = 0; 280 h->interrupts_enabled = 0;
276 writel(SA5_PERF_INTR_OFF, 281 writel(SA5_PERF_INTR_OFF,
277 h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); 282 h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
283 (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
278 } 284 }
279} 285}
280 286