aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/block/DAC960.h
diff options
context:
space:
mode:
authorRichard Knutsson <ricknu-0@student.ltu.se>2007-02-10 04:46:31 -0500
committerLinus Torvalds <torvalds@woody.linux-foundation.org>2007-02-11 14:18:06 -0500
commit87d156bfd50ac6e66db981989948b7311a25b6ae (patch)
treee7ce7821abc8b4f6bad7594468e901b22cb0588d /drivers/block/DAC960.h
parent2b1cd4c43b90059b54baa8d9113365984113c631 (diff)
[PATCH] drivers/block/DAC960: convert 'boolean' to 'bool'
Converts 'boolean' to 'bool' and removes the 'boolean' typedef. Signed-off-by: Richard Knutsson <ricknu-0@student.ltu.se> Cc: Jens Axboe <axboe@suse.de> Cc: James Bottomley <James.Bottomley@steeleye.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Diffstat (limited to 'drivers/block/DAC960.h')
-rw-r--r--drivers/block/DAC960.h495
1 files changed, 244 insertions, 251 deletions
diff --git a/drivers/block/DAC960.h b/drivers/block/DAC960.h
index 6148073532b2..f5e2436c39aa 100644
--- a/drivers/block/DAC960.h
+++ b/drivers/block/DAC960.h
@@ -68,13 +68,6 @@
68#define DAC690_V2_PciDmaMask 0xffffffffffffffffULL 68#define DAC690_V2_PciDmaMask 0xffffffffffffffffULL
69 69
70/* 70/*
71 Define a Boolean data type.
72*/
73
74typedef bool boolean;
75
76
77/*
78 Define a 32/64 bit I/O Address data type. 71 Define a 32/64 bit I/O Address data type.
79*/ 72*/
80 73
@@ -139,25 +132,25 @@ typedef struct DAC960_SCSI_Inquiry
139 unsigned char PeripheralDeviceType:5; /* Byte 0 Bits 0-4 */ 132 unsigned char PeripheralDeviceType:5; /* Byte 0 Bits 0-4 */
140 unsigned char PeripheralQualifier:3; /* Byte 0 Bits 5-7 */ 133 unsigned char PeripheralQualifier:3; /* Byte 0 Bits 5-7 */
141 unsigned char DeviceTypeModifier:7; /* Byte 1 Bits 0-6 */ 134 unsigned char DeviceTypeModifier:7; /* Byte 1 Bits 0-6 */
142 boolean RMB:1; /* Byte 1 Bit 7 */ 135 bool RMB:1; /* Byte 1 Bit 7 */
143 unsigned char ANSI_ApprovedVersion:3; /* Byte 2 Bits 0-2 */ 136 unsigned char ANSI_ApprovedVersion:3; /* Byte 2 Bits 0-2 */
144 unsigned char ECMA_Version:3; /* Byte 2 Bits 3-5 */ 137 unsigned char ECMA_Version:3; /* Byte 2 Bits 3-5 */
145 unsigned char ISO_Version:2; /* Byte 2 Bits 6-7 */ 138 unsigned char ISO_Version:2; /* Byte 2 Bits 6-7 */
146 unsigned char ResponseDataFormat:4; /* Byte 3 Bits 0-3 */ 139 unsigned char ResponseDataFormat:4; /* Byte 3 Bits 0-3 */
147 unsigned char :2; /* Byte 3 Bits 4-5 */ 140 unsigned char :2; /* Byte 3 Bits 4-5 */
148 boolean TrmIOP:1; /* Byte 3 Bit 6 */ 141 bool TrmIOP:1; /* Byte 3 Bit 6 */
149 boolean AENC:1; /* Byte 3 Bit 7 */ 142 bool AENC:1; /* Byte 3 Bit 7 */
150 unsigned char AdditionalLength; /* Byte 4 */ 143 unsigned char AdditionalLength; /* Byte 4 */
151 unsigned char :8; /* Byte 5 */ 144 unsigned char :8; /* Byte 5 */
152 unsigned char :8; /* Byte 6 */ 145 unsigned char :8; /* Byte 6 */
153 boolean SftRe:1; /* Byte 7 Bit 0 */ 146 bool SftRe:1; /* Byte 7 Bit 0 */
154 boolean CmdQue:1; /* Byte 7 Bit 1 */ 147 bool CmdQue:1; /* Byte 7 Bit 1 */
155 boolean :1; /* Byte 7 Bit 2 */ 148 bool :1; /* Byte 7 Bit 2 */
156 boolean Linked:1; /* Byte 7 Bit 3 */ 149 bool Linked:1; /* Byte 7 Bit 3 */
157 boolean Sync:1; /* Byte 7 Bit 4 */ 150 bool Sync:1; /* Byte 7 Bit 4 */
158 boolean WBus16:1; /* Byte 7 Bit 5 */ 151 bool WBus16:1; /* Byte 7 Bit 5 */
159 boolean WBus32:1; /* Byte 7 Bit 6 */ 152 bool WBus32:1; /* Byte 7 Bit 6 */
160 boolean RelAdr:1; /* Byte 7 Bit 7 */ 153 bool RelAdr:1; /* Byte 7 Bit 7 */
161 unsigned char VendorIdentification[8]; /* Bytes 8-15 */ 154 unsigned char VendorIdentification[8]; /* Bytes 8-15 */
162 unsigned char ProductIdentification[16]; /* Bytes 16-31 */ 155 unsigned char ProductIdentification[16]; /* Bytes 16-31 */
163 unsigned char ProductRevisionLevel[4]; /* Bytes 32-35 */ 156 unsigned char ProductRevisionLevel[4]; /* Bytes 32-35 */
@@ -215,13 +208,13 @@ DAC960_SCSI_RequestSenseKey_T;
215typedef struct DAC960_SCSI_RequestSense 208typedef struct DAC960_SCSI_RequestSense
216{ 209{
217 unsigned char ErrorCode:7; /* Byte 0 Bits 0-6 */ 210 unsigned char ErrorCode:7; /* Byte 0 Bits 0-6 */
218 boolean Valid:1; /* Byte 0 Bit 7 */ 211 bool Valid:1; /* Byte 0 Bit 7 */
219 unsigned char SegmentNumber; /* Byte 1 */ 212 unsigned char SegmentNumber; /* Byte 1 */
220 DAC960_SCSI_RequestSenseKey_T SenseKey:4; /* Byte 2 Bits 0-3 */ 213 DAC960_SCSI_RequestSenseKey_T SenseKey:4; /* Byte 2 Bits 0-3 */
221 unsigned char :1; /* Byte 2 Bit 4 */ 214 unsigned char :1; /* Byte 2 Bit 4 */
222 boolean ILI:1; /* Byte 2 Bit 5 */ 215 bool ILI:1; /* Byte 2 Bit 5 */
223 boolean EOM:1; /* Byte 2 Bit 6 */ 216 bool EOM:1; /* Byte 2 Bit 6 */
224 boolean Filemark:1; /* Byte 2 Bit 7 */ 217 bool Filemark:1; /* Byte 2 Bit 7 */
225 unsigned char Information[4]; /* Bytes 3-6 */ 218 unsigned char Information[4]; /* Bytes 3-6 */
226 unsigned char AdditionalSenseLength; /* Byte 7 */ 219 unsigned char AdditionalSenseLength; /* Byte 7 */
227 unsigned char CommandSpecificInformation[4]; /* Bytes 8-11 */ 220 unsigned char CommandSpecificInformation[4]; /* Bytes 8-11 */
@@ -381,8 +374,8 @@ typedef struct DAC960_V1_Enquiry
381 unsigned int LogicalDriveSizes[32]; /* Bytes 4-131 */ 374 unsigned int LogicalDriveSizes[32]; /* Bytes 4-131 */
382 unsigned short FlashAge; /* Bytes 132-133 */ 375 unsigned short FlashAge; /* Bytes 132-133 */
383 struct { 376 struct {
384 boolean DeferredWriteError:1; /* Byte 134 Bit 0 */ 377 bool DeferredWriteError:1; /* Byte 134 Bit 0 */
385 boolean BatteryLow:1; /* Byte 134 Bit 1 */ 378 bool BatteryLow:1; /* Byte 134 Bit 1 */
386 unsigned char :6; /* Byte 134 Bits 2-7 */ 379 unsigned char :6; /* Byte 134 Bits 2-7 */
387 } StatusFlags; 380 } StatusFlags;
388 unsigned char :8; /* Byte 135 */ 381 unsigned char :8; /* Byte 135 */
@@ -410,7 +403,7 @@ typedef struct DAC960_V1_Enquiry
410 unsigned char RebuildCount; /* Byte 150 */ 403 unsigned char RebuildCount; /* Byte 150 */
411 struct { 404 struct {
412 unsigned char :3; /* Byte 151 Bits 0-2 */ 405 unsigned char :3; /* Byte 151 Bits 0-2 */
413 boolean BatteryBackupUnitPresent:1; /* Byte 151 Bit 3 */ 406 bool BatteryBackupUnitPresent:1; /* Byte 151 Bit 3 */
414 unsigned char :3; /* Byte 151 Bits 4-6 */ 407 unsigned char :3; /* Byte 151 Bits 4-6 */
415 unsigned char :1; /* Byte 151 Bit 7 */ 408 unsigned char :1; /* Byte 151 Bit 7 */
416 } MiscFlags; 409 } MiscFlags;
@@ -492,8 +485,8 @@ typedef struct DAC960_V1_Enquiry2
492 DAC960_V1_ErrorCorrection_ECC = 0x2, 485 DAC960_V1_ErrorCorrection_ECC = 0x2,
493 DAC960_V1_ErrorCorrection_Last = 0x7 486 DAC960_V1_ErrorCorrection_Last = 0x7
494 } __attribute__ ((packed)) ErrorCorrection:3; /* Byte 40 Bits 3-5 */ 487 } __attribute__ ((packed)) ErrorCorrection:3; /* Byte 40 Bits 3-5 */
495 boolean FastPageMode:1; /* Byte 40 Bit 6 */ 488 bool FastPageMode:1; /* Byte 40 Bit 6 */
496 boolean LowPowerMemory:1; /* Byte 40 Bit 7 */ 489 bool LowPowerMemory:1; /* Byte 40 Bit 7 */
497 unsigned char :8; /* Bytes 41 */ 490 unsigned char :8; /* Bytes 41 */
498 } MemoryType; 491 } MemoryType;
499 unsigned short ClockSpeed; /* Bytes 42-43 */ 492 unsigned short ClockSpeed; /* Bytes 42-43 */
@@ -538,7 +531,7 @@ typedef struct DAC960_V1_Enquiry2
538 DAC960_V1_Ultra = 0x1, 531 DAC960_V1_Ultra = 0x1,
539 DAC960_V1_Ultra2 = 0x2 532 DAC960_V1_Ultra2 = 0x2
540 } __attribute__ ((packed)) BusSpeed:2; /* Byte 106 Bits 2-3 */ 533 } __attribute__ ((packed)) BusSpeed:2; /* Byte 106 Bits 2-3 */
541 boolean Differential:1; /* Byte 106 Bit 4 */ 534 bool Differential:1; /* Byte 106 Bit 4 */
542 unsigned char :3; /* Byte 106 Bits 5-7 */ 535 unsigned char :3; /* Byte 106 Bits 5-7 */
543 } SCSICapability; 536 } SCSICapability;
544 unsigned char :8; /* Byte 107 */ 537 unsigned char :8; /* Byte 107 */
@@ -554,10 +547,10 @@ typedef struct DAC960_V1_Enquiry2
554 } __attribute__ ((packed)) FaultManagementType; /* Byte 114 */ 547 } __attribute__ ((packed)) FaultManagementType; /* Byte 114 */
555 unsigned char :8; /* Byte 115 */ 548 unsigned char :8; /* Byte 115 */
556 struct { 549 struct {
557 boolean Clustering:1; /* Byte 116 Bit 0 */ 550 bool Clustering:1; /* Byte 116 Bit 0 */
558 boolean MylexOnlineRAIDExpansion:1; /* Byte 116 Bit 1 */ 551 bool MylexOnlineRAIDExpansion:1; /* Byte 116 Bit 1 */
559 boolean ReadAhead:1; /* Byte 116 Bit 2 */ 552 bool ReadAhead:1; /* Byte 116 Bit 2 */
560 boolean BackgroundInitialization:1; /* Byte 116 Bit 3 */ 553 bool BackgroundInitialization:1; /* Byte 116 Bit 3 */
561 unsigned int :28; /* Bytes 116-119 */ 554 unsigned int :28; /* Bytes 116-119 */
562 } FirmwareFeatures; 555 } FirmwareFeatures;
563 unsigned int :32; /* Bytes 120-123 */ 556 unsigned int :32; /* Bytes 120-123 */
@@ -589,7 +582,7 @@ typedef struct DAC960_V1_LogicalDriveInformation
589 unsigned int LogicalDriveSize; /* Bytes 0-3 */ 582 unsigned int LogicalDriveSize; /* Bytes 0-3 */
590 DAC960_V1_LogicalDriveState_T LogicalDriveState; /* Byte 4 */ 583 DAC960_V1_LogicalDriveState_T LogicalDriveState; /* Byte 4 */
591 unsigned char RAIDLevel:7; /* Byte 5 Bits 0-6 */ 584 unsigned char RAIDLevel:7; /* Byte 5 Bits 0-6 */
592 boolean WriteBack:1; /* Byte 5 Bit 7 */ 585 bool WriteBack:1; /* Byte 5 Bit 7 */
593 unsigned short :16; /* Bytes 6-7 */ 586 unsigned short :16; /* Bytes 6-7 */
594} 587}
595DAC960_V1_LogicalDriveInformation_T; 588DAC960_V1_LogicalDriveInformation_T;
@@ -630,13 +623,13 @@ typedef struct DAC960_V1_EventLogEntry
630 unsigned char :2; /* Byte 3 Bits 6-7 */ 623 unsigned char :2; /* Byte 3 Bits 6-7 */
631 unsigned short SequenceNumber; /* Bytes 4-5 */ 624 unsigned short SequenceNumber; /* Bytes 4-5 */
632 unsigned char ErrorCode:7; /* Byte 6 Bits 0-6 */ 625 unsigned char ErrorCode:7; /* Byte 6 Bits 0-6 */
633 boolean Valid:1; /* Byte 6 Bit 7 */ 626 bool Valid:1; /* Byte 6 Bit 7 */
634 unsigned char SegmentNumber; /* Byte 7 */ 627 unsigned char SegmentNumber; /* Byte 7 */
635 DAC960_SCSI_RequestSenseKey_T SenseKey:4; /* Byte 8 Bits 0-3 */ 628 DAC960_SCSI_RequestSenseKey_T SenseKey:4; /* Byte 8 Bits 0-3 */
636 unsigned char :1; /* Byte 8 Bit 4 */ 629 unsigned char :1; /* Byte 8 Bit 4 */
637 boolean ILI:1; /* Byte 8 Bit 5 */ 630 bool ILI:1; /* Byte 8 Bit 5 */
638 boolean EOM:1; /* Byte 8 Bit 6 */ 631 bool EOM:1; /* Byte 8 Bit 6 */
639 boolean Filemark:1; /* Byte 8 Bit 7 */ 632 bool Filemark:1; /* Byte 8 Bit 7 */
640 unsigned char Information[4]; /* Bytes 9-12 */ 633 unsigned char Information[4]; /* Bytes 9-12 */
641 unsigned char AdditionalSenseLength; /* Byte 13 */ 634 unsigned char AdditionalSenseLength; /* Byte 13 */
642 unsigned char CommandSpecificInformation[4]; /* Bytes 14-17 */ 635 unsigned char CommandSpecificInformation[4]; /* Bytes 14-17 */
@@ -670,7 +663,7 @@ DAC960_V1_PhysicalDeviceState_T;
670 663
671typedef struct DAC960_V1_DeviceState 664typedef struct DAC960_V1_DeviceState
672{ 665{
673 boolean Present:1; /* Byte 0 Bit 0 */ 666 bool Present:1; /* Byte 0 Bit 0 */
674 unsigned char :7; /* Byte 0 Bits 1-7 */ 667 unsigned char :7; /* Byte 0 Bits 1-7 */
675 enum { 668 enum {
676 DAC960_V1_OtherType = 0x0, 669 DAC960_V1_OtherType = 0x0,
@@ -678,12 +671,12 @@ typedef struct DAC960_V1_DeviceState
678 DAC960_V1_SequentialType = 0x2, 671 DAC960_V1_SequentialType = 0x2,
679 DAC960_V1_CDROM_or_WORM_Type = 0x3 672 DAC960_V1_CDROM_or_WORM_Type = 0x3
680 } __attribute__ ((packed)) DeviceType:2; /* Byte 1 Bits 0-1 */ 673 } __attribute__ ((packed)) DeviceType:2; /* Byte 1 Bits 0-1 */
681 boolean :1; /* Byte 1 Bit 2 */ 674 bool :1; /* Byte 1 Bit 2 */
682 boolean Fast20:1; /* Byte 1 Bit 3 */ 675 bool Fast20:1; /* Byte 1 Bit 3 */
683 boolean Sync:1; /* Byte 1 Bit 4 */ 676 bool Sync:1; /* Byte 1 Bit 4 */
684 boolean Fast:1; /* Byte 1 Bit 5 */ 677 bool Fast:1; /* Byte 1 Bit 5 */
685 boolean Wide:1; /* Byte 1 Bit 6 */ 678 bool Wide:1; /* Byte 1 Bit 6 */
686 boolean TaggedQueuingSupported:1; /* Byte 1 Bit 7 */ 679 bool TaggedQueuingSupported:1; /* Byte 1 Bit 7 */
687 DAC960_V1_PhysicalDeviceState_T DeviceState; /* Byte 2 */ 680 DAC960_V1_PhysicalDeviceState_T DeviceState; /* Byte 2 */
688 unsigned char :8; /* Byte 3 */ 681 unsigned char :8; /* Byte 3 */
689 unsigned char SynchronousMultiplier; /* Byte 4 */ 682 unsigned char SynchronousMultiplier; /* Byte 4 */
@@ -765,15 +758,15 @@ DAC960_V1_ErrorTable_T;
765typedef struct DAC960_V1_Config2 758typedef struct DAC960_V1_Config2
766{ 759{
767 unsigned char :1; /* Byte 0 Bit 0 */ 760 unsigned char :1; /* Byte 0 Bit 0 */
768 boolean ActiveNegationEnabled:1; /* Byte 0 Bit 1 */ 761 bool ActiveNegationEnabled:1; /* Byte 0 Bit 1 */
769 unsigned char :5; /* Byte 0 Bits 2-6 */ 762 unsigned char :5; /* Byte 0 Bits 2-6 */
770 boolean NoRescanIfResetReceivedDuringScan:1; /* Byte 0 Bit 7 */ 763 bool NoRescanIfResetReceivedDuringScan:1; /* Byte 0 Bit 7 */
771 boolean StorageWorksSupportEnabled:1; /* Byte 1 Bit 0 */ 764 bool StorageWorksSupportEnabled:1; /* Byte 1 Bit 0 */
772 boolean HewlettPackardSupportEnabled:1; /* Byte 1 Bit 1 */ 765 bool HewlettPackardSupportEnabled:1; /* Byte 1 Bit 1 */
773 boolean NoDisconnectOnFirstCommand:1; /* Byte 1 Bit 2 */ 766 bool NoDisconnectOnFirstCommand:1; /* Byte 1 Bit 2 */
774 unsigned char :2; /* Byte 1 Bits 3-4 */ 767 unsigned char :2; /* Byte 1 Bits 3-4 */
775 boolean AEMI_ARM:1; /* Byte 1 Bit 5 */ 768 bool AEMI_ARM:1; /* Byte 1 Bit 5 */
776 boolean AEMI_OFM:1; /* Byte 1 Bit 6 */ 769 bool AEMI_OFM:1; /* Byte 1 Bit 6 */
777 unsigned char :1; /* Byte 1 Bit 7 */ 770 unsigned char :1; /* Byte 1 Bit 7 */
778 enum { 771 enum {
779 DAC960_V1_OEMID_Mylex = 0x00, 772 DAC960_V1_OEMID_Mylex = 0x00,
@@ -787,13 +780,13 @@ typedef struct DAC960_V1_Config2
787 unsigned char PhysicalSector; /* Byte 4 */ 780 unsigned char PhysicalSector; /* Byte 4 */
788 unsigned char LogicalSector; /* Byte 5 */ 781 unsigned char LogicalSector; /* Byte 5 */
789 unsigned char BlockFactor; /* Byte 6 */ 782 unsigned char BlockFactor; /* Byte 6 */
790 boolean ReadAheadEnabled:1; /* Byte 7 Bit 0 */ 783 bool ReadAheadEnabled:1; /* Byte 7 Bit 0 */
791 boolean LowBIOSDelay:1; /* Byte 7 Bit 1 */ 784 bool LowBIOSDelay:1; /* Byte 7 Bit 1 */
792 unsigned char :2; /* Byte 7 Bits 2-3 */ 785 unsigned char :2; /* Byte 7 Bits 2-3 */
793 boolean ReassignRestrictedToOneSector:1; /* Byte 7 Bit 4 */ 786 bool ReassignRestrictedToOneSector:1; /* Byte 7 Bit 4 */
794 unsigned char :1; /* Byte 7 Bit 5 */ 787 unsigned char :1; /* Byte 7 Bit 5 */
795 boolean ForceUnitAccessDuringWriteRecovery:1; /* Byte 7 Bit 6 */ 788 bool ForceUnitAccessDuringWriteRecovery:1; /* Byte 7 Bit 6 */
796 boolean EnableLeftSymmetricRAID5Algorithm:1; /* Byte 7 Bit 7 */ 789 bool EnableLeftSymmetricRAID5Algorithm:1; /* Byte 7 Bit 7 */
797 unsigned char DefaultRebuildRate; /* Byte 8 */ 790 unsigned char DefaultRebuildRate; /* Byte 8 */
798 unsigned char :8; /* Byte 9 */ 791 unsigned char :8; /* Byte 9 */
799 unsigned char BlocksPerCacheLine; /* Byte 10 */ 792 unsigned char BlocksPerCacheLine; /* Byte 10 */
@@ -805,10 +798,10 @@ typedef struct DAC960_V1_Config2
805 DAC960_V1_Sync_5MHz = 0x2, 798 DAC960_V1_Sync_5MHz = 0x2,
806 DAC960_V1_Sync_10or20MHz = 0x3 /* Byte 11 Bits 0-1 */ 799 DAC960_V1_Sync_10or20MHz = 0x3 /* Byte 11 Bits 0-1 */
807 } __attribute__ ((packed)) Speed:2; 800 } __attribute__ ((packed)) Speed:2;
808 boolean Force8Bit:1; /* Byte 11 Bit 2 */ 801 bool Force8Bit:1; /* Byte 11 Bit 2 */
809 boolean DisableFast20:1; /* Byte 11 Bit 3 */ 802 bool DisableFast20:1; /* Byte 11 Bit 3 */
810 unsigned char :3; /* Byte 11 Bits 4-6 */ 803 unsigned char :3; /* Byte 11 Bits 4-6 */
811 boolean EnableTaggedQueuing:1; /* Byte 11 Bit 7 */ 804 bool EnableTaggedQueuing:1; /* Byte 11 Bit 7 */
812 } __attribute__ ((packed)) ChannelParameters[6]; /* Bytes 12-17 */ 805 } __attribute__ ((packed)) ChannelParameters[6]; /* Bytes 12-17 */
813 unsigned char SCSIInitiatorID; /* Byte 18 */ 806 unsigned char SCSIInitiatorID; /* Byte 18 */
814 unsigned char :8; /* Byte 19 */ 807 unsigned char :8; /* Byte 19 */
@@ -819,8 +812,8 @@ typedef struct DAC960_V1_Config2
819 unsigned char SimultaneousDeviceSpinUpCount; /* Byte 21 */ 812 unsigned char SimultaneousDeviceSpinUpCount; /* Byte 21 */
820 unsigned char SecondsDelayBetweenSpinUps; /* Byte 22 */ 813 unsigned char SecondsDelayBetweenSpinUps; /* Byte 22 */
821 unsigned char Reserved1[29]; /* Bytes 23-51 */ 814 unsigned char Reserved1[29]; /* Bytes 23-51 */
822 boolean BIOSDisabled:1; /* Byte 52 Bit 0 */ 815 bool BIOSDisabled:1; /* Byte 52 Bit 0 */
823 boolean CDROMBootEnabled:1; /* Byte 52 Bit 1 */ 816 bool CDROMBootEnabled:1; /* Byte 52 Bit 1 */
824 unsigned char :3; /* Byte 52 Bits 2-4 */ 817 unsigned char :3; /* Byte 52 Bits 2-4 */
825 enum { 818 enum {
826 DAC960_V1_Geometry_128_32 = 0x0, 819 DAC960_V1_Geometry_128_32 = 0x0,
@@ -849,7 +842,7 @@ typedef struct DAC960_V1_DCDB
849 DAC960_V1_DCDB_DataTransferSystemToDevice = 2, 842 DAC960_V1_DCDB_DataTransferSystemToDevice = 2,
850 DAC960_V1_DCDB_IllegalDataTransfer = 3 843 DAC960_V1_DCDB_IllegalDataTransfer = 3
851 } __attribute__ ((packed)) Direction:2; /* Byte 1 Bits 0-1 */ 844 } __attribute__ ((packed)) Direction:2; /* Byte 1 Bits 0-1 */
852 boolean EarlyStatus:1; /* Byte 1 Bit 2 */ 845 bool EarlyStatus:1; /* Byte 1 Bit 2 */
853 unsigned char :1; /* Byte 1 Bit 3 */ 846 unsigned char :1; /* Byte 1 Bit 3 */
854 enum { 847 enum {
855 DAC960_V1_DCDB_Timeout_24_hours = 0, 848 DAC960_V1_DCDB_Timeout_24_hours = 0,
@@ -857,8 +850,8 @@ typedef struct DAC960_V1_DCDB
857 DAC960_V1_DCDB_Timeout_60_seconds = 2, 850 DAC960_V1_DCDB_Timeout_60_seconds = 2,
858 DAC960_V1_DCDB_Timeout_10_minutes = 3 851 DAC960_V1_DCDB_Timeout_10_minutes = 3
859 } __attribute__ ((packed)) Timeout:2; /* Byte 1 Bits 4-5 */ 852 } __attribute__ ((packed)) Timeout:2; /* Byte 1 Bits 4-5 */
860 boolean NoAutomaticRequestSense:1; /* Byte 1 Bit 6 */ 853 bool NoAutomaticRequestSense:1; /* Byte 1 Bit 6 */
861 boolean DisconnectPermitted:1; /* Byte 1 Bit 7 */ 854 bool DisconnectPermitted:1; /* Byte 1 Bit 7 */
862 unsigned short TransferLength; /* Bytes 2-3 */ 855 unsigned short TransferLength; /* Bytes 2-3 */
863 DAC960_BusAddress32_T BusAddress; /* Bytes 4-7 */ 856 DAC960_BusAddress32_T BusAddress; /* Bytes 4-7 */
864 unsigned char CDBLength:4; /* Byte 8 Bits 0-3 */ 857 unsigned char CDBLength:4; /* Byte 8 Bits 0-3 */
@@ -920,7 +913,7 @@ typedef union DAC960_V1_CommandMailbox
920 DAC960_V1_CommandIdentifier_T CommandIdentifier; /* Byte 1 */ 913 DAC960_V1_CommandIdentifier_T CommandIdentifier; /* Byte 1 */
921 unsigned char Dummy1[5]; /* Bytes 2-6 */ 914 unsigned char Dummy1[5]; /* Bytes 2-6 */
922 unsigned char LogicalDriveNumber:6; /* Byte 7 Bits 0-6 */ 915 unsigned char LogicalDriveNumber:6; /* Byte 7 Bits 0-6 */
923 boolean AutoRestore:1; /* Byte 7 Bit 7 */ 916 bool AutoRestore:1; /* Byte 7 Bit 7 */
924 unsigned char Dummy2[8]; /* Bytes 8-15 */ 917 unsigned char Dummy2[8]; /* Bytes 8-15 */
925 } __attribute__ ((packed)) Type3C; 918 } __attribute__ ((packed)) Type3C;
926 struct { 919 struct {
@@ -1070,9 +1063,9 @@ typedef struct DAC960_V2_MemoryType
1070 DAC960_V2_MemoryType_SDRAM = 0x04, 1063 DAC960_V2_MemoryType_SDRAM = 0x04,
1071 DAC960_V2_MemoryType_Last = 0x1F 1064 DAC960_V2_MemoryType_Last = 0x1F
1072 } __attribute__ ((packed)) MemoryType:5; /* Byte 0 Bits 0-4 */ 1065 } __attribute__ ((packed)) MemoryType:5; /* Byte 0 Bits 0-4 */
1073 boolean :1; /* Byte 0 Bit 5 */ 1066 bool :1; /* Byte 0 Bit 5 */
1074 boolean MemoryParity:1; /* Byte 0 Bit 6 */ 1067 bool MemoryParity:1; /* Byte 0 Bit 6 */
1075 boolean MemoryECC:1; /* Byte 0 Bit 7 */ 1068 bool MemoryECC:1; /* Byte 0 Bit 7 */
1076} 1069}
1077DAC960_V2_MemoryType_T; 1070DAC960_V2_MemoryType_T;
1078 1071
@@ -1187,13 +1180,13 @@ typedef struct DAC960_V2_ControllerInfo
1187 unsigned char OEM_Code; /* Byte 131 */ 1180 unsigned char OEM_Code; /* Byte 131 */
1188 unsigned char VendorName[16]; /* Bytes 132-147 */ 1181 unsigned char VendorName[16]; /* Bytes 132-147 */
1189 /* Other Physical/Controller/Operation Information */ 1182 /* Other Physical/Controller/Operation Information */
1190 boolean BBU_Present:1; /* Byte 148 Bit 0 */ 1183 bool BBU_Present:1; /* Byte 148 Bit 0 */
1191 boolean ActiveActiveClusteringMode:1; /* Byte 148 Bit 1 */ 1184 bool ActiveActiveClusteringMode:1; /* Byte 148 Bit 1 */
1192 unsigned char :6; /* Byte 148 Bits 2-7 */ 1185 unsigned char :6; /* Byte 148 Bits 2-7 */
1193 unsigned char :8; /* Byte 149 */ 1186 unsigned char :8; /* Byte 149 */
1194 unsigned short :16; /* Bytes 150-151 */ 1187 unsigned short :16; /* Bytes 150-151 */
1195 /* Physical Device Scan Information */ 1188 /* Physical Device Scan Information */
1196 boolean PhysicalScanActive:1; /* Byte 152 Bit 0 */ 1189 bool PhysicalScanActive:1; /* Byte 152 Bit 0 */
1197 unsigned char :7; /* Byte 152 Bits 1-7 */ 1190 unsigned char :7; /* Byte 152 Bits 1-7 */
1198 unsigned char PhysicalDeviceChannelNumber; /* Byte 153 */ 1191 unsigned char PhysicalDeviceChannelNumber; /* Byte 153 */
1199 unsigned char PhysicalDeviceTargetID; /* Byte 154 */ 1192 unsigned char PhysicalDeviceTargetID; /* Byte 154 */
@@ -1305,8 +1298,8 @@ typedef struct DAC960_V2_ControllerInfo
1305 unsigned int FreeIOP; /* Bytes 468-471 */ 1298 unsigned int FreeIOP; /* Bytes 468-471 */
1306 unsigned short MaximumCombLengthInBlocks; /* Bytes 472-473 */ 1299 unsigned short MaximumCombLengthInBlocks; /* Bytes 472-473 */
1307 unsigned short NumberOfConfigurationGroups; /* Bytes 474-475 */ 1300 unsigned short NumberOfConfigurationGroups; /* Bytes 474-475 */
1308 boolean InstallationAbortStatus:1; /* Byte 476 Bit 0 */ 1301 bool InstallationAbortStatus:1; /* Byte 476 Bit 0 */
1309 boolean MaintenanceModeStatus:1; /* Byte 476 Bit 1 */ 1302 bool MaintenanceModeStatus:1; /* Byte 476 Bit 1 */
1310 unsigned int :24; /* Bytes 476-479 */ 1303 unsigned int :24; /* Bytes 476-479 */
1311 unsigned char Reserved10[32]; /* Bytes 480-511 */ 1304 unsigned char Reserved10[32]; /* Bytes 480-511 */
1312 unsigned char Reserved11[512]; /* Bytes 512-1023 */ 1305 unsigned char Reserved11[512]; /* Bytes 512-1023 */
@@ -1357,33 +1350,33 @@ typedef struct DAC960_V2_LogicalDeviceInfo
1357 DAC960_V2_IntelligentWriteCacheEnabled = 0x3, 1350 DAC960_V2_IntelligentWriteCacheEnabled = 0x3,
1358 DAC960_V2_WriteCache_Last = 0x7 1351 DAC960_V2_WriteCache_Last = 0x7
1359 } __attribute__ ((packed)) WriteCache:3; /* Byte 8 Bits 3-5 */ 1352 } __attribute__ ((packed)) WriteCache:3; /* Byte 8 Bits 3-5 */
1360 boolean :1; /* Byte 8 Bit 6 */ 1353 bool :1; /* Byte 8 Bit 6 */
1361 boolean LogicalDeviceInitialized:1; /* Byte 8 Bit 7 */ 1354 bool LogicalDeviceInitialized:1; /* Byte 8 Bit 7 */
1362 } LogicalDeviceControl; /* Byte 8 */ 1355 } LogicalDeviceControl; /* Byte 8 */
1363 /* Logical Device Operations Status */ 1356 /* Logical Device Operations Status */
1364 boolean ConsistencyCheckInProgress:1; /* Byte 9 Bit 0 */ 1357 bool ConsistencyCheckInProgress:1; /* Byte 9 Bit 0 */
1365 boolean RebuildInProgress:1; /* Byte 9 Bit 1 */ 1358 bool RebuildInProgress:1; /* Byte 9 Bit 1 */
1366 boolean BackgroundInitializationInProgress:1; /* Byte 9 Bit 2 */ 1359 bool BackgroundInitializationInProgress:1; /* Byte 9 Bit 2 */
1367 boolean ForegroundInitializationInProgress:1; /* Byte 9 Bit 3 */ 1360 bool ForegroundInitializationInProgress:1; /* Byte 9 Bit 3 */
1368 boolean DataMigrationInProgress:1; /* Byte 9 Bit 4 */ 1361 bool DataMigrationInProgress:1; /* Byte 9 Bit 4 */
1369 boolean PatrolOperationInProgress:1; /* Byte 9 Bit 5 */ 1362 bool PatrolOperationInProgress:1; /* Byte 9 Bit 5 */
1370 unsigned char :2; /* Byte 9 Bits 6-7 */ 1363 unsigned char :2; /* Byte 9 Bits 6-7 */
1371 unsigned char RAID5WriteUpdate; /* Byte 10 */ 1364 unsigned char RAID5WriteUpdate; /* Byte 10 */
1372 unsigned char RAID5Algorithm; /* Byte 11 */ 1365 unsigned char RAID5Algorithm; /* Byte 11 */
1373 unsigned short LogicalDeviceNumber; /* Bytes 12-13 */ 1366 unsigned short LogicalDeviceNumber; /* Bytes 12-13 */
1374 /* BIOS Info */ 1367 /* BIOS Info */
1375 boolean BIOSDisabled:1; /* Byte 14 Bit 0 */ 1368 bool BIOSDisabled:1; /* Byte 14 Bit 0 */
1376 boolean CDROMBootEnabled:1; /* Byte 14 Bit 1 */ 1369 bool CDROMBootEnabled:1; /* Byte 14 Bit 1 */
1377 boolean DriveCoercionEnabled:1; /* Byte 14 Bit 2 */ 1370 bool DriveCoercionEnabled:1; /* Byte 14 Bit 2 */
1378 boolean WriteSameDisabled:1; /* Byte 14 Bit 3 */ 1371 bool WriteSameDisabled:1; /* Byte 14 Bit 3 */
1379 boolean HBA_ModeEnabled:1; /* Byte 14 Bit 4 */ 1372 bool HBA_ModeEnabled:1; /* Byte 14 Bit 4 */
1380 enum { 1373 enum {
1381 DAC960_V2_Geometry_128_32 = 0x0, 1374 DAC960_V2_Geometry_128_32 = 0x0,
1382 DAC960_V2_Geometry_255_63 = 0x1, 1375 DAC960_V2_Geometry_255_63 = 0x1,
1383 DAC960_V2_Geometry_Reserved1 = 0x2, 1376 DAC960_V2_Geometry_Reserved1 = 0x2,
1384 DAC960_V2_Geometry_Reserved2 = 0x3 1377 DAC960_V2_Geometry_Reserved2 = 0x3
1385 } __attribute__ ((packed)) DriveGeometry:2; /* Byte 14 Bits 5-6 */ 1378 } __attribute__ ((packed)) DriveGeometry:2; /* Byte 14 Bits 5-6 */
1386 boolean SuperReadAheadEnabled:1; /* Byte 14 Bit 7 */ 1379 bool SuperReadAheadEnabled:1; /* Byte 14 Bit 7 */
1387 unsigned char :8; /* Byte 15 */ 1380 unsigned char :8; /* Byte 15 */
1388 /* Error Counters */ 1381 /* Error Counters */
1389 unsigned short SoftErrors; /* Bytes 16-17 */ 1382 unsigned short SoftErrors; /* Bytes 16-17 */
@@ -1446,13 +1439,13 @@ typedef struct DAC960_V2_PhysicalDeviceInfo
1446 unsigned char TargetID; /* Byte 2 */ 1439 unsigned char TargetID; /* Byte 2 */
1447 unsigned char LogicalUnit; /* Byte 3 */ 1440 unsigned char LogicalUnit; /* Byte 3 */
1448 /* Configuration Status Bits */ 1441 /* Configuration Status Bits */
1449 boolean PhysicalDeviceFaultTolerant:1; /* Byte 4 Bit 0 */ 1442 bool PhysicalDeviceFaultTolerant:1; /* Byte 4 Bit 0 */
1450 boolean PhysicalDeviceConnected:1; /* Byte 4 Bit 1 */ 1443 bool PhysicalDeviceConnected:1; /* Byte 4 Bit 1 */
1451 boolean PhysicalDeviceLocalToController:1; /* Byte 4 Bit 2 */ 1444 bool PhysicalDeviceLocalToController:1; /* Byte 4 Bit 2 */
1452 unsigned char :5; /* Byte 4 Bits 3-7 */ 1445 unsigned char :5; /* Byte 4 Bits 3-7 */
1453 /* Multiple Host/Controller Status Bits */ 1446 /* Multiple Host/Controller Status Bits */
1454 boolean RemoteHostSystemDead:1; /* Byte 5 Bit 0 */ 1447 bool RemoteHostSystemDead:1; /* Byte 5 Bit 0 */
1455 boolean RemoteControllerDead:1; /* Byte 5 Bit 1 */ 1448 bool RemoteControllerDead:1; /* Byte 5 Bit 1 */
1456 unsigned char :6; /* Byte 5 Bits 2-7 */ 1449 unsigned char :6; /* Byte 5 Bits 2-7 */
1457 DAC960_V2_PhysicalDeviceState_T PhysicalDeviceState; /* Byte 6 */ 1450 DAC960_V2_PhysicalDeviceState_T PhysicalDeviceState; /* Byte 6 */
1458 unsigned char NegotiatedDataWidthBits; /* Byte 7 */ 1451 unsigned char NegotiatedDataWidthBits; /* Byte 7 */
@@ -1464,12 +1457,12 @@ typedef struct DAC960_V2_PhysicalDeviceInfo
1464 unsigned char NetworkAddress[16]; /* Bytes 16-31 */ 1457 unsigned char NetworkAddress[16]; /* Bytes 16-31 */
1465 unsigned short MaximumTags; /* Bytes 32-33 */ 1458 unsigned short MaximumTags; /* Bytes 32-33 */
1466 /* Physical Device Operations Status */ 1459 /* Physical Device Operations Status */
1467 boolean ConsistencyCheckInProgress:1; /* Byte 34 Bit 0 */ 1460 bool ConsistencyCheckInProgress:1; /* Byte 34 Bit 0 */
1468 boolean RebuildInProgress:1; /* Byte 34 Bit 1 */ 1461 bool RebuildInProgress:1; /* Byte 34 Bit 1 */
1469 boolean MakingDataConsistentInProgress:1; /* Byte 34 Bit 2 */ 1462 bool MakingDataConsistentInProgress:1; /* Byte 34 Bit 2 */
1470 boolean PhysicalDeviceInitializationInProgress:1; /* Byte 34 Bit 3 */ 1463 bool PhysicalDeviceInitializationInProgress:1; /* Byte 34 Bit 3 */
1471 boolean DataMigrationInProgress:1; /* Byte 34 Bit 4 */ 1464 bool DataMigrationInProgress:1; /* Byte 34 Bit 4 */
1472 boolean PatrolOperationInProgress:1; /* Byte 34 Bit 5 */ 1465 bool PatrolOperationInProgress:1; /* Byte 34 Bit 5 */
1473 unsigned char :2; /* Byte 34 Bits 6-7 */ 1466 unsigned char :2; /* Byte 34 Bits 6-7 */
1474 unsigned char LongOperationStatus; /* Byte 35 */ 1467 unsigned char LongOperationStatus; /* Byte 35 */
1475 unsigned char ParityErrors; /* Byte 36 */ 1468 unsigned char ParityErrors; /* Byte 36 */
@@ -1555,14 +1548,14 @@ DAC960_V2_Event_T;
1555 1548
1556typedef struct DAC960_V2_CommandControlBits 1549typedef struct DAC960_V2_CommandControlBits
1557{ 1550{
1558 boolean ForceUnitAccess:1; /* Byte 0 Bit 0 */ 1551 bool ForceUnitAccess:1; /* Byte 0 Bit 0 */
1559 boolean DisablePageOut:1; /* Byte 0 Bit 1 */ 1552 bool DisablePageOut:1; /* Byte 0 Bit 1 */
1560 boolean :1; /* Byte 0 Bit 2 */ 1553 bool :1; /* Byte 0 Bit 2 */
1561 boolean AdditionalScatterGatherListMemory:1; /* Byte 0 Bit 3 */ 1554 bool AdditionalScatterGatherListMemory:1; /* Byte 0 Bit 3 */
1562 boolean DataTransferControllerToHost:1; /* Byte 0 Bit 4 */ 1555 bool DataTransferControllerToHost:1; /* Byte 0 Bit 4 */
1563 boolean :1; /* Byte 0 Bit 5 */ 1556 bool :1; /* Byte 0 Bit 5 */
1564 boolean NoAutoRequestSense:1; /* Byte 0 Bit 6 */ 1557 bool NoAutoRequestSense:1; /* Byte 0 Bit 6 */
1565 boolean DisconnectProhibited:1; /* Byte 0 Bit 7 */ 1558 bool DisconnectProhibited:1; /* Byte 0 Bit 7 */
1566} 1559}
1567DAC960_V2_CommandControlBits_T; 1560DAC960_V2_CommandControlBits_T;
1568 1561
@@ -1825,8 +1818,8 @@ typedef union DAC960_V2_CommandMailbox
1825 DAC960_V2_CommandTimeout_T CommandTimeout; /* Byte 19 */ 1818 DAC960_V2_CommandTimeout_T CommandTimeout; /* Byte 19 */
1826 unsigned char RequestSenseSize; /* Byte 20 */ 1819 unsigned char RequestSenseSize; /* Byte 20 */
1827 unsigned char IOCTL_Opcode; /* Byte 21 */ 1820 unsigned char IOCTL_Opcode; /* Byte 21 */
1828 boolean RestoreConsistency:1; /* Byte 22 Bit 0 */ 1821 bool RestoreConsistency:1; /* Byte 22 Bit 0 */
1829 boolean InitializedAreaOnly:1; /* Byte 22 Bit 1 */ 1822 bool InitializedAreaOnly:1; /* Byte 22 Bit 1 */
1830 unsigned char :6; /* Byte 22 Bits 2-7 */ 1823 unsigned char :6; /* Byte 22 Bits 2-7 */
1831 unsigned char Reserved[9]; /* Bytes 23-31 */ 1824 unsigned char Reserved[9]; /* Bytes 23-31 */
1832 DAC960_V2_DataTransferMemoryAddress_T 1825 DAC960_V2_DataTransferMemoryAddress_T
@@ -2190,7 +2183,7 @@ typedef union DAC960_V1_StatusMailbox
2190 struct { 2183 struct {
2191 DAC960_V1_CommandIdentifier_T CommandIdentifier; /* Byte 0 */ 2184 DAC960_V1_CommandIdentifier_T CommandIdentifier; /* Byte 0 */
2192 unsigned char :7; /* Byte 1 Bits 0-6 */ 2185 unsigned char :7; /* Byte 1 Bits 0-6 */
2193 boolean Valid:1; /* Byte 1 Bit 7 */ 2186 bool Valid:1; /* Byte 1 Bit 7 */
2194 DAC960_V1_CommandStatus_T CommandStatus; /* Bytes 2-3 */ 2187 DAC960_V1_CommandStatus_T CommandStatus; /* Bytes 2-3 */
2195 } Fields; 2188 } Fields;
2196} 2189}
@@ -2322,12 +2315,12 @@ typedef struct DAC960_Controller
2322 unsigned long ShutdownMonitoringTimer; 2315 unsigned long ShutdownMonitoringTimer;
2323 unsigned long LastProgressReportTime; 2316 unsigned long LastProgressReportTime;
2324 unsigned long LastCurrentStatusTime; 2317 unsigned long LastCurrentStatusTime;
2325 boolean ControllerInitialized; 2318 bool ControllerInitialized;
2326 boolean MonitoringCommandDeferred; 2319 bool MonitoringCommandDeferred;
2327 boolean EphemeralProgressMessage; 2320 bool EphemeralProgressMessage;
2328 boolean DriveSpinUpMessageDisplayed; 2321 bool DriveSpinUpMessageDisplayed;
2329 boolean MonitoringAlertMode; 2322 bool MonitoringAlertMode;
2330 boolean SuppressEnclosureMessages; 2323 bool SuppressEnclosureMessages;
2331 struct timer_list MonitoringTimer; 2324 struct timer_list MonitoringTimer;
2332 struct gendisk *disks[DAC960_MaxLogicalDrives]; 2325 struct gendisk *disks[DAC960_MaxLogicalDrives];
2333 struct pci_pool *ScatterGatherPool; 2326 struct pci_pool *ScatterGatherPool;
@@ -2342,11 +2335,11 @@ typedef struct DAC960_Controller
2342 DAC960_Command_T InitialCommand; 2335 DAC960_Command_T InitialCommand;
2343 DAC960_Command_T *Commands[DAC960_MaxDriverQueueDepth]; 2336 DAC960_Command_T *Commands[DAC960_MaxDriverQueueDepth];
2344 struct proc_dir_entry *ControllerProcEntry; 2337 struct proc_dir_entry *ControllerProcEntry;
2345 boolean LogicalDriveInitiallyAccessible[DAC960_MaxLogicalDrives]; 2338 bool LogicalDriveInitiallyAccessible[DAC960_MaxLogicalDrives];
2346 void (*QueueCommand)(DAC960_Command_T *Command); 2339 void (*QueueCommand)(DAC960_Command_T *Command);
2347 boolean (*ReadControllerConfiguration)(struct DAC960_Controller *); 2340 bool (*ReadControllerConfiguration)(struct DAC960_Controller *);
2348 boolean (*ReadDeviceConfiguration)(struct DAC960_Controller *); 2341 bool (*ReadDeviceConfiguration)(struct DAC960_Controller *);
2349 boolean (*ReportDeviceConfiguration)(struct DAC960_Controller *); 2342 bool (*ReportDeviceConfiguration)(struct DAC960_Controller *);
2350 void (*QueueReadWriteCommand)(DAC960_Command_T *Command); 2343 void (*QueueReadWriteCommand)(DAC960_Command_T *Command);
2351 union { 2344 union {
2352 struct { 2345 struct {
@@ -2359,21 +2352,21 @@ typedef struct DAC960_Controller
2359 unsigned short OldEventLogSequenceNumber; 2352 unsigned short OldEventLogSequenceNumber;
2360 unsigned short DeviceStateChannel; 2353 unsigned short DeviceStateChannel;
2361 unsigned short DeviceStateTargetID; 2354 unsigned short DeviceStateTargetID;
2362 boolean DualModeMemoryMailboxInterface; 2355 bool DualModeMemoryMailboxInterface;
2363 boolean BackgroundInitializationStatusSupported; 2356 bool BackgroundInitializationStatusSupported;
2364 boolean SAFTE_EnclosureManagementEnabled; 2357 bool SAFTE_EnclosureManagementEnabled;
2365 boolean NeedLogicalDriveInformation; 2358 bool NeedLogicalDriveInformation;
2366 boolean NeedErrorTableInformation; 2359 bool NeedErrorTableInformation;
2367 boolean NeedDeviceStateInformation; 2360 bool NeedDeviceStateInformation;
2368 boolean NeedDeviceInquiryInformation; 2361 bool NeedDeviceInquiryInformation;
2369 boolean NeedDeviceSerialNumberInformation; 2362 bool NeedDeviceSerialNumberInformation;
2370 boolean NeedRebuildProgress; 2363 bool NeedRebuildProgress;
2371 boolean NeedConsistencyCheckProgress; 2364 bool NeedConsistencyCheckProgress;
2372 boolean NeedBackgroundInitializationStatus; 2365 bool NeedBackgroundInitializationStatus;
2373 boolean StartDeviceStateScan; 2366 bool StartDeviceStateScan;
2374 boolean RebuildProgressFirst; 2367 bool RebuildProgressFirst;
2375 boolean RebuildFlagPending; 2368 bool RebuildFlagPending;
2376 boolean RebuildStatusPending; 2369 bool RebuildStatusPending;
2377 2370
2378 dma_addr_t FirstCommandMailboxDMA; 2371 dma_addr_t FirstCommandMailboxDMA;
2379 DAC960_V1_CommandMailbox_T *FirstCommandMailbox; 2372 DAC960_V1_CommandMailbox_T *FirstCommandMailbox;
@@ -2432,17 +2425,17 @@ typedef struct DAC960_Controller
2432 dma_addr_t NewInquiryUnitSerialNumberDMA; 2425 dma_addr_t NewInquiryUnitSerialNumberDMA;
2433 2426
2434 int DeviceResetCount[DAC960_V1_MaxChannels][DAC960_V1_MaxTargets]; 2427 int DeviceResetCount[DAC960_V1_MaxChannels][DAC960_V1_MaxTargets];
2435 boolean DirectCommandActive[DAC960_V1_MaxChannels][DAC960_V1_MaxTargets]; 2428 bool DirectCommandActive[DAC960_V1_MaxChannels][DAC960_V1_MaxTargets];
2436 } V1; 2429 } V1;
2437 struct { 2430 struct {
2438 unsigned int StatusChangeCounter; 2431 unsigned int StatusChangeCounter;
2439 unsigned int NextEventSequenceNumber; 2432 unsigned int NextEventSequenceNumber;
2440 unsigned int PhysicalDeviceIndex; 2433 unsigned int PhysicalDeviceIndex;
2441 boolean NeedLogicalDeviceInformation; 2434 bool NeedLogicalDeviceInformation;
2442 boolean NeedPhysicalDeviceInformation; 2435 bool NeedPhysicalDeviceInformation;
2443 boolean NeedDeviceSerialNumberInformation; 2436 bool NeedDeviceSerialNumberInformation;
2444 boolean StartLogicalDeviceInformationScan; 2437 bool StartLogicalDeviceInformationScan;
2445 boolean StartPhysicalDeviceInformationScan; 2438 bool StartPhysicalDeviceInformationScan;
2446 struct pci_pool *RequestSensePool; 2439 struct pci_pool *RequestSensePool;
2447 2440
2448 dma_addr_t FirstCommandMailboxDMA; 2441 dma_addr_t FirstCommandMailboxDMA;
@@ -2487,7 +2480,7 @@ typedef struct DAC960_Controller
2487 2480
2488 DAC960_V2_PhysicalDevice_T 2481 DAC960_V2_PhysicalDevice_T
2489 LogicalDriveToVirtualDevice[DAC960_MaxLogicalDrives]; 2482 LogicalDriveToVirtualDevice[DAC960_MaxLogicalDrives];
2490 boolean LogicalDriveFoundDuringScan[DAC960_MaxLogicalDrives]; 2483 bool LogicalDriveFoundDuringScan[DAC960_MaxLogicalDrives];
2491 } V2; 2484 } V2;
2492 } FW; 2485 } FW;
2493 unsigned char ProgressBuffer[DAC960_ProgressBufferSize]; 2486 unsigned char ProgressBuffer[DAC960_ProgressBufferSize];
@@ -2572,17 +2565,17 @@ typedef union DAC960_GEM_InboundDoorBellRegister
2572 unsigned int All; 2565 unsigned int All;
2573 struct { 2566 struct {
2574 unsigned int :24; 2567 unsigned int :24;
2575 boolean HardwareMailboxNewCommand:1; 2568 bool HardwareMailboxNewCommand:1;
2576 boolean AcknowledgeHardwareMailboxStatus:1; 2569 bool AcknowledgeHardwareMailboxStatus:1;
2577 boolean GenerateInterrupt:1; 2570 bool GenerateInterrupt:1;
2578 boolean ControllerReset:1; 2571 bool ControllerReset:1;
2579 boolean MemoryMailboxNewCommand:1; 2572 bool MemoryMailboxNewCommand:1;
2580 unsigned int :3; 2573 unsigned int :3;
2581 } Write; 2574 } Write;
2582 struct { 2575 struct {
2583 unsigned int :24; 2576 unsigned int :24;
2584 boolean HardwareMailboxFull:1; 2577 bool HardwareMailboxFull:1;
2585 boolean InitializationInProgress:1; 2578 bool InitializationInProgress:1;
2586 unsigned int :6; 2579 unsigned int :6;
2587 } Read; 2580 } Read;
2588} 2581}
@@ -2596,14 +2589,14 @@ typedef union DAC960_GEM_OutboundDoorBellRegister
2596 unsigned int All; 2589 unsigned int All;
2597 struct { 2590 struct {
2598 unsigned int :24; 2591 unsigned int :24;
2599 boolean AcknowledgeHardwareMailboxInterrupt:1; 2592 bool AcknowledgeHardwareMailboxInterrupt:1;
2600 boolean AcknowledgeMemoryMailboxInterrupt:1; 2593 bool AcknowledgeMemoryMailboxInterrupt:1;
2601 unsigned int :6; 2594 unsigned int :6;
2602 } Write; 2595 } Write;
2603 struct { 2596 struct {
2604 unsigned int :24; 2597 unsigned int :24;
2605 boolean HardwareMailboxStatusAvailable:1; 2598 bool HardwareMailboxStatusAvailable:1;
2606 boolean MemoryMailboxStatusAvailable:1; 2599 bool MemoryMailboxStatusAvailable:1;
2607 unsigned int :6; 2600 unsigned int :6;
2608 } Read; 2601 } Read;
2609} 2602}
@@ -2635,7 +2628,7 @@ typedef union DAC960_GEM_ErrorStatusRegister
2635 struct { 2628 struct {
2636 unsigned int :24; 2629 unsigned int :24;
2637 unsigned int :5; 2630 unsigned int :5;
2638 boolean ErrorStatusPending:1; 2631 bool ErrorStatusPending:1;
2639 unsigned int :2; 2632 unsigned int :2;
2640 } Bits; 2633 } Bits;
2641} 2634}
@@ -2697,7 +2690,7 @@ void DAC960_GEM_MemoryMailboxNewCommand(void __iomem *ControllerBaseAddress)
2697} 2690}
2698 2691
2699static inline 2692static inline
2700boolean DAC960_GEM_HardwareMailboxFullP(void __iomem *ControllerBaseAddress) 2693bool DAC960_GEM_HardwareMailboxFullP(void __iomem *ControllerBaseAddress)
2701{ 2694{
2702 DAC960_GEM_InboundDoorBellRegister_T InboundDoorBellRegister; 2695 DAC960_GEM_InboundDoorBellRegister_T InboundDoorBellRegister;
2703 InboundDoorBellRegister.All = 2696 InboundDoorBellRegister.All =
@@ -2707,7 +2700,7 @@ boolean DAC960_GEM_HardwareMailboxFullP(void __iomem *ControllerBaseAddress)
2707} 2700}
2708 2701
2709static inline 2702static inline
2710boolean DAC960_GEM_InitializationInProgressP(void __iomem *ControllerBaseAddress) 2703bool DAC960_GEM_InitializationInProgressP(void __iomem *ControllerBaseAddress)
2711{ 2704{
2712 DAC960_GEM_InboundDoorBellRegister_T InboundDoorBellRegister; 2705 DAC960_GEM_InboundDoorBellRegister_T InboundDoorBellRegister;
2713 InboundDoorBellRegister.All = 2706 InboundDoorBellRegister.All =
@@ -2748,7 +2741,7 @@ void DAC960_GEM_AcknowledgeInterrupt(void __iomem *ControllerBaseAddress)
2748} 2741}
2749 2742
2750static inline 2743static inline
2751boolean DAC960_GEM_HardwareMailboxStatusAvailableP(void __iomem *ControllerBaseAddress) 2744bool DAC960_GEM_HardwareMailboxStatusAvailableP(void __iomem *ControllerBaseAddress)
2752{ 2745{
2753 DAC960_GEM_OutboundDoorBellRegister_T OutboundDoorBellRegister; 2746 DAC960_GEM_OutboundDoorBellRegister_T OutboundDoorBellRegister;
2754 OutboundDoorBellRegister.All = 2747 OutboundDoorBellRegister.All =
@@ -2758,7 +2751,7 @@ boolean DAC960_GEM_HardwareMailboxStatusAvailableP(void __iomem *ControllerBaseA
2758} 2751}
2759 2752
2760static inline 2753static inline
2761boolean DAC960_GEM_MemoryMailboxStatusAvailableP(void __iomem *ControllerBaseAddress) 2754bool DAC960_GEM_MemoryMailboxStatusAvailableP(void __iomem *ControllerBaseAddress)
2762{ 2755{
2763 DAC960_GEM_OutboundDoorBellRegister_T OutboundDoorBellRegister; 2756 DAC960_GEM_OutboundDoorBellRegister_T OutboundDoorBellRegister;
2764 OutboundDoorBellRegister.All = 2757 OutboundDoorBellRegister.All =
@@ -2790,7 +2783,7 @@ void DAC960_GEM_DisableInterrupts(void __iomem *ControllerBaseAddress)
2790} 2783}
2791 2784
2792static inline 2785static inline
2793boolean DAC960_GEM_InterruptsEnabledP(void __iomem *ControllerBaseAddress) 2786bool DAC960_GEM_InterruptsEnabledP(void __iomem *ControllerBaseAddress)
2794{ 2787{
2795 DAC960_GEM_InterruptMaskRegister_T InterruptMaskRegister; 2788 DAC960_GEM_InterruptMaskRegister_T InterruptMaskRegister;
2796 InterruptMaskRegister.All = 2789 InterruptMaskRegister.All =
@@ -2834,7 +2827,7 @@ DAC960_GEM_ReadCommandStatus(void __iomem *ControllerBaseAddress)
2834 return readw(ControllerBaseAddress + DAC960_GEM_CommandStatusOffset + 2); 2827 return readw(ControllerBaseAddress + DAC960_GEM_CommandStatusOffset + 2);
2835} 2828}
2836 2829
2837static inline boolean 2830static inline bool
2838DAC960_GEM_ReadErrorStatus(void __iomem *ControllerBaseAddress, 2831DAC960_GEM_ReadErrorStatus(void __iomem *ControllerBaseAddress,
2839 unsigned char *ErrorStatus, 2832 unsigned char *ErrorStatus,
2840 unsigned char *Parameter0, 2833 unsigned char *Parameter0,
@@ -2882,16 +2875,16 @@ typedef union DAC960_BA_InboundDoorBellRegister
2882{ 2875{
2883 unsigned char All; 2876 unsigned char All;
2884 struct { 2877 struct {
2885 boolean HardwareMailboxNewCommand:1; /* Bit 0 */ 2878 bool HardwareMailboxNewCommand:1; /* Bit 0 */
2886 boolean AcknowledgeHardwareMailboxStatus:1; /* Bit 1 */ 2879 bool AcknowledgeHardwareMailboxStatus:1; /* Bit 1 */
2887 boolean GenerateInterrupt:1; /* Bit 2 */ 2880 bool GenerateInterrupt:1; /* Bit 2 */
2888 boolean ControllerReset:1; /* Bit 3 */ 2881 bool ControllerReset:1; /* Bit 3 */
2889 boolean MemoryMailboxNewCommand:1; /* Bit 4 */ 2882 bool MemoryMailboxNewCommand:1; /* Bit 4 */
2890 unsigned char :3; /* Bits 5-7 */ 2883 unsigned char :3; /* Bits 5-7 */
2891 } Write; 2884 } Write;
2892 struct { 2885 struct {
2893 boolean HardwareMailboxEmpty:1; /* Bit 0 */ 2886 bool HardwareMailboxEmpty:1; /* Bit 0 */
2894 boolean InitializationNotInProgress:1; /* Bit 1 */ 2887 bool InitializationNotInProgress:1; /* Bit 1 */
2895 unsigned char :6; /* Bits 2-7 */ 2888 unsigned char :6; /* Bits 2-7 */
2896 } Read; 2889 } Read;
2897} 2890}
@@ -2906,13 +2899,13 @@ typedef union DAC960_BA_OutboundDoorBellRegister
2906{ 2899{
2907 unsigned char All; 2900 unsigned char All;
2908 struct { 2901 struct {
2909 boolean AcknowledgeHardwareMailboxInterrupt:1; /* Bit 0 */ 2902 bool AcknowledgeHardwareMailboxInterrupt:1; /* Bit 0 */
2910 boolean AcknowledgeMemoryMailboxInterrupt:1; /* Bit 1 */ 2903 bool AcknowledgeMemoryMailboxInterrupt:1; /* Bit 1 */
2911 unsigned char :6; /* Bits 2-7 */ 2904 unsigned char :6; /* Bits 2-7 */
2912 } Write; 2905 } Write;
2913 struct { 2906 struct {
2914 boolean HardwareMailboxStatusAvailable:1; /* Bit 0 */ 2907 bool HardwareMailboxStatusAvailable:1; /* Bit 0 */
2915 boolean MemoryMailboxStatusAvailable:1; /* Bit 1 */ 2908 bool MemoryMailboxStatusAvailable:1; /* Bit 1 */
2916 unsigned char :6; /* Bits 2-7 */ 2909 unsigned char :6; /* Bits 2-7 */
2917 } Read; 2910 } Read;
2918} 2911}
@@ -2928,8 +2921,8 @@ typedef union DAC960_BA_InterruptMaskRegister
2928 unsigned char All; 2921 unsigned char All;
2929 struct { 2922 struct {
2930 unsigned int :2; /* Bits 0-1 */ 2923 unsigned int :2; /* Bits 0-1 */
2931 boolean DisableInterrupts:1; /* Bit 2 */ 2924 bool DisableInterrupts:1; /* Bit 2 */
2932 boolean DisableInterruptsI2O:1; /* Bit 3 */ 2925 bool DisableInterruptsI2O:1; /* Bit 3 */
2933 unsigned int :4; /* Bits 4-7 */ 2926 unsigned int :4; /* Bits 4-7 */
2934 } Bits; 2927 } Bits;
2935} 2928}
@@ -2945,7 +2938,7 @@ typedef union DAC960_BA_ErrorStatusRegister
2945 unsigned char All; 2938 unsigned char All;
2946 struct { 2939 struct {
2947 unsigned int :2; /* Bits 0-1 */ 2940 unsigned int :2; /* Bits 0-1 */
2948 boolean ErrorStatusPending:1; /* Bit 2 */ 2941 bool ErrorStatusPending:1; /* Bit 2 */
2949 unsigned int :5; /* Bits 3-7 */ 2942 unsigned int :5; /* Bits 3-7 */
2950 } Bits; 2943 } Bits;
2951} 2944}
@@ -3008,7 +3001,7 @@ void DAC960_BA_MemoryMailboxNewCommand(void __iomem *ControllerBaseAddress)
3008} 3001}
3009 3002
3010static inline 3003static inline
3011boolean DAC960_BA_HardwareMailboxFullP(void __iomem *ControllerBaseAddress) 3004bool DAC960_BA_HardwareMailboxFullP(void __iomem *ControllerBaseAddress)
3012{ 3005{
3013 DAC960_BA_InboundDoorBellRegister_T InboundDoorBellRegister; 3006 DAC960_BA_InboundDoorBellRegister_T InboundDoorBellRegister;
3014 InboundDoorBellRegister.All = 3007 InboundDoorBellRegister.All =
@@ -3017,7 +3010,7 @@ boolean DAC960_BA_HardwareMailboxFullP(void __iomem *ControllerBaseAddress)
3017} 3010}
3018 3011
3019static inline 3012static inline
3020boolean DAC960_BA_InitializationInProgressP(void __iomem *ControllerBaseAddress) 3013bool DAC960_BA_InitializationInProgressP(void __iomem *ControllerBaseAddress)
3021{ 3014{
3022 DAC960_BA_InboundDoorBellRegister_T InboundDoorBellRegister; 3015 DAC960_BA_InboundDoorBellRegister_T InboundDoorBellRegister;
3023 InboundDoorBellRegister.All = 3016 InboundDoorBellRegister.All =
@@ -3057,7 +3050,7 @@ void DAC960_BA_AcknowledgeInterrupt(void __iomem *ControllerBaseAddress)
3057} 3050}
3058 3051
3059static inline 3052static inline
3060boolean DAC960_BA_HardwareMailboxStatusAvailableP(void __iomem *ControllerBaseAddress) 3053bool DAC960_BA_HardwareMailboxStatusAvailableP(void __iomem *ControllerBaseAddress)
3061{ 3054{
3062 DAC960_BA_OutboundDoorBellRegister_T OutboundDoorBellRegister; 3055 DAC960_BA_OutboundDoorBellRegister_T OutboundDoorBellRegister;
3063 OutboundDoorBellRegister.All = 3056 OutboundDoorBellRegister.All =
@@ -3066,7 +3059,7 @@ boolean DAC960_BA_HardwareMailboxStatusAvailableP(void __iomem *ControllerBaseAd
3066} 3059}
3067 3060
3068static inline 3061static inline
3069boolean DAC960_BA_MemoryMailboxStatusAvailableP(void __iomem *ControllerBaseAddress) 3062bool DAC960_BA_MemoryMailboxStatusAvailableP(void __iomem *ControllerBaseAddress)
3070{ 3063{
3071 DAC960_BA_OutboundDoorBellRegister_T OutboundDoorBellRegister; 3064 DAC960_BA_OutboundDoorBellRegister_T OutboundDoorBellRegister;
3072 OutboundDoorBellRegister.All = 3065 OutboundDoorBellRegister.All =
@@ -3097,7 +3090,7 @@ void DAC960_BA_DisableInterrupts(void __iomem *ControllerBaseAddress)
3097} 3090}
3098 3091
3099static inline 3092static inline
3100boolean DAC960_BA_InterruptsEnabledP(void __iomem *ControllerBaseAddress) 3093bool DAC960_BA_InterruptsEnabledP(void __iomem *ControllerBaseAddress)
3101{ 3094{
3102 DAC960_BA_InterruptMaskRegister_T InterruptMaskRegister; 3095 DAC960_BA_InterruptMaskRegister_T InterruptMaskRegister;
3103 InterruptMaskRegister.All = 3096 InterruptMaskRegister.All =
@@ -3140,7 +3133,7 @@ DAC960_BA_ReadCommandStatus(void __iomem *ControllerBaseAddress)
3140 return readw(ControllerBaseAddress + DAC960_BA_CommandStatusOffset + 2); 3133 return readw(ControllerBaseAddress + DAC960_BA_CommandStatusOffset + 2);
3141} 3134}
3142 3135
3143static inline boolean 3136static inline bool
3144DAC960_BA_ReadErrorStatus(void __iomem *ControllerBaseAddress, 3137DAC960_BA_ReadErrorStatus(void __iomem *ControllerBaseAddress,
3145 unsigned char *ErrorStatus, 3138 unsigned char *ErrorStatus,
3146 unsigned char *Parameter0, 3139 unsigned char *Parameter0,
@@ -3188,16 +3181,16 @@ typedef union DAC960_LP_InboundDoorBellRegister
3188{ 3181{
3189 unsigned char All; 3182 unsigned char All;
3190 struct { 3183 struct {
3191 boolean HardwareMailboxNewCommand:1; /* Bit 0 */ 3184 bool HardwareMailboxNewCommand:1; /* Bit 0 */
3192 boolean AcknowledgeHardwareMailboxStatus:1; /* Bit 1 */ 3185 bool AcknowledgeHardwareMailboxStatus:1; /* Bit 1 */
3193 boolean GenerateInterrupt:1; /* Bit 2 */ 3186 bool GenerateInterrupt:1; /* Bit 2 */
3194 boolean ControllerReset:1; /* Bit 3 */ 3187 bool ControllerReset:1; /* Bit 3 */
3195 boolean MemoryMailboxNewCommand:1; /* Bit 4 */ 3188 bool MemoryMailboxNewCommand:1; /* Bit 4 */
3196 unsigned char :3; /* Bits 5-7 */ 3189 unsigned char :3; /* Bits 5-7 */
3197 } Write; 3190 } Write;
3198 struct { 3191 struct {
3199 boolean HardwareMailboxFull:1; /* Bit 0 */ 3192 bool HardwareMailboxFull:1; /* Bit 0 */
3200 boolean InitializationInProgress:1; /* Bit 1 */ 3193 bool InitializationInProgress:1; /* Bit 1 */
3201 unsigned char :6; /* Bits 2-7 */ 3194 unsigned char :6; /* Bits 2-7 */
3202 } Read; 3195 } Read;
3203} 3196}
@@ -3212,13 +3205,13 @@ typedef union DAC960_LP_OutboundDoorBellRegister
3212{ 3205{
3213 unsigned char All; 3206 unsigned char All;
3214 struct { 3207 struct {
3215 boolean AcknowledgeHardwareMailboxInterrupt:1; /* Bit 0 */ 3208 bool AcknowledgeHardwareMailboxInterrupt:1; /* Bit 0 */
3216 boolean AcknowledgeMemoryMailboxInterrupt:1; /* Bit 1 */ 3209 bool AcknowledgeMemoryMailboxInterrupt:1; /* Bit 1 */
3217 unsigned char :6; /* Bits 2-7 */ 3210 unsigned char :6; /* Bits 2-7 */
3218 } Write; 3211 } Write;
3219 struct { 3212 struct {
3220 boolean HardwareMailboxStatusAvailable:1; /* Bit 0 */ 3213 bool HardwareMailboxStatusAvailable:1; /* Bit 0 */
3221 boolean MemoryMailboxStatusAvailable:1; /* Bit 1 */ 3214 bool MemoryMailboxStatusAvailable:1; /* Bit 1 */
3222 unsigned char :6; /* Bits 2-7 */ 3215 unsigned char :6; /* Bits 2-7 */
3223 } Read; 3216 } Read;
3224} 3217}
@@ -3234,7 +3227,7 @@ typedef union DAC960_LP_InterruptMaskRegister
3234 unsigned char All; 3227 unsigned char All;
3235 struct { 3228 struct {
3236 unsigned int :2; /* Bits 0-1 */ 3229 unsigned int :2; /* Bits 0-1 */
3237 boolean DisableInterrupts:1; /* Bit 2 */ 3230 bool DisableInterrupts:1; /* Bit 2 */
3238 unsigned int :5; /* Bits 3-7 */ 3231 unsigned int :5; /* Bits 3-7 */
3239 } Bits; 3232 } Bits;
3240} 3233}
@@ -3250,7 +3243,7 @@ typedef union DAC960_LP_ErrorStatusRegister
3250 unsigned char All; 3243 unsigned char All;
3251 struct { 3244 struct {
3252 unsigned int :2; /* Bits 0-1 */ 3245 unsigned int :2; /* Bits 0-1 */
3253 boolean ErrorStatusPending:1; /* Bit 2 */ 3246 bool ErrorStatusPending:1; /* Bit 2 */
3254 unsigned int :5; /* Bits 3-7 */ 3247 unsigned int :5; /* Bits 3-7 */
3255 } Bits; 3248 } Bits;
3256} 3249}
@@ -3313,7 +3306,7 @@ void DAC960_LP_MemoryMailboxNewCommand(void __iomem *ControllerBaseAddress)
3313} 3306}
3314 3307
3315static inline 3308static inline
3316boolean DAC960_LP_HardwareMailboxFullP(void __iomem *ControllerBaseAddress) 3309bool DAC960_LP_HardwareMailboxFullP(void __iomem *ControllerBaseAddress)
3317{ 3310{
3318 DAC960_LP_InboundDoorBellRegister_T InboundDoorBellRegister; 3311 DAC960_LP_InboundDoorBellRegister_T InboundDoorBellRegister;
3319 InboundDoorBellRegister.All = 3312 InboundDoorBellRegister.All =
@@ -3322,7 +3315,7 @@ boolean DAC960_LP_HardwareMailboxFullP(void __iomem *ControllerBaseAddress)
3322} 3315}
3323 3316
3324static inline 3317static inline
3325boolean DAC960_LP_InitializationInProgressP(void __iomem *ControllerBaseAddress) 3318bool DAC960_LP_InitializationInProgressP(void __iomem *ControllerBaseAddress)
3326{ 3319{
3327 DAC960_LP_InboundDoorBellRegister_T InboundDoorBellRegister; 3320 DAC960_LP_InboundDoorBellRegister_T InboundDoorBellRegister;
3328 InboundDoorBellRegister.All = 3321 InboundDoorBellRegister.All =
@@ -3362,7 +3355,7 @@ void DAC960_LP_AcknowledgeInterrupt(void __iomem *ControllerBaseAddress)
3362} 3355}
3363 3356
3364static inline 3357static inline
3365boolean DAC960_LP_HardwareMailboxStatusAvailableP(void __iomem *ControllerBaseAddress) 3358bool DAC960_LP_HardwareMailboxStatusAvailableP(void __iomem *ControllerBaseAddress)
3366{ 3359{
3367 DAC960_LP_OutboundDoorBellRegister_T OutboundDoorBellRegister; 3360 DAC960_LP_OutboundDoorBellRegister_T OutboundDoorBellRegister;
3368 OutboundDoorBellRegister.All = 3361 OutboundDoorBellRegister.All =
@@ -3371,7 +3364,7 @@ boolean DAC960_LP_HardwareMailboxStatusAvailableP(void __iomem *ControllerBaseAd
3371} 3364}
3372 3365
3373static inline 3366static inline
3374boolean DAC960_LP_MemoryMailboxStatusAvailableP(void __iomem *ControllerBaseAddress) 3367bool DAC960_LP_MemoryMailboxStatusAvailableP(void __iomem *ControllerBaseAddress)
3375{ 3368{
3376 DAC960_LP_OutboundDoorBellRegister_T OutboundDoorBellRegister; 3369 DAC960_LP_OutboundDoorBellRegister_T OutboundDoorBellRegister;
3377 OutboundDoorBellRegister.All = 3370 OutboundDoorBellRegister.All =
@@ -3400,7 +3393,7 @@ void DAC960_LP_DisableInterrupts(void __iomem *ControllerBaseAddress)
3400} 3393}
3401 3394
3402static inline 3395static inline
3403boolean DAC960_LP_InterruptsEnabledP(void __iomem *ControllerBaseAddress) 3396bool DAC960_LP_InterruptsEnabledP(void __iomem *ControllerBaseAddress)
3404{ 3397{
3405 DAC960_LP_InterruptMaskRegister_T InterruptMaskRegister; 3398 DAC960_LP_InterruptMaskRegister_T InterruptMaskRegister;
3406 InterruptMaskRegister.All = 3399 InterruptMaskRegister.All =
@@ -3442,7 +3435,7 @@ DAC960_LP_ReadCommandStatus(void __iomem *ControllerBaseAddress)
3442 return readw(ControllerBaseAddress + DAC960_LP_CommandStatusOffset + 2); 3435 return readw(ControllerBaseAddress + DAC960_LP_CommandStatusOffset + 2);
3443} 3436}
3444 3437
3445static inline boolean 3438static inline bool
3446DAC960_LP_ReadErrorStatus(void __iomem *ControllerBaseAddress, 3439DAC960_LP_ReadErrorStatus(void __iomem *ControllerBaseAddress,
3447 unsigned char *ErrorStatus, 3440 unsigned char *ErrorStatus,
3448 unsigned char *Parameter0, 3441 unsigned char *Parameter0,
@@ -3502,16 +3495,16 @@ typedef union DAC960_LA_InboundDoorBellRegister
3502{ 3495{
3503 unsigned char All; 3496 unsigned char All;
3504 struct { 3497 struct {
3505 boolean HardwareMailboxNewCommand:1; /* Bit 0 */ 3498 bool HardwareMailboxNewCommand:1; /* Bit 0 */
3506 boolean AcknowledgeHardwareMailboxStatus:1; /* Bit 1 */ 3499 bool AcknowledgeHardwareMailboxStatus:1; /* Bit 1 */
3507 boolean GenerateInterrupt:1; /* Bit 2 */ 3500 bool GenerateInterrupt:1; /* Bit 2 */
3508 boolean ControllerReset:1; /* Bit 3 */ 3501 bool ControllerReset:1; /* Bit 3 */
3509 boolean MemoryMailboxNewCommand:1; /* Bit 4 */ 3502 bool MemoryMailboxNewCommand:1; /* Bit 4 */
3510 unsigned char :3; /* Bits 5-7 */ 3503 unsigned char :3; /* Bits 5-7 */
3511 } Write; 3504 } Write;
3512 struct { 3505 struct {
3513 boolean HardwareMailboxEmpty:1; /* Bit 0 */ 3506 bool HardwareMailboxEmpty:1; /* Bit 0 */
3514 boolean InitializationNotInProgress:1; /* Bit 1 */ 3507 bool InitializationNotInProgress:1; /* Bit 1 */
3515 unsigned char :6; /* Bits 2-7 */ 3508 unsigned char :6; /* Bits 2-7 */
3516 } Read; 3509 } Read;
3517} 3510}
@@ -3526,13 +3519,13 @@ typedef union DAC960_LA_OutboundDoorBellRegister
3526{ 3519{
3527 unsigned char All; 3520 unsigned char All;
3528 struct { 3521 struct {
3529 boolean AcknowledgeHardwareMailboxInterrupt:1; /* Bit 0 */ 3522 bool AcknowledgeHardwareMailboxInterrupt:1; /* Bit 0 */
3530 boolean AcknowledgeMemoryMailboxInterrupt:1; /* Bit 1 */ 3523 bool AcknowledgeMemoryMailboxInterrupt:1; /* Bit 1 */
3531 unsigned char :6; /* Bits 2-7 */ 3524 unsigned char :6; /* Bits 2-7 */
3532 } Write; 3525 } Write;
3533 struct { 3526 struct {
3534 boolean HardwareMailboxStatusAvailable:1; /* Bit 0 */ 3527 bool HardwareMailboxStatusAvailable:1; /* Bit 0 */
3535 boolean MemoryMailboxStatusAvailable:1; /* Bit 1 */ 3528 bool MemoryMailboxStatusAvailable:1; /* Bit 1 */
3536 unsigned char :6; /* Bits 2-7 */ 3529 unsigned char :6; /* Bits 2-7 */
3537 } Read; 3530 } Read;
3538} 3531}
@@ -3548,7 +3541,7 @@ typedef union DAC960_LA_InterruptMaskRegister
3548 unsigned char All; 3541 unsigned char All;
3549 struct { 3542 struct {
3550 unsigned char :2; /* Bits 0-1 */ 3543 unsigned char :2; /* Bits 0-1 */
3551 boolean DisableInterrupts:1; /* Bit 2 */ 3544 bool DisableInterrupts:1; /* Bit 2 */
3552 unsigned char :5; /* Bits 3-7 */ 3545 unsigned char :5; /* Bits 3-7 */
3553 } Bits; 3546 } Bits;
3554} 3547}
@@ -3564,7 +3557,7 @@ typedef union DAC960_LA_ErrorStatusRegister
3564 unsigned char All; 3557 unsigned char All;
3565 struct { 3558 struct {
3566 unsigned int :2; /* Bits 0-1 */ 3559 unsigned int :2; /* Bits 0-1 */
3567 boolean ErrorStatusPending:1; /* Bit 2 */ 3560 bool ErrorStatusPending:1; /* Bit 2 */
3568 unsigned int :5; /* Bits 3-7 */ 3561 unsigned int :5; /* Bits 3-7 */
3569 } Bits; 3562 } Bits;
3570} 3563}
@@ -3627,7 +3620,7 @@ void DAC960_LA_MemoryMailboxNewCommand(void __iomem *ControllerBaseAddress)
3627} 3620}
3628 3621
3629static inline 3622static inline
3630boolean DAC960_LA_HardwareMailboxFullP(void __iomem *ControllerBaseAddress) 3623bool DAC960_LA_HardwareMailboxFullP(void __iomem *ControllerBaseAddress)
3631{ 3624{
3632 DAC960_LA_InboundDoorBellRegister_T InboundDoorBellRegister; 3625 DAC960_LA_InboundDoorBellRegister_T InboundDoorBellRegister;
3633 InboundDoorBellRegister.All = 3626 InboundDoorBellRegister.All =
@@ -3636,7 +3629,7 @@ boolean DAC960_LA_HardwareMailboxFullP(void __iomem *ControllerBaseAddress)
3636} 3629}
3637 3630
3638static inline 3631static inline
3639boolean DAC960_LA_InitializationInProgressP(void __iomem *ControllerBaseAddress) 3632bool DAC960_LA_InitializationInProgressP(void __iomem *ControllerBaseAddress)
3640{ 3633{
3641 DAC960_LA_InboundDoorBellRegister_T InboundDoorBellRegister; 3634 DAC960_LA_InboundDoorBellRegister_T InboundDoorBellRegister;
3642 InboundDoorBellRegister.All = 3635 InboundDoorBellRegister.All =
@@ -3676,7 +3669,7 @@ void DAC960_LA_AcknowledgeInterrupt(void __iomem *ControllerBaseAddress)
3676} 3669}
3677 3670
3678static inline 3671static inline
3679boolean DAC960_LA_HardwareMailboxStatusAvailableP(void __iomem *ControllerBaseAddress) 3672bool DAC960_LA_HardwareMailboxStatusAvailableP(void __iomem *ControllerBaseAddress)
3680{ 3673{
3681 DAC960_LA_OutboundDoorBellRegister_T OutboundDoorBellRegister; 3674 DAC960_LA_OutboundDoorBellRegister_T OutboundDoorBellRegister;
3682 OutboundDoorBellRegister.All = 3675 OutboundDoorBellRegister.All =
@@ -3685,7 +3678,7 @@ boolean DAC960_LA_HardwareMailboxStatusAvailableP(void __iomem *ControllerBaseAd
3685} 3678}
3686 3679
3687static inline 3680static inline
3688boolean DAC960_LA_MemoryMailboxStatusAvailableP(void __iomem *ControllerBaseAddress) 3681bool DAC960_LA_MemoryMailboxStatusAvailableP(void __iomem *ControllerBaseAddress)
3689{ 3682{
3690 DAC960_LA_OutboundDoorBellRegister_T OutboundDoorBellRegister; 3683 DAC960_LA_OutboundDoorBellRegister_T OutboundDoorBellRegister;
3691 OutboundDoorBellRegister.All = 3684 OutboundDoorBellRegister.All =
@@ -3714,7 +3707,7 @@ void DAC960_LA_DisableInterrupts(void __iomem *ControllerBaseAddress)
3714} 3707}
3715 3708
3716static inline 3709static inline
3717boolean DAC960_LA_InterruptsEnabledP(void __iomem *ControllerBaseAddress) 3710bool DAC960_LA_InterruptsEnabledP(void __iomem *ControllerBaseAddress)
3718{ 3711{
3719 DAC960_LA_InterruptMaskRegister_T InterruptMaskRegister; 3712 DAC960_LA_InterruptMaskRegister_T InterruptMaskRegister;
3720 InterruptMaskRegister.All = 3713 InterruptMaskRegister.All =
@@ -3763,7 +3756,7 @@ DAC960_LA_ReadStatusRegister(void __iomem *ControllerBaseAddress)
3763 return readw(ControllerBaseAddress + DAC960_LA_StatusRegisterOffset); 3756 return readw(ControllerBaseAddress + DAC960_LA_StatusRegisterOffset);
3764} 3757}
3765 3758
3766static inline boolean 3759static inline bool
3767DAC960_LA_ReadErrorStatus(void __iomem *ControllerBaseAddress, 3760DAC960_LA_ReadErrorStatus(void __iomem *ControllerBaseAddress,
3768 unsigned char *ErrorStatus, 3761 unsigned char *ErrorStatus,
3769 unsigned char *Parameter0, 3762 unsigned char *Parameter0,
@@ -3822,16 +3815,16 @@ typedef union DAC960_PG_InboundDoorBellRegister
3822{ 3815{
3823 unsigned int All; 3816 unsigned int All;
3824 struct { 3817 struct {
3825 boolean HardwareMailboxNewCommand:1; /* Bit 0 */ 3818 bool HardwareMailboxNewCommand:1; /* Bit 0 */
3826 boolean AcknowledgeHardwareMailboxStatus:1; /* Bit 1 */ 3819 bool AcknowledgeHardwareMailboxStatus:1; /* Bit 1 */
3827 boolean GenerateInterrupt:1; /* Bit 2 */ 3820 bool GenerateInterrupt:1; /* Bit 2 */
3828 boolean ControllerReset:1; /* Bit 3 */ 3821 bool ControllerReset:1; /* Bit 3 */
3829 boolean MemoryMailboxNewCommand:1; /* Bit 4 */ 3822 bool MemoryMailboxNewCommand:1; /* Bit 4 */
3830 unsigned int :27; /* Bits 5-31 */ 3823 unsigned int :27; /* Bits 5-31 */
3831 } Write; 3824 } Write;
3832 struct { 3825 struct {
3833 boolean HardwareMailboxFull:1; /* Bit 0 */ 3826 bool HardwareMailboxFull:1; /* Bit 0 */
3834 boolean InitializationInProgress:1; /* Bit 1 */ 3827 bool InitializationInProgress:1; /* Bit 1 */
3835 unsigned int :30; /* Bits 2-31 */ 3828 unsigned int :30; /* Bits 2-31 */
3836 } Read; 3829 } Read;
3837} 3830}
@@ -3846,13 +3839,13 @@ typedef union DAC960_PG_OutboundDoorBellRegister
3846{ 3839{
3847 unsigned int All; 3840 unsigned int All;
3848 struct { 3841 struct {
3849 boolean AcknowledgeHardwareMailboxInterrupt:1; /* Bit 0 */ 3842 bool AcknowledgeHardwareMailboxInterrupt:1; /* Bit 0 */
3850 boolean AcknowledgeMemoryMailboxInterrupt:1; /* Bit 1 */ 3843 bool AcknowledgeMemoryMailboxInterrupt:1; /* Bit 1 */
3851 unsigned int :30; /* Bits 2-31 */ 3844 unsigned int :30; /* Bits 2-31 */
3852 } Write; 3845 } Write;
3853 struct { 3846 struct {
3854 boolean HardwareMailboxStatusAvailable:1; /* Bit 0 */ 3847 bool HardwareMailboxStatusAvailable:1; /* Bit 0 */
3855 boolean MemoryMailboxStatusAvailable:1; /* Bit 1 */ 3848 bool MemoryMailboxStatusAvailable:1; /* Bit 1 */
3856 unsigned int :30; /* Bits 2-31 */ 3849 unsigned int :30; /* Bits 2-31 */
3857 } Read; 3850 } Read;
3858} 3851}
@@ -3868,7 +3861,7 @@ typedef union DAC960_PG_InterruptMaskRegister
3868 unsigned int All; 3861 unsigned int All;
3869 struct { 3862 struct {
3870 unsigned int MessageUnitInterruptMask1:2; /* Bits 0-1 */ 3863 unsigned int MessageUnitInterruptMask1:2; /* Bits 0-1 */
3871 boolean DisableInterrupts:1; /* Bit 2 */ 3864 bool DisableInterrupts:1; /* Bit 2 */
3872 unsigned int MessageUnitInterruptMask2:5; /* Bits 3-7 */ 3865 unsigned int MessageUnitInterruptMask2:5; /* Bits 3-7 */
3873 unsigned int Reserved0:24; /* Bits 8-31 */ 3866 unsigned int Reserved0:24; /* Bits 8-31 */
3874 } Bits; 3867 } Bits;
@@ -3885,7 +3878,7 @@ typedef union DAC960_PG_ErrorStatusRegister
3885 unsigned char All; 3878 unsigned char All;
3886 struct { 3879 struct {
3887 unsigned int :2; /* Bits 0-1 */ 3880 unsigned int :2; /* Bits 0-1 */
3888 boolean ErrorStatusPending:1; /* Bit 2 */ 3881 bool ErrorStatusPending:1; /* Bit 2 */
3889 unsigned int :5; /* Bits 3-7 */ 3882 unsigned int :5; /* Bits 3-7 */
3890 } Bits; 3883 } Bits;
3891} 3884}
@@ -3948,7 +3941,7 @@ void DAC960_PG_MemoryMailboxNewCommand(void __iomem *ControllerBaseAddress)
3948} 3941}
3949 3942
3950static inline 3943static inline
3951boolean DAC960_PG_HardwareMailboxFullP(void __iomem *ControllerBaseAddress) 3944bool DAC960_PG_HardwareMailboxFullP(void __iomem *ControllerBaseAddress)
3952{ 3945{
3953 DAC960_PG_InboundDoorBellRegister_T InboundDoorBellRegister; 3946 DAC960_PG_InboundDoorBellRegister_T InboundDoorBellRegister;
3954 InboundDoorBellRegister.All = 3947 InboundDoorBellRegister.All =
@@ -3957,7 +3950,7 @@ boolean DAC960_PG_HardwareMailboxFullP(void __iomem *ControllerBaseAddress)
3957} 3950}
3958 3951
3959static inline 3952static inline
3960boolean DAC960_PG_InitializationInProgressP(void __iomem *ControllerBaseAddress) 3953bool DAC960_PG_InitializationInProgressP(void __iomem *ControllerBaseAddress)
3961{ 3954{
3962 DAC960_PG_InboundDoorBellRegister_T InboundDoorBellRegister; 3955 DAC960_PG_InboundDoorBellRegister_T InboundDoorBellRegister;
3963 InboundDoorBellRegister.All = 3956 InboundDoorBellRegister.All =
@@ -3997,7 +3990,7 @@ void DAC960_PG_AcknowledgeInterrupt(void __iomem *ControllerBaseAddress)
3997} 3990}
3998 3991
3999static inline 3992static inline
4000boolean DAC960_PG_HardwareMailboxStatusAvailableP(void __iomem *ControllerBaseAddress) 3993bool DAC960_PG_HardwareMailboxStatusAvailableP(void __iomem *ControllerBaseAddress)
4001{ 3994{
4002 DAC960_PG_OutboundDoorBellRegister_T OutboundDoorBellRegister; 3995 DAC960_PG_OutboundDoorBellRegister_T OutboundDoorBellRegister;
4003 OutboundDoorBellRegister.All = 3996 OutboundDoorBellRegister.All =
@@ -4006,7 +3999,7 @@ boolean DAC960_PG_HardwareMailboxStatusAvailableP(void __iomem *ControllerBaseAd
4006} 3999}
4007 4000
4008static inline 4001static inline
4009boolean DAC960_PG_MemoryMailboxStatusAvailableP(void __iomem *ControllerBaseAddress) 4002bool DAC960_PG_MemoryMailboxStatusAvailableP(void __iomem *ControllerBaseAddress)
4010{ 4003{
4011 DAC960_PG_OutboundDoorBellRegister_T OutboundDoorBellRegister; 4004 DAC960_PG_OutboundDoorBellRegister_T OutboundDoorBellRegister;
4012 OutboundDoorBellRegister.All = 4005 OutboundDoorBellRegister.All =
@@ -4039,7 +4032,7 @@ void DAC960_PG_DisableInterrupts(void __iomem *ControllerBaseAddress)
4039} 4032}
4040 4033
4041static inline 4034static inline
4042boolean DAC960_PG_InterruptsEnabledP(void __iomem *ControllerBaseAddress) 4035bool DAC960_PG_InterruptsEnabledP(void __iomem *ControllerBaseAddress)
4043{ 4036{
4044 DAC960_PG_InterruptMaskRegister_T InterruptMaskRegister; 4037 DAC960_PG_InterruptMaskRegister_T InterruptMaskRegister;
4045 InterruptMaskRegister.All = 4038 InterruptMaskRegister.All =
@@ -4088,7 +4081,7 @@ DAC960_PG_ReadStatusRegister(void __iomem *ControllerBaseAddress)
4088 return readw(ControllerBaseAddress + DAC960_PG_StatusRegisterOffset); 4081 return readw(ControllerBaseAddress + DAC960_PG_StatusRegisterOffset);
4089} 4082}
4090 4083
4091static inline boolean 4084static inline bool
4092DAC960_PG_ReadErrorStatus(void __iomem *ControllerBaseAddress, 4085DAC960_PG_ReadErrorStatus(void __iomem *ControllerBaseAddress,
4093 unsigned char *ErrorStatus, 4086 unsigned char *ErrorStatus,
4094 unsigned char *Parameter0, 4087 unsigned char *Parameter0,
@@ -4147,15 +4140,15 @@ typedef union DAC960_PD_InboundDoorBellRegister
4147{ 4140{
4148 unsigned char All; 4141 unsigned char All;
4149 struct { 4142 struct {
4150 boolean NewCommand:1; /* Bit 0 */ 4143 bool NewCommand:1; /* Bit 0 */
4151 boolean AcknowledgeStatus:1; /* Bit 1 */ 4144 bool AcknowledgeStatus:1; /* Bit 1 */
4152 boolean GenerateInterrupt:1; /* Bit 2 */ 4145 bool GenerateInterrupt:1; /* Bit 2 */
4153 boolean ControllerReset:1; /* Bit 3 */ 4146 bool ControllerReset:1; /* Bit 3 */
4154 unsigned char :4; /* Bits 4-7 */ 4147 unsigned char :4; /* Bits 4-7 */
4155 } Write; 4148 } Write;
4156 struct { 4149 struct {
4157 boolean MailboxFull:1; /* Bit 0 */ 4150 bool MailboxFull:1; /* Bit 0 */
4158 boolean InitializationInProgress:1; /* Bit 1 */ 4151 bool InitializationInProgress:1; /* Bit 1 */
4159 unsigned char :6; /* Bits 2-7 */ 4152 unsigned char :6; /* Bits 2-7 */
4160 } Read; 4153 } Read;
4161} 4154}
@@ -4170,11 +4163,11 @@ typedef union DAC960_PD_OutboundDoorBellRegister
4170{ 4163{
4171 unsigned char All; 4164 unsigned char All;
4172 struct { 4165 struct {
4173 boolean AcknowledgeInterrupt:1; /* Bit 0 */ 4166 bool AcknowledgeInterrupt:1; /* Bit 0 */
4174 unsigned char :7; /* Bits 1-7 */ 4167 unsigned char :7; /* Bits 1-7 */
4175 } Write; 4168 } Write;
4176 struct { 4169 struct {
4177 boolean StatusAvailable:1; /* Bit 0 */ 4170 bool StatusAvailable:1; /* Bit 0 */
4178 unsigned char :7; /* Bits 1-7 */ 4171 unsigned char :7; /* Bits 1-7 */
4179 } Read; 4172 } Read;
4180} 4173}
@@ -4189,7 +4182,7 @@ typedef union DAC960_PD_InterruptEnableRegister
4189{ 4182{
4190 unsigned char All; 4183 unsigned char All;
4191 struct { 4184 struct {
4192 boolean EnableInterrupts:1; /* Bit 0 */ 4185 bool EnableInterrupts:1; /* Bit 0 */
4193 unsigned char :7; /* Bits 1-7 */ 4186 unsigned char :7; /* Bits 1-7 */
4194 } Bits; 4187 } Bits;
4195} 4188}
@@ -4205,7 +4198,7 @@ typedef union DAC960_PD_ErrorStatusRegister
4205 unsigned char All; 4198 unsigned char All;
4206 struct { 4199 struct {
4207 unsigned int :2; /* Bits 0-1 */ 4200 unsigned int :2; /* Bits 0-1 */
4208 boolean ErrorStatusPending:1; /* Bit 2 */ 4201 bool ErrorStatusPending:1; /* Bit 2 */
4209 unsigned int :5; /* Bits 3-7 */ 4202 unsigned int :5; /* Bits 3-7 */
4210 } Bits; 4203 } Bits;
4211} 4204}
@@ -4258,7 +4251,7 @@ void DAC960_PD_ControllerReset(void __iomem *ControllerBaseAddress)
4258} 4251}
4259 4252
4260static inline 4253static inline
4261boolean DAC960_PD_MailboxFullP(void __iomem *ControllerBaseAddress) 4254bool DAC960_PD_MailboxFullP(void __iomem *ControllerBaseAddress)
4262{ 4255{
4263 DAC960_PD_InboundDoorBellRegister_T InboundDoorBellRegister; 4256 DAC960_PD_InboundDoorBellRegister_T InboundDoorBellRegister;
4264 InboundDoorBellRegister.All = 4257 InboundDoorBellRegister.All =
@@ -4267,7 +4260,7 @@ boolean DAC960_PD_MailboxFullP(void __iomem *ControllerBaseAddress)
4267} 4260}
4268 4261
4269static inline 4262static inline
4270boolean DAC960_PD_InitializationInProgressP(void __iomem *ControllerBaseAddress) 4263bool DAC960_PD_InitializationInProgressP(void __iomem *ControllerBaseAddress)
4271{ 4264{
4272 DAC960_PD_InboundDoorBellRegister_T InboundDoorBellRegister; 4265 DAC960_PD_InboundDoorBellRegister_T InboundDoorBellRegister;
4273 InboundDoorBellRegister.All = 4266 InboundDoorBellRegister.All =
@@ -4286,7 +4279,7 @@ void DAC960_PD_AcknowledgeInterrupt(void __iomem *ControllerBaseAddress)
4286} 4279}
4287 4280
4288static inline 4281static inline
4289boolean DAC960_PD_StatusAvailableP(void __iomem *ControllerBaseAddress) 4282bool DAC960_PD_StatusAvailableP(void __iomem *ControllerBaseAddress)
4290{ 4283{
4291 DAC960_PD_OutboundDoorBellRegister_T OutboundDoorBellRegister; 4284 DAC960_PD_OutboundDoorBellRegister_T OutboundDoorBellRegister;
4292 OutboundDoorBellRegister.All = 4285 OutboundDoorBellRegister.All =
@@ -4315,7 +4308,7 @@ void DAC960_PD_DisableInterrupts(void __iomem *ControllerBaseAddress)
4315} 4308}
4316 4309
4317static inline 4310static inline
4318boolean DAC960_PD_InterruptsEnabledP(void __iomem *ControllerBaseAddress) 4311bool DAC960_PD_InterruptsEnabledP(void __iomem *ControllerBaseAddress)
4319{ 4312{
4320 DAC960_PD_InterruptEnableRegister_T InterruptEnableRegister; 4313 DAC960_PD_InterruptEnableRegister_T InterruptEnableRegister;
4321 InterruptEnableRegister.All = 4314 InterruptEnableRegister.All =
@@ -4350,7 +4343,7 @@ DAC960_PD_ReadStatusRegister(void __iomem *ControllerBaseAddress)
4350 return readw(ControllerBaseAddress + DAC960_PD_StatusRegisterOffset); 4343 return readw(ControllerBaseAddress + DAC960_PD_StatusRegisterOffset);
4351} 4344}
4352 4345
4353static inline boolean 4346static inline bool
4354DAC960_PD_ReadErrorStatus(void __iomem *ControllerBaseAddress, 4347DAC960_PD_ReadErrorStatus(void __iomem *ControllerBaseAddress,
4355 unsigned char *ErrorStatus, 4348 unsigned char *ErrorStatus,
4356 unsigned char *Parameter0, 4349 unsigned char *Parameter0,
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-08 10:54:23 -0500