litmus-rt.git - The LITMUS^RT kernel.

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The LITMUS^RT kernel.

Bjoern Brandenburg

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path: root/drivers/base/node.c

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author	Salyzyn, Mark <mark_salyzyn@adaptec.com>	2005-12-17 22:26:30 -0500
committer	Linus Torvalds <torvalds@g5.osdl.org>	2005-12-18 14:19:44 -0500
commit	e5508c13ac25b07585229b144a45cf64a990171e (patch)
tree	6c2de87941b7dd81a6c36ca73d517165629c9147 /drivers/base/node.c
parent	87d47d0547631e059c308b392cd2423fe9248c93 (diff)

[PATCH] dpt_i2o fix for deadlock condition

Miquel van Smoorenburg <miquels@cistron.nl> forwarded me this fix to resolve a deadlock condition that occurs due to the API change in 2.6.13+ kernels dropping the host locking when entering the error handling. They all end up calling adpt_i2o_post_wait(), which if you call it unlocked, might return with host_lock locked anyway and that causes a deadlock. Signed-off-by: Mark Salyzyn <aacraid@adaptec.com> Cc: James Bottomley <James.Bottomley@steeleye.com> Cc: <stable@kernel.org> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>

Diffstat (limited to 'drivers/base/node.c')

0 files changed, 0 insertions, 0 deletions

n> #define ATMEL_US_CHRL_5 (0 << 6) #define ATMEL_US_CHRL_6 (1 << 6) #define ATMEL_US_CHRL_7 (2 << 6) #define ATMEL_US_CHRL_8 (3 << 6) #define ATMEL_US_SYNC (1 << 8) /* Synchronous Mode Select */ #define ATMEL_US_PAR (7 << 9) /* Parity Type */ #define ATMEL_US_PAR_EVEN (0 << 9) #define ATMEL_US_PAR_ODD (1 << 9) #define ATMEL_US_PAR_SPACE (2 << 9) #define ATMEL_US_PAR_MARK (3 << 9) #define ATMEL_US_PAR_NONE (4 << 9) #define ATMEL_US_PAR_MULTI_DROP (6 << 9) #define ATMEL_US_NBSTOP (3 << 12) /* Number of Stop Bits */ #define ATMEL_US_NBSTOP_1 (0 << 12) #define ATMEL_US_NBSTOP_1_5 (1 << 12) #define ATMEL_US_NBSTOP_2 (2 << 12) #define ATMEL_US_CHMODE (3 << 14) /* Channel Mode */ #define ATMEL_US_CHMODE_NORMAL (0 << 14) #define ATMEL_US_CHMODE_ECHO (1 << 14) #define ATMEL_US_CHMODE_LOC_LOOP (2 << 14) #define ATMEL_US_CHMODE_REM_LOOP (3 << 14) #define ATMEL_US_MSBF (1 << 16) /* Bit Order */ #define ATMEL_US_MODE9 (1 << 17) /* 9-bit Character Length */ #define ATMEL_US_CLKO (1 << 18) /* Clock Output Select */ #define ATMEL_US_OVER (1 << 19) /* Oversampling Mode */ #define ATMEL_US_INACK (1 << 20) /* Inhibit Non Acknowledge */ #define ATMEL_US_DSNACK (1 << 21) /* Disable Successive NACK */ #define ATMEL_US_MAX_ITER (7 << 24) /* Max Iterations */ #define ATMEL_US_FILTER (1 << 28) /* Infrared Receive Line Filter */ #define ATMEL_US_IER 0x08 /* Interrupt Enable Register */ #define ATMEL_US_RXRDY (1 << 0) /* Receiver Ready */ #define ATMEL_US_TXRDY (1 << 1) /* Transmitter Ready */ #define ATMEL_US_RXBRK (1 << 2) /* Break Received / End of Break */ #define ATMEL_US_ENDRX (1 << 3) /* End of Receiver Transfer */ #define ATMEL_US_ENDTX (1 << 4) /* End of Transmitter Transfer */ #define ATMEL_US_OVRE (1 << 5) /* Overrun Error */ #define ATMEL_US_FRAME (1 << 6) /* Framing Error */ #define ATMEL_US_PARE (1 << 7) /* Parity Error */ #define ATMEL_US_TIMEOUT (1 << 8) /* Receiver Time-out */ #define ATMEL_US_TXEMPTY (1 << 9) /* Transmitter Empty */ #define ATMEL_US_ITERATION (1 << 10) /* Max number of Repetitions Reached */ #define ATMEL_US_TXBUFE (1 << 11) /* Transmission Buffer Empty */ #define ATMEL_US_RXBUFF (1 << 12) /* Reception Buffer Full */ #define ATMEL_US_NACK (1 << 13) /* Non Acknowledge */ #define ATMEL_US_RIIC (1 << 16) /* Ring Indicator Input Change [AT91RM9200 only] */ #define ATMEL_US_DSRIC (1 << 17) /* Data Set Ready Input Change [AT91RM9200 only] */ #define ATMEL_US_DCDIC (1 << 18) /* Data Carrier Detect Input Change [AT91RM9200 only] */ #define ATMEL_US_CTSIC (1 << 19) /* Clear to Send Input Change */ #define ATMEL_US_RI (1 << 20) /* RI */ #define ATMEL_US_DSR (1 << 21) /* DSR */ #define ATMEL_US_DCD (1 << 22) /* DCD */ #define ATMEL_US_CTS (1 << 23) /* CTS */ #define ATMEL_US_IDR 0x0c /* Interrupt Disable Register */ #define ATMEL_US_IMR 0x10 /* Interrupt Mask Register */ #define ATMEL_US_CSR 0x14 /* Channel Status Register */ #define ATMEL_US_RHR 0x18 /* Receiver Holding Register */ #define ATMEL_US_THR 0x1c /* Transmitter Holding Register */ #define ATMEL_US_SYNH (1 << 15) /* Transmit/Receive Sync [AT91SAM9261 only] */ #define ATMEL_US_BRGR 0x20 /* Baud Rate Generator Register */ #define ATMEL_US_CD (0xffff << 0) /* Clock Divider */ #define ATMEL_US_RTOR 0x24 /* Receiver Time-out Register */ #define ATMEL_US_TO (0xffff << 0) /* Time-out Value */ #define ATMEL_US_TTGR 0x28 /* Transmitter Timeguard Register */ #define ATMEL_US_TG (0xff << 0) /* Timeguard Value */ #define ATMEL_US_FIDI 0x40 /* FI DI Ratio Register */ #define ATMEL_US_NER 0x44 /* Number of Errors Register */ #define ATMEL_US_IF 0x4c /* IrDA Filter Register */ #endif