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authorchas williams - CONTRACTOR <chas@cmf.nrl.navy.mil>2010-05-29 05:03:44 -0400
committerDavid S. Miller <davem@davemloft.net>2010-05-31 03:27:46 -0400
commit098fde114bf6655f4b75d71dbea208d039fc1de3 (patch)
treeea889dae935d8ca04508694929a0d17fde42ac1a /drivers/atm
parent741a00be1f6bfa027225f44703ab72a741b757b7 (diff)
atm: [nicstar] reformatted with Lindent
Signed-off-by: Chas Williams - CONTRACTOR <chas@cmf.nrl.navy.mil> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/atm')
-rw-r--r--drivers/atm/nicstar.c5115
-rw-r--r--drivers/atm/nicstar.h578
-rw-r--r--drivers/atm/nicstarmac.c364
3 files changed, 2888 insertions, 3169 deletions
diff --git a/drivers/atm/nicstar.c b/drivers/atm/nicstar.c
index b7473a6110a7..a07b6b7fc7d8 100644
--- a/drivers/atm/nicstar.c
+++ b/drivers/atm/nicstar.c
@@ -1,5 +1,4 @@
1/****************************************************************************** 1/*
2 *
3 * nicstar.c 2 * nicstar.c
4 * 3 *
5 * Device driver supporting CBR for IDT 77201/77211 "NICStAR" based cards. 4 * Device driver supporting CBR for IDT 77201/77211 "NICStAR" based cards.
@@ -16,12 +15,10 @@
16 * 15 *
17 * 16 *
18 * (C) INESC 1999 17 * (C) INESC 1999
19 * 18 */
20 *
21 ******************************************************************************/
22
23 19
24/**** IMPORTANT INFORMATION *************************************************** 20/*
21 * IMPORTANT INFORMATION
25 * 22 *
26 * There are currently three types of spinlocks: 23 * There are currently three types of spinlocks:
27 * 24 *
@@ -31,9 +28,9 @@
31 * 28 *
32 * These must NEVER be grabbed in reverse order. 29 * These must NEVER be grabbed in reverse order.
33 * 30 *
34 ******************************************************************************/ 31 */
35 32
36/* Header files ***************************************************************/ 33/* Header files */
37 34
38#include <linux/module.h> 35#include <linux/module.h>
39#include <linux/kernel.h> 36#include <linux/kernel.h>
@@ -62,15 +59,14 @@
62#endif /* CONFIG_ATM_NICSTAR_USE_IDT77105 */ 59#endif /* CONFIG_ATM_NICSTAR_USE_IDT77105 */
63 60
64#if BITS_PER_LONG != 32 61#if BITS_PER_LONG != 32
65# error FIXME: this driver requires a 32-bit platform 62# error FIXME: this driver requires a 32-bit platform
66#endif 63#endif
67 64
68/* Additional code ************************************************************/ 65/* Additional code */
69 66
70#include "nicstarmac.c" 67#include "nicstarmac.c"
71 68
72 69/* Configurable parameters */
73/* Configurable parameters ****************************************************/
74 70
75#undef PHY_LOOPBACK 71#undef PHY_LOOPBACK
76#undef TX_DEBUG 72#undef TX_DEBUG
@@ -78,11 +74,10 @@
78#undef GENERAL_DEBUG 74#undef GENERAL_DEBUG
79#undef EXTRA_DEBUG 75#undef EXTRA_DEBUG
80 76
81#undef NS_USE_DESTRUCTORS /* For now keep this undefined unless you know 77#undef NS_USE_DESTRUCTORS /* For now keep this undefined unless you know
82 you're going to use only raw ATM */ 78 you're going to use only raw ATM */
83
84 79
85/* Do not touch these *********************************************************/ 80/* Do not touch these */
86 81
87#ifdef TX_DEBUG 82#ifdef TX_DEBUG
88#define TXPRINTK(args...) printk(args) 83#define TXPRINTK(args...) printk(args)
@@ -108,8 +103,7 @@
108#define XPRINTK(args...) 103#define XPRINTK(args...)
109#endif /* EXTRA_DEBUG */ 104#endif /* EXTRA_DEBUG */
110 105
111 106/* Macros */
112/* Macros *********************************************************************/
113 107
114#define CMD_BUSY(card) (readl((card)->membase + STAT) & NS_STAT_CMDBZ) 108#define CMD_BUSY(card) (readl((card)->membase + STAT) & NS_STAT_CMDBZ)
115 109
@@ -126,2890 +120,2711 @@
126#define ATM_SKB(s) (&(s)->atm) 120#define ATM_SKB(s) (&(s)->atm)
127#endif 121#endif
128 122
123/* Function declarations */
129 124
130/* Function declarations ******************************************************/ 125static u32 ns_read_sram(ns_dev * card, u32 sram_address);
131 126static void ns_write_sram(ns_dev * card, u32 sram_address, u32 * value,
132static u32 ns_read_sram(ns_dev *card, u32 sram_address); 127 int count);
133static void ns_write_sram(ns_dev *card, u32 sram_address, u32 *value, int count);
134static int __devinit ns_init_card(int i, struct pci_dev *pcidev); 128static int __devinit ns_init_card(int i, struct pci_dev *pcidev);
135static void __devinit ns_init_card_error(ns_dev *card, int error); 129static void __devinit ns_init_card_error(ns_dev * card, int error);
136static scq_info *get_scq(int size, u32 scd); 130static scq_info *get_scq(int size, u32 scd);
137static void free_scq(scq_info *scq, struct atm_vcc *vcc); 131static void free_scq(scq_info * scq, struct atm_vcc *vcc);
138static void push_rxbufs(ns_dev *, struct sk_buff *); 132static void push_rxbufs(ns_dev *, struct sk_buff *);
139static irqreturn_t ns_irq_handler(int irq, void *dev_id); 133static irqreturn_t ns_irq_handler(int irq, void *dev_id);
140static int ns_open(struct atm_vcc *vcc); 134static int ns_open(struct atm_vcc *vcc);
141static void ns_close(struct atm_vcc *vcc); 135static void ns_close(struct atm_vcc *vcc);
142static void fill_tst(ns_dev *card, int n, vc_map *vc); 136static void fill_tst(ns_dev * card, int n, vc_map * vc);
143static int ns_send(struct atm_vcc *vcc, struct sk_buff *skb); 137static int ns_send(struct atm_vcc *vcc, struct sk_buff *skb);
144static int push_scqe(ns_dev *card, vc_map *vc, scq_info *scq, ns_scqe *tbd, 138static int push_scqe(ns_dev * card, vc_map * vc, scq_info * scq, ns_scqe * tbd,
145 struct sk_buff *skb); 139 struct sk_buff *skb);
146static void process_tsq(ns_dev *card); 140static void process_tsq(ns_dev * card);
147static void drain_scq(ns_dev *card, scq_info *scq, int pos); 141static void drain_scq(ns_dev * card, scq_info * scq, int pos);
148static void process_rsq(ns_dev *card); 142static void process_rsq(ns_dev * card);
149static void dequeue_rx(ns_dev *card, ns_rsqe *rsqe); 143static void dequeue_rx(ns_dev * card, ns_rsqe * rsqe);
150#ifdef NS_USE_DESTRUCTORS 144#ifdef NS_USE_DESTRUCTORS
151static void ns_sb_destructor(struct sk_buff *sb); 145static void ns_sb_destructor(struct sk_buff *sb);
152static void ns_lb_destructor(struct sk_buff *lb); 146static void ns_lb_destructor(struct sk_buff *lb);
153static void ns_hb_destructor(struct sk_buff *hb); 147static void ns_hb_destructor(struct sk_buff *hb);
154#endif /* NS_USE_DESTRUCTORS */ 148#endif /* NS_USE_DESTRUCTORS */
155static void recycle_rx_buf(ns_dev *card, struct sk_buff *skb); 149static void recycle_rx_buf(ns_dev * card, struct sk_buff *skb);
156static void recycle_iovec_rx_bufs(ns_dev *card, struct iovec *iov, int count); 150static void recycle_iovec_rx_bufs(ns_dev * card, struct iovec *iov, int count);
157static void recycle_iov_buf(ns_dev *card, struct sk_buff *iovb); 151static void recycle_iov_buf(ns_dev * card, struct sk_buff *iovb);
158static void dequeue_sm_buf(ns_dev *card, struct sk_buff *sb); 152static void dequeue_sm_buf(ns_dev * card, struct sk_buff *sb);
159static void dequeue_lg_buf(ns_dev *card, struct sk_buff *lb); 153static void dequeue_lg_buf(ns_dev * card, struct sk_buff *lb);
160static int ns_proc_read(struct atm_dev *dev, loff_t *pos, char *page); 154static int ns_proc_read(struct atm_dev *dev, loff_t * pos, char *page);
161static int ns_ioctl(struct atm_dev *dev, unsigned int cmd, void __user *arg); 155static int ns_ioctl(struct atm_dev *dev, unsigned int cmd, void __user * arg);
162static void which_list(ns_dev *card, struct sk_buff *skb); 156static void which_list(ns_dev * card, struct sk_buff *skb);
163static void ns_poll(unsigned long arg); 157static void ns_poll(unsigned long arg);
164static int ns_parse_mac(char *mac, unsigned char *esi); 158static int ns_parse_mac(char *mac, unsigned char *esi);
165static short ns_h2i(char c); 159static short ns_h2i(char c);
166static void ns_phy_put(struct atm_dev *dev, unsigned char value, 160static void ns_phy_put(struct atm_dev *dev, unsigned char value,
167 unsigned long addr); 161 unsigned long addr);
168static unsigned char ns_phy_get(struct atm_dev *dev, unsigned long addr); 162static unsigned char ns_phy_get(struct atm_dev *dev, unsigned long addr);
169 163
170 164/* Global variables */
171
172/* Global variables ***********************************************************/
173 165
174static struct ns_dev *cards[NS_MAX_CARDS]; 166static struct ns_dev *cards[NS_MAX_CARDS];
175static unsigned num_cards; 167static unsigned num_cards;
176static struct atmdev_ops atm_ops = 168static struct atmdev_ops atm_ops = {
177{ 169 .open = ns_open,
178 .open = ns_open, 170 .close = ns_close,
179 .close = ns_close, 171 .ioctl = ns_ioctl,
180 .ioctl = ns_ioctl, 172 .send = ns_send,
181 .send = ns_send, 173 .phy_put = ns_phy_put,
182 .phy_put = ns_phy_put, 174 .phy_get = ns_phy_get,
183 .phy_get = ns_phy_get, 175 .proc_read = ns_proc_read,
184 .proc_read = ns_proc_read, 176 .owner = THIS_MODULE,
185 .owner = THIS_MODULE,
186}; 177};
178
187static struct timer_list ns_timer; 179static struct timer_list ns_timer;
188static char *mac[NS_MAX_CARDS]; 180static char *mac[NS_MAX_CARDS];
189module_param_array(mac, charp, NULL, 0); 181module_param_array(mac, charp, NULL, 0);
190MODULE_LICENSE("GPL"); 182MODULE_LICENSE("GPL");
191 183
192 184/* Functions */
193/* Functions*******************************************************************/
194 185
195static int __devinit nicstar_init_one(struct pci_dev *pcidev, 186static int __devinit nicstar_init_one(struct pci_dev *pcidev,
196 const struct pci_device_id *ent) 187 const struct pci_device_id *ent)
197{ 188{
198 static int index = -1; 189 static int index = -1;
199 unsigned int error; 190 unsigned int error;
200 191
201 index++; 192 index++;
202 cards[index] = NULL; 193 cards[index] = NULL;
203 194
204 error = ns_init_card(index, pcidev); 195 error = ns_init_card(index, pcidev);
205 if (error) { 196 if (error) {
206 cards[index--] = NULL; /* don't increment index */ 197 cards[index--] = NULL; /* don't increment index */
207 goto err_out; 198 goto err_out;
208 } 199 }
209 200
210 return 0; 201 return 0;
211err_out: 202err_out:
212 return -ENODEV; 203 return -ENODEV;
213} 204}
214 205
215
216
217static void __devexit nicstar_remove_one(struct pci_dev *pcidev) 206static void __devexit nicstar_remove_one(struct pci_dev *pcidev)
218{ 207{
219 int i, j; 208 int i, j;
220 ns_dev *card = pci_get_drvdata(pcidev); 209 ns_dev *card = pci_get_drvdata(pcidev);
221 struct sk_buff *hb; 210 struct sk_buff *hb;
222 struct sk_buff *iovb; 211 struct sk_buff *iovb;
223 struct sk_buff *lb; 212 struct sk_buff *lb;
224 struct sk_buff *sb; 213 struct sk_buff *sb;
225 214
226 i = card->index; 215 i = card->index;
227 216
228 if (cards[i] == NULL) 217 if (cards[i] == NULL)
229 return; 218 return;
230 219
231 if (card->atmdev->phy && card->atmdev->phy->stop) 220 if (card->atmdev->phy && card->atmdev->phy->stop)
232 card->atmdev->phy->stop(card->atmdev); 221 card->atmdev->phy->stop(card->atmdev);
233 222
234 /* Stop everything */ 223 /* Stop everything */
235 writel(0x00000000, card->membase + CFG); 224 writel(0x00000000, card->membase + CFG);
236 225
237 /* De-register device */ 226 /* De-register device */
238 atm_dev_deregister(card->atmdev); 227 atm_dev_deregister(card->atmdev);
239 228
240 /* Disable PCI device */ 229 /* Disable PCI device */
241 pci_disable_device(pcidev); 230 pci_disable_device(pcidev);
242 231
243 /* Free up resources */ 232 /* Free up resources */
244 j = 0; 233 j = 0;
245 PRINTK("nicstar%d: freeing %d huge buffers.\n", i, card->hbpool.count); 234 PRINTK("nicstar%d: freeing %d huge buffers.\n", i, card->hbpool.count);
246 while ((hb = skb_dequeue(&card->hbpool.queue)) != NULL) 235 while ((hb = skb_dequeue(&card->hbpool.queue)) != NULL) {
247 { 236 dev_kfree_skb_any(hb);
248 dev_kfree_skb_any(hb); 237 j++;
249 j++; 238 }
250 } 239 PRINTK("nicstar%d: %d huge buffers freed.\n", i, j);
251 PRINTK("nicstar%d: %d huge buffers freed.\n", i, j); 240 j = 0;
252 j = 0; 241 PRINTK("nicstar%d: freeing %d iovec buffers.\n", i,
253 PRINTK("nicstar%d: freeing %d iovec buffers.\n", i, card->iovpool.count); 242 card->iovpool.count);
254 while ((iovb = skb_dequeue(&card->iovpool.queue)) != NULL) 243 while ((iovb = skb_dequeue(&card->iovpool.queue)) != NULL) {
255 { 244 dev_kfree_skb_any(iovb);
256 dev_kfree_skb_any(iovb); 245 j++;
257 j++; 246 }
258 } 247 PRINTK("nicstar%d: %d iovec buffers freed.\n", i, j);
259 PRINTK("nicstar%d: %d iovec buffers freed.\n", i, j); 248 while ((lb = skb_dequeue(&card->lbpool.queue)) != NULL)
260 while ((lb = skb_dequeue(&card->lbpool.queue)) != NULL) 249 dev_kfree_skb_any(lb);
261 dev_kfree_skb_any(lb); 250 while ((sb = skb_dequeue(&card->sbpool.queue)) != NULL)
262 while ((sb = skb_dequeue(&card->sbpool.queue)) != NULL) 251 dev_kfree_skb_any(sb);
263 dev_kfree_skb_any(sb); 252 free_scq(card->scq0, NULL);
264 free_scq(card->scq0, NULL); 253 for (j = 0; j < NS_FRSCD_NUM; j++) {
265 for (j = 0; j < NS_FRSCD_NUM; j++) 254 if (card->scd2vc[j] != NULL)
266 { 255 free_scq(card->scd2vc[j]->scq, card->scd2vc[j]->tx_vcc);
267 if (card->scd2vc[j] != NULL) 256 }
268 free_scq(card->scd2vc[j]->scq, card->scd2vc[j]->tx_vcc); 257 kfree(card->rsq.org);
269 } 258 kfree(card->tsq.org);
270 kfree(card->rsq.org); 259 free_irq(card->pcidev->irq, card);
271 kfree(card->tsq.org); 260 iounmap(card->membase);
272 free_irq(card->pcidev->irq, card); 261 kfree(card);
273 iounmap(card->membase);
274 kfree(card);
275} 262}
276 263
277 264static struct pci_device_id nicstar_pci_tbl[] __devinitdata = {
278
279static struct pci_device_id nicstar_pci_tbl[] __devinitdata =
280{
281 {PCI_VENDOR_ID_IDT, PCI_DEVICE_ID_IDT_IDT77201, 265 {PCI_VENDOR_ID_IDT, PCI_DEVICE_ID_IDT_IDT77201,
282 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 266 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
283 {0,} /* terminate list */ 267 {0,} /* terminate list */
284}; 268};
285MODULE_DEVICE_TABLE(pci, nicstar_pci_tbl);
286
287 269
270MODULE_DEVICE_TABLE(pci, nicstar_pci_tbl);
288 271
289static struct pci_driver nicstar_driver = { 272static struct pci_driver nicstar_driver = {
290 .name = "nicstar", 273 .name = "nicstar",
291 .id_table = nicstar_pci_tbl, 274 .id_table = nicstar_pci_tbl,
292 .probe = nicstar_init_one, 275 .probe = nicstar_init_one,
293 .remove = __devexit_p(nicstar_remove_one), 276 .remove = __devexit_p(nicstar_remove_one),
294}; 277};
295 278
296
297
298static int __init nicstar_init(void) 279static int __init nicstar_init(void)
299{ 280{
300 unsigned error = 0; /* Initialized to remove compile warning */ 281 unsigned error = 0; /* Initialized to remove compile warning */
301 282
302 XPRINTK("nicstar: nicstar_init() called.\n"); 283 XPRINTK("nicstar: nicstar_init() called.\n");
303 284
304 error = pci_register_driver(&nicstar_driver); 285 error = pci_register_driver(&nicstar_driver);
305 286
306 TXPRINTK("nicstar: TX debug enabled.\n"); 287 TXPRINTK("nicstar: TX debug enabled.\n");
307 RXPRINTK("nicstar: RX debug enabled.\n"); 288 RXPRINTK("nicstar: RX debug enabled.\n");
308 PRINTK("nicstar: General debug enabled.\n"); 289 PRINTK("nicstar: General debug enabled.\n");
309#ifdef PHY_LOOPBACK 290#ifdef PHY_LOOPBACK
310 printk("nicstar: using PHY loopback.\n"); 291 printk("nicstar: using PHY loopback.\n");
311#endif /* PHY_LOOPBACK */ 292#endif /* PHY_LOOPBACK */
312 XPRINTK("nicstar: nicstar_init() returned.\n"); 293 XPRINTK("nicstar: nicstar_init() returned.\n");
313
314 if (!error) {
315 init_timer(&ns_timer);
316 ns_timer.expires = jiffies + NS_POLL_PERIOD;
317 ns_timer.data = 0UL;
318 ns_timer.function = ns_poll;
319 add_timer(&ns_timer);
320 }
321
322 return error;
323}
324 294
295 if (!error) {
296 init_timer(&ns_timer);
297 ns_timer.expires = jiffies + NS_POLL_PERIOD;
298 ns_timer.data = 0UL;
299 ns_timer.function = ns_poll;
300 add_timer(&ns_timer);
301 }
325 302
303 return error;
304}
326 305
327static void __exit nicstar_cleanup(void) 306static void __exit nicstar_cleanup(void)
328{ 307{
329 XPRINTK("nicstar: nicstar_cleanup() called.\n"); 308 XPRINTK("nicstar: nicstar_cleanup() called.\n");
330 309
331 del_timer(&ns_timer); 310 del_timer(&ns_timer);
332 311
333 pci_unregister_driver(&nicstar_driver); 312 pci_unregister_driver(&nicstar_driver);
334 313
335 XPRINTK("nicstar: nicstar_cleanup() returned.\n"); 314 XPRINTK("nicstar: nicstar_cleanup() returned.\n");
336} 315}
337 316
338 317static u32 ns_read_sram(ns_dev * card, u32 sram_address)
339
340static u32 ns_read_sram(ns_dev *card, u32 sram_address)
341{ 318{
342 unsigned long flags; 319 unsigned long flags;
343 u32 data; 320 u32 data;
344 sram_address <<= 2; 321 sram_address <<= 2;
345 sram_address &= 0x0007FFFC; /* address must be dword aligned */ 322 sram_address &= 0x0007FFFC; /* address must be dword aligned */
346 sram_address |= 0x50000000; /* SRAM read command */ 323 sram_address |= 0x50000000; /* SRAM read command */
347 spin_lock_irqsave(&card->res_lock, flags); 324 spin_lock_irqsave(&card->res_lock, flags);
348 while (CMD_BUSY(card)); 325 while (CMD_BUSY(card)) ;
349 writel(sram_address, card->membase + CMD); 326 writel(sram_address, card->membase + CMD);
350 while (CMD_BUSY(card)); 327 while (CMD_BUSY(card)) ;
351 data = readl(card->membase + DR0); 328 data = readl(card->membase + DR0);
352 spin_unlock_irqrestore(&card->res_lock, flags); 329 spin_unlock_irqrestore(&card->res_lock, flags);
353 return data; 330 return data;
354} 331}
355 332
356 333static void ns_write_sram(ns_dev * card, u32 sram_address, u32 * value,
357 334 int count)
358static void ns_write_sram(ns_dev *card, u32 sram_address, u32 *value, int count)
359{ 335{
360 unsigned long flags; 336 unsigned long flags;
361 int i, c; 337 int i, c;
362 count--; /* count range now is 0..3 instead of 1..4 */ 338 count--; /* count range now is 0..3 instead of 1..4 */
363 c = count; 339 c = count;
364 c <<= 2; /* to use increments of 4 */ 340 c <<= 2; /* to use increments of 4 */
365 spin_lock_irqsave(&card->res_lock, flags); 341 spin_lock_irqsave(&card->res_lock, flags);
366 while (CMD_BUSY(card)); 342 while (CMD_BUSY(card)) ;
367 for (i = 0; i <= c; i += 4) 343 for (i = 0; i <= c; i += 4)
368 writel(*(value++), card->membase + i); 344 writel(*(value++), card->membase + i);
369 /* Note: DR# registers are the first 4 dwords in nicstar's memspace, 345 /* Note: DR# registers are the first 4 dwords in nicstar's memspace,
370 so card->membase + DR0 == card->membase */ 346 so card->membase + DR0 == card->membase */
371 sram_address <<= 2; 347 sram_address <<= 2;
372 sram_address &= 0x0007FFFC; 348 sram_address &= 0x0007FFFC;
373 sram_address |= (0x40000000 | count); 349 sram_address |= (0x40000000 | count);
374 writel(sram_address, card->membase + CMD); 350 writel(sram_address, card->membase + CMD);
375 spin_unlock_irqrestore(&card->res_lock, flags); 351 spin_unlock_irqrestore(&card->res_lock, flags);
376} 352}
377 353
378
379static int __devinit ns_init_card(int i, struct pci_dev *pcidev) 354static int __devinit ns_init_card(int i, struct pci_dev *pcidev)
380{ 355{
381 int j; 356 int j;
382 struct ns_dev *card = NULL; 357 struct ns_dev *card = NULL;
383 unsigned char pci_latency; 358 unsigned char pci_latency;
384 unsigned error; 359 unsigned error;
385 u32 data; 360 u32 data;
386 u32 u32d[4]; 361 u32 u32d[4];
387 u32 ns_cfg_rctsize; 362 u32 ns_cfg_rctsize;
388 int bcount; 363 int bcount;
389 unsigned long membase; 364 unsigned long membase;
390 365
391 error = 0; 366 error = 0;
392 367
393 if (pci_enable_device(pcidev)) 368 if (pci_enable_device(pcidev)) {
394 { 369 printk("nicstar%d: can't enable PCI device\n", i);
395 printk("nicstar%d: can't enable PCI device\n", i); 370 error = 2;
396 error = 2; 371 ns_init_card_error(card, error);
397 ns_init_card_error(card, error); 372 return error;
398 return error; 373 }
399 } 374
400 375 if ((card = kmalloc(sizeof(ns_dev), GFP_KERNEL)) == NULL) {
401 if ((card = kmalloc(sizeof(ns_dev), GFP_KERNEL)) == NULL) 376 printk
402 { 377 ("nicstar%d: can't allocate memory for device structure.\n",
403 printk("nicstar%d: can't allocate memory for device structure.\n", i); 378 i);
404 error = 2; 379 error = 2;
405 ns_init_card_error(card, error); 380 ns_init_card_error(card, error);
406 return error; 381 return error;
407 } 382 }
408 cards[i] = card; 383 cards[i] = card;
409 spin_lock_init(&card->int_lock); 384 spin_lock_init(&card->int_lock);
410 spin_lock_init(&card->res_lock); 385 spin_lock_init(&card->res_lock);
411 386
412 pci_set_drvdata(pcidev, card); 387 pci_set_drvdata(pcidev, card);
413 388
414 card->index = i; 389 card->index = i;
415 card->atmdev = NULL; 390 card->atmdev = NULL;
416 card->pcidev = pcidev; 391 card->pcidev = pcidev;
417 membase = pci_resource_start(pcidev, 1); 392 membase = pci_resource_start(pcidev, 1);
418 card->membase = ioremap(membase, NS_IOREMAP_SIZE); 393 card->membase = ioremap(membase, NS_IOREMAP_SIZE);
419 if (!card->membase) 394 if (!card->membase) {
420 { 395 printk("nicstar%d: can't ioremap() membase.\n", i);
421 printk("nicstar%d: can't ioremap() membase.\n",i); 396 error = 3;
422 error = 3; 397 ns_init_card_error(card, error);
423 ns_init_card_error(card, error); 398 return error;
424 return error; 399 }
425 } 400 PRINTK("nicstar%d: membase at 0x%x.\n", i, card->membase);
426 PRINTK("nicstar%d: membase at 0x%x.\n", i, card->membase); 401
427 402 pci_set_master(pcidev);
428 pci_set_master(pcidev); 403
429 404 if (pci_read_config_byte(pcidev, PCI_LATENCY_TIMER, &pci_latency) != 0) {
430 if (pci_read_config_byte(pcidev, PCI_LATENCY_TIMER, &pci_latency) != 0) 405 printk("nicstar%d: can't read PCI latency timer.\n", i);
431 { 406 error = 6;
432 printk("nicstar%d: can't read PCI latency timer.\n", i); 407 ns_init_card_error(card, error);
433 error = 6; 408 return error;
434 ns_init_card_error(card, error); 409 }
435 return error;
436 }
437#ifdef NS_PCI_LATENCY 410#ifdef NS_PCI_LATENCY
438 if (pci_latency < NS_PCI_LATENCY) 411 if (pci_latency < NS_PCI_LATENCY) {
439 { 412 PRINTK("nicstar%d: setting PCI latency timer to %d.\n", i,
440 PRINTK("nicstar%d: setting PCI latency timer to %d.\n", i, NS_PCI_LATENCY); 413 NS_PCI_LATENCY);
441 for (j = 1; j < 4; j++) 414 for (j = 1; j < 4; j++) {
442 { 415 if (pci_write_config_byte
443 if (pci_write_config_byte(pcidev, PCI_LATENCY_TIMER, NS_PCI_LATENCY) != 0) 416 (pcidev, PCI_LATENCY_TIMER, NS_PCI_LATENCY) != 0)
444 break; 417 break;
445 } 418 }
446 if (j == 4) 419 if (j == 4) {
447 { 420 printk
448 printk("nicstar%d: can't set PCI latency timer to %d.\n", i, NS_PCI_LATENCY); 421 ("nicstar%d: can't set PCI latency timer to %d.\n",
449 error = 7; 422 i, NS_PCI_LATENCY);
450 ns_init_card_error(card, error); 423 error = 7;
451 return error; 424 ns_init_card_error(card, error);
452 } 425 return error;
453 } 426 }
427 }
454#endif /* NS_PCI_LATENCY */ 428#endif /* NS_PCI_LATENCY */
455 429
456 /* Clear timer overflow */ 430 /* Clear timer overflow */
457 data = readl(card->membase + STAT); 431 data = readl(card->membase + STAT);
458 if (data & NS_STAT_TMROF) 432 if (data & NS_STAT_TMROF)
459 writel(NS_STAT_TMROF, card->membase + STAT); 433 writel(NS_STAT_TMROF, card->membase + STAT);
460 434
461 /* Software reset */ 435 /* Software reset */
462 writel(NS_CFG_SWRST, card->membase + CFG); 436 writel(NS_CFG_SWRST, card->membase + CFG);
463 NS_DELAY; 437 NS_DELAY;
464 writel(0x00000000, card->membase + CFG); 438 writel(0x00000000, card->membase + CFG);
465 439
466 /* PHY reset */ 440 /* PHY reset */
467 writel(0x00000008, card->membase + GP); 441 writel(0x00000008, card->membase + GP);
468 NS_DELAY; 442 NS_DELAY;
469 writel(0x00000001, card->membase + GP); 443 writel(0x00000001, card->membase + GP);
470 NS_DELAY; 444 NS_DELAY;
471 while (CMD_BUSY(card)); 445 while (CMD_BUSY(card)) ;
472 writel(NS_CMD_WRITE_UTILITY | 0x00000100, card->membase + CMD); /* Sync UTOPIA with SAR clock */ 446 writel(NS_CMD_WRITE_UTILITY | 0x00000100, card->membase + CMD); /* Sync UTOPIA with SAR clock */
473 NS_DELAY; 447 NS_DELAY;
474 448
475 /* Detect PHY type */ 449 /* Detect PHY type */
476 while (CMD_BUSY(card)); 450 while (CMD_BUSY(card)) ;
477 writel(NS_CMD_READ_UTILITY | 0x00000200, card->membase + CMD); 451 writel(NS_CMD_READ_UTILITY | 0x00000200, card->membase + CMD);
478 while (CMD_BUSY(card)); 452 while (CMD_BUSY(card)) ;
479 data = readl(card->membase + DR0); 453 data = readl(card->membase + DR0);
480 switch(data) { 454 switch (data) {
481 case 0x00000009: 455 case 0x00000009:
482 printk("nicstar%d: PHY seems to be 25 Mbps.\n", i); 456 printk("nicstar%d: PHY seems to be 25 Mbps.\n", i);
483 card->max_pcr = ATM_25_PCR; 457 card->max_pcr = ATM_25_PCR;
484 while(CMD_BUSY(card)); 458 while (CMD_BUSY(card)) ;
485 writel(0x00000008, card->membase + DR0); 459 writel(0x00000008, card->membase + DR0);
486 writel(NS_CMD_WRITE_UTILITY | 0x00000200, card->membase + CMD); 460 writel(NS_CMD_WRITE_UTILITY | 0x00000200, card->membase + CMD);
487 /* Clear an eventual pending interrupt */ 461 /* Clear an eventual pending interrupt */
488 writel(NS_STAT_SFBQF, card->membase + STAT); 462 writel(NS_STAT_SFBQF, card->membase + STAT);
489#ifdef PHY_LOOPBACK 463#ifdef PHY_LOOPBACK
490 while(CMD_BUSY(card)); 464 while (CMD_BUSY(card)) ;
491 writel(0x00000022, card->membase + DR0); 465 writel(0x00000022, card->membase + DR0);
492 writel(NS_CMD_WRITE_UTILITY | 0x00000202, card->membase + CMD); 466 writel(NS_CMD_WRITE_UTILITY | 0x00000202, card->membase + CMD);
493#endif /* PHY_LOOPBACK */ 467#endif /* PHY_LOOPBACK */
494 break; 468 break;
495 case 0x00000030: 469 case 0x00000030:
496 case 0x00000031: 470 case 0x00000031:
497 printk("nicstar%d: PHY seems to be 155 Mbps.\n", i); 471 printk("nicstar%d: PHY seems to be 155 Mbps.\n", i);
498 card->max_pcr = ATM_OC3_PCR; 472 card->max_pcr = ATM_OC3_PCR;
499#ifdef PHY_LOOPBACK 473#ifdef PHY_LOOPBACK
500 while(CMD_BUSY(card)); 474 while (CMD_BUSY(card)) ;
501 writel(0x00000002, card->membase + DR0); 475 writel(0x00000002, card->membase + DR0);
502 writel(NS_CMD_WRITE_UTILITY | 0x00000205, card->membase + CMD); 476 writel(NS_CMD_WRITE_UTILITY | 0x00000205, card->membase + CMD);
503#endif /* PHY_LOOPBACK */ 477#endif /* PHY_LOOPBACK */
504 break; 478 break;
505 default: 479 default:
506 printk("nicstar%d: unknown PHY type (0x%08X).\n", i, data); 480 printk("nicstar%d: unknown PHY type (0x%08X).\n", i, data);
507 error = 8; 481 error = 8;
508 ns_init_card_error(card, error); 482 ns_init_card_error(card, error);
509 return error; 483 return error;
510 } 484 }
511 writel(0x00000000, card->membase + GP); 485 writel(0x00000000, card->membase + GP);
512 486
513 /* Determine SRAM size */ 487 /* Determine SRAM size */
514 data = 0x76543210; 488 data = 0x76543210;
515 ns_write_sram(card, 0x1C003, &data, 1); 489 ns_write_sram(card, 0x1C003, &data, 1);
516 data = 0x89ABCDEF; 490 data = 0x89ABCDEF;
517 ns_write_sram(card, 0x14003, &data, 1); 491 ns_write_sram(card, 0x14003, &data, 1);
518 if (ns_read_sram(card, 0x14003) == 0x89ABCDEF && 492 if (ns_read_sram(card, 0x14003) == 0x89ABCDEF &&
519 ns_read_sram(card, 0x1C003) == 0x76543210) 493 ns_read_sram(card, 0x1C003) == 0x76543210)
520 card->sram_size = 128; 494 card->sram_size = 128;
521 else 495 else
522 card->sram_size = 32; 496 card->sram_size = 32;
523 PRINTK("nicstar%d: %dK x 32bit SRAM size.\n", i, card->sram_size); 497 PRINTK("nicstar%d: %dK x 32bit SRAM size.\n", i, card->sram_size);
524 498
525 card->rct_size = NS_MAX_RCTSIZE; 499 card->rct_size = NS_MAX_RCTSIZE;
526 500
527#if (NS_MAX_RCTSIZE == 4096) 501#if (NS_MAX_RCTSIZE == 4096)
528 if (card->sram_size == 128) 502 if (card->sram_size == 128)
529 printk("nicstar%d: limiting maximum VCI. See NS_MAX_RCTSIZE in nicstar.h\n", i); 503 printk
504 ("nicstar%d: limiting maximum VCI. See NS_MAX_RCTSIZE in nicstar.h\n",
505 i);
530#elif (NS_MAX_RCTSIZE == 16384) 506#elif (NS_MAX_RCTSIZE == 16384)
531 if (card->sram_size == 32) 507 if (card->sram_size == 32) {
532 { 508 printk
533 printk("nicstar%d: wasting memory. See NS_MAX_RCTSIZE in nicstar.h\n", i); 509 ("nicstar%d: wasting memory. See NS_MAX_RCTSIZE in nicstar.h\n",
534 card->rct_size = 4096; 510 i);
535 } 511 card->rct_size = 4096;
512 }
536#else 513#else
537#error NS_MAX_RCTSIZE must be either 4096 or 16384 in nicstar.c 514#error NS_MAX_RCTSIZE must be either 4096 or 16384 in nicstar.c
538#endif 515#endif
539 516
540 card->vpibits = NS_VPIBITS; 517 card->vpibits = NS_VPIBITS;
541 if (card->rct_size == 4096) 518 if (card->rct_size == 4096)
542 card->vcibits = 12 - NS_VPIBITS; 519 card->vcibits = 12 - NS_VPIBITS;
543 else /* card->rct_size == 16384 */ 520 else /* card->rct_size == 16384 */
544 card->vcibits = 14 - NS_VPIBITS; 521 card->vcibits = 14 - NS_VPIBITS;
545 522
546 /* Initialize the nicstar eeprom/eprom stuff, for the MAC addr */ 523 /* Initialize the nicstar eeprom/eprom stuff, for the MAC addr */
547 if (mac[i] == NULL) 524 if (mac[i] == NULL)
548 nicstar_init_eprom(card->membase); 525 nicstar_init_eprom(card->membase);
549 526
550 /* Set the VPI/VCI MSb mask to zero so we can receive OAM cells */ 527 /* Set the VPI/VCI MSb mask to zero so we can receive OAM cells */
551 writel(0x00000000, card->membase + VPM); 528 writel(0x00000000, card->membase + VPM);
552 529
553 /* Initialize TSQ */ 530 /* Initialize TSQ */
554 card->tsq.org = kmalloc(NS_TSQSIZE + NS_TSQ_ALIGNMENT, GFP_KERNEL); 531 card->tsq.org = kmalloc(NS_TSQSIZE + NS_TSQ_ALIGNMENT, GFP_KERNEL);
555 if (card->tsq.org == NULL) 532 if (card->tsq.org == NULL) {
556 { 533 printk("nicstar%d: can't allocate TSQ.\n", i);
557 printk("nicstar%d: can't allocate TSQ.\n", i); 534 error = 10;
558 error = 10; 535 ns_init_card_error(card, error);
559 ns_init_card_error(card, error); 536 return error;
560 return error; 537 }
561 } 538 card->tsq.base =
562 card->tsq.base = (ns_tsi *) ALIGN_ADDRESS(card->tsq.org, NS_TSQ_ALIGNMENT); 539 (ns_tsi *) ALIGN_ADDRESS(card->tsq.org, NS_TSQ_ALIGNMENT);
563 card->tsq.next = card->tsq.base; 540 card->tsq.next = card->tsq.base;
564 card->tsq.last = card->tsq.base + (NS_TSQ_NUM_ENTRIES - 1); 541 card->tsq.last = card->tsq.base + (NS_TSQ_NUM_ENTRIES - 1);
565 for (j = 0; j < NS_TSQ_NUM_ENTRIES; j++) 542 for (j = 0; j < NS_TSQ_NUM_ENTRIES; j++)
566 ns_tsi_init(card->tsq.base + j); 543 ns_tsi_init(card->tsq.base + j);
567 writel(0x00000000, card->membase + TSQH); 544 writel(0x00000000, card->membase + TSQH);
568 writel((u32) virt_to_bus(card->tsq.base), card->membase + TSQB); 545 writel((u32) virt_to_bus(card->tsq.base), card->membase + TSQB);
569 PRINTK("nicstar%d: TSQ base at 0x%x 0x%x 0x%x.\n", i, (u32) card->tsq.base, 546 PRINTK("nicstar%d: TSQ base at 0x%x 0x%x 0x%x.\n", i,
570 (u32) virt_to_bus(card->tsq.base), readl(card->membase + TSQB)); 547 (u32) card->tsq.base, (u32) virt_to_bus(card->tsq.base),
571 548 readl(card->membase + TSQB));
572 /* Initialize RSQ */ 549
573 card->rsq.org = kmalloc(NS_RSQSIZE + NS_RSQ_ALIGNMENT, GFP_KERNEL); 550 /* Initialize RSQ */
574 if (card->rsq.org == NULL) 551 card->rsq.org = kmalloc(NS_RSQSIZE + NS_RSQ_ALIGNMENT, GFP_KERNEL);
575 { 552 if (card->rsq.org == NULL) {
576 printk("nicstar%d: can't allocate RSQ.\n", i); 553 printk("nicstar%d: can't allocate RSQ.\n", i);
577 error = 11; 554 error = 11;
578 ns_init_card_error(card, error); 555 ns_init_card_error(card, error);
579 return error; 556 return error;
580 } 557 }
581 card->rsq.base = (ns_rsqe *) ALIGN_ADDRESS(card->rsq.org, NS_RSQ_ALIGNMENT); 558 card->rsq.base =
582 card->rsq.next = card->rsq.base; 559 (ns_rsqe *) ALIGN_ADDRESS(card->rsq.org, NS_RSQ_ALIGNMENT);
583 card->rsq.last = card->rsq.base + (NS_RSQ_NUM_ENTRIES - 1); 560 card->rsq.next = card->rsq.base;
584 for (j = 0; j < NS_RSQ_NUM_ENTRIES; j++) 561 card->rsq.last = card->rsq.base + (NS_RSQ_NUM_ENTRIES - 1);
585 ns_rsqe_init(card->rsq.base + j); 562 for (j = 0; j < NS_RSQ_NUM_ENTRIES; j++)
586 writel(0x00000000, card->membase + RSQH); 563 ns_rsqe_init(card->rsq.base + j);
587 writel((u32) virt_to_bus(card->rsq.base), card->membase + RSQB); 564 writel(0x00000000, card->membase + RSQH);
588 PRINTK("nicstar%d: RSQ base at 0x%x.\n", i, (u32) card->rsq.base); 565 writel((u32) virt_to_bus(card->rsq.base), card->membase + RSQB);
589 566 PRINTK("nicstar%d: RSQ base at 0x%x.\n", i, (u32) card->rsq.base);
590 /* Initialize SCQ0, the only VBR SCQ used */ 567
591 card->scq1 = NULL; 568 /* Initialize SCQ0, the only VBR SCQ used */
592 card->scq2 = NULL; 569 card->scq1 = NULL;
593 card->scq0 = get_scq(VBR_SCQSIZE, NS_VRSCD0); 570 card->scq2 = NULL;
594 if (card->scq0 == NULL) 571 card->scq0 = get_scq(VBR_SCQSIZE, NS_VRSCD0);
595 { 572 if (card->scq0 == NULL) {
596 printk("nicstar%d: can't get SCQ0.\n", i); 573 printk("nicstar%d: can't get SCQ0.\n", i);
597 error = 12; 574 error = 12;
598 ns_init_card_error(card, error); 575 ns_init_card_error(card, error);
599 return error; 576 return error;
600 } 577 }
601 u32d[0] = (u32) virt_to_bus(card->scq0->base); 578 u32d[0] = (u32) virt_to_bus(card->scq0->base);
602 u32d[1] = (u32) 0x00000000; 579 u32d[1] = (u32) 0x00000000;
603 u32d[2] = (u32) 0xffffffff; 580 u32d[2] = (u32) 0xffffffff;
604 u32d[3] = (u32) 0x00000000; 581 u32d[3] = (u32) 0x00000000;
605 ns_write_sram(card, NS_VRSCD0, u32d, 4); 582 ns_write_sram(card, NS_VRSCD0, u32d, 4);
606 ns_write_sram(card, NS_VRSCD1, u32d, 4); /* These last two won't be used */ 583 ns_write_sram(card, NS_VRSCD1, u32d, 4); /* These last two won't be used */
607 ns_write_sram(card, NS_VRSCD2, u32d, 4); /* but are initialized, just in case... */ 584 ns_write_sram(card, NS_VRSCD2, u32d, 4); /* but are initialized, just in case... */
608 card->scq0->scd = NS_VRSCD0; 585 card->scq0->scd = NS_VRSCD0;
609 PRINTK("nicstar%d: VBR-SCQ0 base at 0x%x.\n", i, (u32) card->scq0->base); 586 PRINTK("nicstar%d: VBR-SCQ0 base at 0x%x.\n", i,
610 587 (u32) card->scq0->base);
611 /* Initialize TSTs */ 588
612 card->tst_addr = NS_TST0; 589 /* Initialize TSTs */
613 card->tst_free_entries = NS_TST_NUM_ENTRIES; 590 card->tst_addr = NS_TST0;
614 data = NS_TST_OPCODE_VARIABLE; 591 card->tst_free_entries = NS_TST_NUM_ENTRIES;
615 for (j = 0; j < NS_TST_NUM_ENTRIES; j++) 592 data = NS_TST_OPCODE_VARIABLE;
616 ns_write_sram(card, NS_TST0 + j, &data, 1); 593 for (j = 0; j < NS_TST_NUM_ENTRIES; j++)
617 data = ns_tste_make(NS_TST_OPCODE_END, NS_TST0); 594 ns_write_sram(card, NS_TST0 + j, &data, 1);
618 ns_write_sram(card, NS_TST0 + NS_TST_NUM_ENTRIES, &data, 1); 595 data = ns_tste_make(NS_TST_OPCODE_END, NS_TST0);
619 for (j = 0; j < NS_TST_NUM_ENTRIES; j++) 596 ns_write_sram(card, NS_TST0 + NS_TST_NUM_ENTRIES, &data, 1);
620 ns_write_sram(card, NS_TST1 + j, &data, 1); 597 for (j = 0; j < NS_TST_NUM_ENTRIES; j++)
621 data = ns_tste_make(NS_TST_OPCODE_END, NS_TST1); 598 ns_write_sram(card, NS_TST1 + j, &data, 1);
622 ns_write_sram(card, NS_TST1 + NS_TST_NUM_ENTRIES, &data, 1); 599 data = ns_tste_make(NS_TST_OPCODE_END, NS_TST1);
623 for (j = 0; j < NS_TST_NUM_ENTRIES; j++) 600 ns_write_sram(card, NS_TST1 + NS_TST_NUM_ENTRIES, &data, 1);
624 card->tste2vc[j] = NULL; 601 for (j = 0; j < NS_TST_NUM_ENTRIES; j++)
625 writel(NS_TST0 << 2, card->membase + TSTB); 602 card->tste2vc[j] = NULL;
626 603 writel(NS_TST0 << 2, card->membase + TSTB);
627 604
628 /* Initialize RCT. AAL type is set on opening the VC. */ 605 /* Initialize RCT. AAL type is set on opening the VC. */
629#ifdef RCQ_SUPPORT 606#ifdef RCQ_SUPPORT
630 u32d[0] = NS_RCTE_RAWCELLINTEN; 607 u32d[0] = NS_RCTE_RAWCELLINTEN;
631#else 608#else
632 u32d[0] = 0x00000000; 609 u32d[0] = 0x00000000;
633#endif /* RCQ_SUPPORT */ 610#endif /* RCQ_SUPPORT */
634 u32d[1] = 0x00000000; 611 u32d[1] = 0x00000000;
635 u32d[2] = 0x00000000; 612 u32d[2] = 0x00000000;
636 u32d[3] = 0xFFFFFFFF; 613 u32d[3] = 0xFFFFFFFF;
637 for (j = 0; j < card->rct_size; j++) 614 for (j = 0; j < card->rct_size; j++)
638 ns_write_sram(card, j * 4, u32d, 4); 615 ns_write_sram(card, j * 4, u32d, 4);
639 616
640 memset(card->vcmap, 0, NS_MAX_RCTSIZE * sizeof(vc_map)); 617 memset(card->vcmap, 0, NS_MAX_RCTSIZE * sizeof(vc_map));
641 618
642 for (j = 0; j < NS_FRSCD_NUM; j++) 619 for (j = 0; j < NS_FRSCD_NUM; j++)
643 card->scd2vc[j] = NULL; 620 card->scd2vc[j] = NULL;
644 621
645 /* Initialize buffer levels */ 622 /* Initialize buffer levels */
646 card->sbnr.min = MIN_SB; 623 card->sbnr.min = MIN_SB;
647 card->sbnr.init = NUM_SB; 624 card->sbnr.init = NUM_SB;
648 card->sbnr.max = MAX_SB; 625 card->sbnr.max = MAX_SB;
649 card->lbnr.min = MIN_LB; 626 card->lbnr.min = MIN_LB;
650 card->lbnr.init = NUM_LB; 627 card->lbnr.init = NUM_LB;
651 card->lbnr.max = MAX_LB; 628 card->lbnr.max = MAX_LB;
652 card->iovnr.min = MIN_IOVB; 629 card->iovnr.min = MIN_IOVB;
653 card->iovnr.init = NUM_IOVB; 630 card->iovnr.init = NUM_IOVB;
654 card->iovnr.max = MAX_IOVB; 631 card->iovnr.max = MAX_IOVB;
655 card->hbnr.min = MIN_HB; 632 card->hbnr.min = MIN_HB;
656 card->hbnr.init = NUM_HB; 633 card->hbnr.init = NUM_HB;
657 card->hbnr.max = MAX_HB; 634 card->hbnr.max = MAX_HB;
658 635
659 card->sm_handle = 0x00000000; 636 card->sm_handle = 0x00000000;
660 card->sm_addr = 0x00000000; 637 card->sm_addr = 0x00000000;
661 card->lg_handle = 0x00000000; 638 card->lg_handle = 0x00000000;
662 card->lg_addr = 0x00000000; 639 card->lg_addr = 0x00000000;
663 640
664 card->efbie = 1; /* To prevent push_rxbufs from enabling the interrupt */ 641 card->efbie = 1; /* To prevent push_rxbufs from enabling the interrupt */
665 642
666 /* Pre-allocate some huge buffers */ 643 /* Pre-allocate some huge buffers */
667 skb_queue_head_init(&card->hbpool.queue); 644 skb_queue_head_init(&card->hbpool.queue);
668 card->hbpool.count = 0; 645 card->hbpool.count = 0;
669 for (j = 0; j < NUM_HB; j++) 646 for (j = 0; j < NUM_HB; j++) {
670 { 647 struct sk_buff *hb;
671 struct sk_buff *hb; 648 hb = __dev_alloc_skb(NS_HBUFSIZE, GFP_KERNEL);
672 hb = __dev_alloc_skb(NS_HBUFSIZE, GFP_KERNEL); 649 if (hb == NULL) {
673 if (hb == NULL) 650 printk
674 { 651 ("nicstar%d: can't allocate %dth of %d huge buffers.\n",
675 printk("nicstar%d: can't allocate %dth of %d huge buffers.\n", 652 i, j, NUM_HB);
676 i, j, NUM_HB); 653 error = 13;
677 error = 13; 654 ns_init_card_error(card, error);
678 ns_init_card_error(card, error); 655 return error;
679 return error; 656 }
680 } 657 NS_SKB_CB(hb)->buf_type = BUF_NONE;
681 NS_SKB_CB(hb)->buf_type = BUF_NONE; 658 skb_queue_tail(&card->hbpool.queue, hb);
682 skb_queue_tail(&card->hbpool.queue, hb); 659 card->hbpool.count++;
683 card->hbpool.count++; 660 }
684 } 661
685 662 /* Allocate large buffers */
686 663 skb_queue_head_init(&card->lbpool.queue);
687 /* Allocate large buffers */ 664 card->lbpool.count = 0; /* Not used */
688 skb_queue_head_init(&card->lbpool.queue); 665 for (j = 0; j < NUM_LB; j++) {
689 card->lbpool.count = 0; /* Not used */ 666 struct sk_buff *lb;
690 for (j = 0; j < NUM_LB; j++) 667 lb = __dev_alloc_skb(NS_LGSKBSIZE, GFP_KERNEL);
691 { 668 if (lb == NULL) {
692 struct sk_buff *lb; 669 printk
693 lb = __dev_alloc_skb(NS_LGSKBSIZE, GFP_KERNEL); 670 ("nicstar%d: can't allocate %dth of %d large buffers.\n",
694 if (lb == NULL) 671 i, j, NUM_LB);
695 { 672 error = 14;
696 printk("nicstar%d: can't allocate %dth of %d large buffers.\n", 673 ns_init_card_error(card, error);
697 i, j, NUM_LB); 674 return error;
698 error = 14; 675 }
699 ns_init_card_error(card, error); 676 NS_SKB_CB(lb)->buf_type = BUF_LG;
700 return error; 677 skb_queue_tail(&card->lbpool.queue, lb);
701 } 678 skb_reserve(lb, NS_SMBUFSIZE);
702 NS_SKB_CB(lb)->buf_type = BUF_LG; 679 push_rxbufs(card, lb);
703 skb_queue_tail(&card->lbpool.queue, lb); 680 /* Due to the implementation of push_rxbufs() this is 1, not 0 */
704 skb_reserve(lb, NS_SMBUFSIZE); 681 if (j == 1) {
705 push_rxbufs(card, lb); 682 card->rcbuf = lb;
706 /* Due to the implementation of push_rxbufs() this is 1, not 0 */ 683 card->rawch = (u32) virt_to_bus(lb->data);
707 if (j == 1) 684 }
708 { 685 }
709 card->rcbuf = lb; 686 /* Test for strange behaviour which leads to crashes */
710 card->rawch = (u32) virt_to_bus(lb->data); 687 if ((bcount =
711 } 688 ns_stat_lfbqc_get(readl(card->membase + STAT))) < card->lbnr.min) {
712 } 689 printk
713 /* Test for strange behaviour which leads to crashes */ 690 ("nicstar%d: Strange... Just allocated %d large buffers and lfbqc = %d.\n",
714 if ((bcount = ns_stat_lfbqc_get(readl(card->membase + STAT))) < card->lbnr.min) 691 i, j, bcount);
715 { 692 error = 14;
716 printk("nicstar%d: Strange... Just allocated %d large buffers and lfbqc = %d.\n", 693 ns_init_card_error(card, error);
717 i, j, bcount); 694 return error;
718 error = 14; 695 }
719 ns_init_card_error(card, error); 696
720 return error; 697 /* Allocate small buffers */
721 } 698 skb_queue_head_init(&card->sbpool.queue);
722 699 card->sbpool.count = 0; /* Not used */
723 700 for (j = 0; j < NUM_SB; j++) {
724 /* Allocate small buffers */ 701 struct sk_buff *sb;
725 skb_queue_head_init(&card->sbpool.queue); 702 sb = __dev_alloc_skb(NS_SMSKBSIZE, GFP_KERNEL);
726 card->sbpool.count = 0; /* Not used */ 703 if (sb == NULL) {
727 for (j = 0; j < NUM_SB; j++) 704 printk
728 { 705 ("nicstar%d: can't allocate %dth of %d small buffers.\n",
729 struct sk_buff *sb; 706 i, j, NUM_SB);
730 sb = __dev_alloc_skb(NS_SMSKBSIZE, GFP_KERNEL); 707 error = 15;
731 if (sb == NULL) 708 ns_init_card_error(card, error);
732 { 709 return error;
733 printk("nicstar%d: can't allocate %dth of %d small buffers.\n", 710 }
734 i, j, NUM_SB); 711 NS_SKB_CB(sb)->buf_type = BUF_SM;
735 error = 15; 712 skb_queue_tail(&card->sbpool.queue, sb);
736 ns_init_card_error(card, error); 713 skb_reserve(sb, NS_AAL0_HEADER);
737 return error; 714 push_rxbufs(card, sb);
738 } 715 }
739 NS_SKB_CB(sb)->buf_type = BUF_SM; 716 /* Test for strange behaviour which leads to crashes */
740 skb_queue_tail(&card->sbpool.queue, sb); 717 if ((bcount =
741 skb_reserve(sb, NS_AAL0_HEADER); 718 ns_stat_sfbqc_get(readl(card->membase + STAT))) < card->sbnr.min) {
742 push_rxbufs(card, sb); 719 printk
743 } 720 ("nicstar%d: Strange... Just allocated %d small buffers and sfbqc = %d.\n",
744 /* Test for strange behaviour which leads to crashes */ 721 i, j, bcount);
745 if ((bcount = ns_stat_sfbqc_get(readl(card->membase + STAT))) < card->sbnr.min) 722 error = 15;
746 { 723 ns_init_card_error(card, error);
747 printk("nicstar%d: Strange... Just allocated %d small buffers and sfbqc = %d.\n", 724 return error;
748 i, j, bcount); 725 }
749 error = 15; 726
750 ns_init_card_error(card, error); 727 /* Allocate iovec buffers */
751 return error; 728 skb_queue_head_init(&card->iovpool.queue);
752 } 729 card->iovpool.count = 0;
753 730 for (j = 0; j < NUM_IOVB; j++) {
754 731 struct sk_buff *iovb;
755 /* Allocate iovec buffers */ 732 iovb = alloc_skb(NS_IOVBUFSIZE, GFP_KERNEL);
756 skb_queue_head_init(&card->iovpool.queue); 733 if (iovb == NULL) {
757 card->iovpool.count = 0; 734 printk
758 for (j = 0; j < NUM_IOVB; j++) 735 ("nicstar%d: can't allocate %dth of %d iovec buffers.\n",
759 { 736 i, j, NUM_IOVB);
760 struct sk_buff *iovb; 737 error = 16;
761 iovb = alloc_skb(NS_IOVBUFSIZE, GFP_KERNEL); 738 ns_init_card_error(card, error);
762 if (iovb == NULL) 739 return error;
763 { 740 }
764 printk("nicstar%d: can't allocate %dth of %d iovec buffers.\n", 741 NS_SKB_CB(iovb)->buf_type = BUF_NONE;
765 i, j, NUM_IOVB); 742 skb_queue_tail(&card->iovpool.queue, iovb);
766 error = 16; 743 card->iovpool.count++;
767 ns_init_card_error(card, error); 744 }
768 return error; 745
769 } 746 /* Configure NICStAR */
770 NS_SKB_CB(iovb)->buf_type = BUF_NONE; 747 if (card->rct_size == 4096)
771 skb_queue_tail(&card->iovpool.queue, iovb); 748 ns_cfg_rctsize = NS_CFG_RCTSIZE_4096_ENTRIES;
772 card->iovpool.count++; 749 else /* (card->rct_size == 16384) */
773 } 750 ns_cfg_rctsize = NS_CFG_RCTSIZE_16384_ENTRIES;
774 751
775 /* Configure NICStAR */ 752 card->efbie = 1;
776 if (card->rct_size == 4096) 753
777 ns_cfg_rctsize = NS_CFG_RCTSIZE_4096_ENTRIES; 754 card->intcnt = 0;
778 else /* (card->rct_size == 16384) */ 755 if (request_irq
779 ns_cfg_rctsize = NS_CFG_RCTSIZE_16384_ENTRIES; 756 (pcidev->irq, &ns_irq_handler, IRQF_DISABLED | IRQF_SHARED,
780 757 "nicstar", card) != 0) {
781 card->efbie = 1; 758 printk("nicstar%d: can't allocate IRQ %d.\n", i, pcidev->irq);
782 759 error = 9;
783 card->intcnt = 0; 760 ns_init_card_error(card, error);
784 if (request_irq(pcidev->irq, &ns_irq_handler, IRQF_DISABLED | IRQF_SHARED, "nicstar", card) != 0) 761 return error;
785 { 762 }
786 printk("nicstar%d: can't allocate IRQ %d.\n", i, pcidev->irq); 763
787 error = 9; 764 /* Register device */
788 ns_init_card_error(card, error); 765 card->atmdev = atm_dev_register("nicstar", &atm_ops, -1, NULL);
789 return error; 766 if (card->atmdev == NULL) {
790 } 767 printk("nicstar%d: can't register device.\n", i);
791 768 error = 17;
792 /* Register device */ 769 ns_init_card_error(card, error);
793 card->atmdev = atm_dev_register("nicstar", &atm_ops, -1, NULL); 770 return error;
794 if (card->atmdev == NULL) 771 }
795 { 772
796 printk("nicstar%d: can't register device.\n", i); 773 if (ns_parse_mac(mac[i], card->atmdev->esi)) {
797 error = 17; 774 nicstar_read_eprom(card->membase, NICSTAR_EPROM_MAC_ADDR_OFFSET,
798 ns_init_card_error(card, error); 775 card->atmdev->esi, 6);
799 return error; 776 if (memcmp(card->atmdev->esi, "\x00\x00\x00\x00\x00\x00", 6) ==
800 } 777 0) {
801 778 nicstar_read_eprom(card->membase,
802 if (ns_parse_mac(mac[i], card->atmdev->esi)) { 779 NICSTAR_EPROM_MAC_ADDR_OFFSET_ALT,
803 nicstar_read_eprom(card->membase, NICSTAR_EPROM_MAC_ADDR_OFFSET, 780 card->atmdev->esi, 6);
804 card->atmdev->esi, 6); 781 }
805 if (memcmp(card->atmdev->esi, "\x00\x00\x00\x00\x00\x00", 6) == 0) { 782 }
806 nicstar_read_eprom(card->membase, NICSTAR_EPROM_MAC_ADDR_OFFSET_ALT, 783
807 card->atmdev->esi, 6); 784 printk("nicstar%d: MAC address %pM\n", i, card->atmdev->esi);
808 } 785
809 } 786 card->atmdev->dev_data = card;
810 787 card->atmdev->ci_range.vpi_bits = card->vpibits;
811 printk("nicstar%d: MAC address %pM\n", i, card->atmdev->esi); 788 card->atmdev->ci_range.vci_bits = card->vcibits;
812 789 card->atmdev->link_rate = card->max_pcr;
813 card->atmdev->dev_data = card; 790 card->atmdev->phy = NULL;
814 card->atmdev->ci_range.vpi_bits = card->vpibits;
815 card->atmdev->ci_range.vci_bits = card->vcibits;
816 card->atmdev->link_rate = card->max_pcr;
817 card->atmdev->phy = NULL;
818 791
819#ifdef CONFIG_ATM_NICSTAR_USE_SUNI 792#ifdef CONFIG_ATM_NICSTAR_USE_SUNI
820 if (card->max_pcr == ATM_OC3_PCR) 793 if (card->max_pcr == ATM_OC3_PCR)
821 suni_init(card->atmdev); 794 suni_init(card->atmdev);
822#endif /* CONFIG_ATM_NICSTAR_USE_SUNI */ 795#endif /* CONFIG_ATM_NICSTAR_USE_SUNI */
823 796
824#ifdef CONFIG_ATM_NICSTAR_USE_IDT77105 797#ifdef CONFIG_ATM_NICSTAR_USE_IDT77105
825 if (card->max_pcr == ATM_25_PCR) 798 if (card->max_pcr == ATM_25_PCR)
826 idt77105_init(card->atmdev); 799 idt77105_init(card->atmdev);
827#endif /* CONFIG_ATM_NICSTAR_USE_IDT77105 */ 800#endif /* CONFIG_ATM_NICSTAR_USE_IDT77105 */
828 801
829 if (card->atmdev->phy && card->atmdev->phy->start) 802 if (card->atmdev->phy && card->atmdev->phy->start)
830 card->atmdev->phy->start(card->atmdev); 803 card->atmdev->phy->start(card->atmdev);
831
832 writel(NS_CFG_RXPATH |
833 NS_CFG_SMBUFSIZE |
834 NS_CFG_LGBUFSIZE |
835 NS_CFG_EFBIE |
836 NS_CFG_RSQSIZE |
837 NS_CFG_VPIBITS |
838 ns_cfg_rctsize |
839 NS_CFG_RXINT_NODELAY |
840 NS_CFG_RAWIE | /* Only enabled if RCQ_SUPPORT */
841 NS_CFG_RSQAFIE |
842 NS_CFG_TXEN |
843 NS_CFG_TXIE |
844 NS_CFG_TSQFIE_OPT | /* Only enabled if ENABLE_TSQFIE */
845 NS_CFG_PHYIE,
846 card->membase + CFG);
847
848 num_cards++;
849
850 return error;
851}
852 804
805 writel(NS_CFG_RXPATH | NS_CFG_SMBUFSIZE | NS_CFG_LGBUFSIZE | NS_CFG_EFBIE | NS_CFG_RSQSIZE | NS_CFG_VPIBITS | ns_cfg_rctsize | NS_CFG_RXINT_NODELAY | NS_CFG_RAWIE | /* Only enabled if RCQ_SUPPORT */
806 NS_CFG_RSQAFIE | NS_CFG_TXEN | NS_CFG_TXIE | NS_CFG_TSQFIE_OPT | /* Only enabled if ENABLE_TSQFIE */
807 NS_CFG_PHYIE, card->membase + CFG);
853 808
809 num_cards++;
854 810
855static void __devinit ns_init_card_error(ns_dev *card, int error) 811 return error;
856{
857 if (error >= 17)
858 {
859 writel(0x00000000, card->membase + CFG);
860 }
861 if (error >= 16)
862 {
863 struct sk_buff *iovb;
864 while ((iovb = skb_dequeue(&card->iovpool.queue)) != NULL)
865 dev_kfree_skb_any(iovb);
866 }
867 if (error >= 15)
868 {
869 struct sk_buff *sb;
870 while ((sb = skb_dequeue(&card->sbpool.queue)) != NULL)
871 dev_kfree_skb_any(sb);
872 free_scq(card->scq0, NULL);
873 }
874 if (error >= 14)
875 {
876 struct sk_buff *lb;
877 while ((lb = skb_dequeue(&card->lbpool.queue)) != NULL)
878 dev_kfree_skb_any(lb);
879 }
880 if (error >= 13)
881 {
882 struct sk_buff *hb;
883 while ((hb = skb_dequeue(&card->hbpool.queue)) != NULL)
884 dev_kfree_skb_any(hb);
885 }
886 if (error >= 12)
887 {
888 kfree(card->rsq.org);
889 }
890 if (error >= 11)
891 {
892 kfree(card->tsq.org);
893 }
894 if (error >= 10)
895 {
896 free_irq(card->pcidev->irq, card);
897 }
898 if (error >= 4)
899 {
900 iounmap(card->membase);
901 }
902 if (error >= 3)
903 {
904 pci_disable_device(card->pcidev);
905 kfree(card);
906 }
907} 812}
908 813
909 814static void __devinit ns_init_card_error(ns_dev * card, int error)
815{
816 if (error >= 17) {
817 writel(0x00000000, card->membase + CFG);
818 }
819 if (error >= 16) {
820 struct sk_buff *iovb;
821 while ((iovb = skb_dequeue(&card->iovpool.queue)) != NULL)
822 dev_kfree_skb_any(iovb);
823 }
824 if (error >= 15) {
825 struct sk_buff *sb;
826 while ((sb = skb_dequeue(&card->sbpool.queue)) != NULL)
827 dev_kfree_skb_any(sb);
828 free_scq(card->scq0, NULL);
829 }
830 if (error >= 14) {
831 struct sk_buff *lb;
832 while ((lb = skb_dequeue(&card->lbpool.queue)) != NULL)
833 dev_kfree_skb_any(lb);
834 }
835 if (error >= 13) {
836 struct sk_buff *hb;
837 while ((hb = skb_dequeue(&card->hbpool.queue)) != NULL)
838 dev_kfree_skb_any(hb);
839 }
840 if (error >= 12) {
841 kfree(card->rsq.org);
842 }
843 if (error >= 11) {
844 kfree(card->tsq.org);
845 }
846 if (error >= 10) {
847 free_irq(card->pcidev->irq, card);
848 }
849 if (error >= 4) {
850 iounmap(card->membase);
851 }
852 if (error >= 3) {
853 pci_disable_device(card->pcidev);
854 kfree(card);
855 }
856}
910 857
911static scq_info *get_scq(int size, u32 scd) 858static scq_info *get_scq(int size, u32 scd)
912{ 859{
913 scq_info *scq; 860 scq_info *scq;
914 int i; 861 int i;
915 862
916 if (size != VBR_SCQSIZE && size != CBR_SCQSIZE) 863 if (size != VBR_SCQSIZE && size != CBR_SCQSIZE)
917 return NULL; 864 return NULL;
918 865
919 scq = kmalloc(sizeof(scq_info), GFP_KERNEL); 866 scq = kmalloc(sizeof(scq_info), GFP_KERNEL);
920 if (scq == NULL) 867 if (scq == NULL)
921 return NULL; 868 return NULL;
922 scq->org = kmalloc(2 * size, GFP_KERNEL); 869 scq->org = kmalloc(2 * size, GFP_KERNEL);
923 if (scq->org == NULL) 870 if (scq->org == NULL) {
924 { 871 kfree(scq);
925 kfree(scq); 872 return NULL;
926 return NULL; 873 }
927 } 874 scq->skb = kmalloc(sizeof(struct sk_buff *) *
928 scq->skb = kmalloc(sizeof(struct sk_buff *) * 875 (size / NS_SCQE_SIZE), GFP_KERNEL);
929 (size / NS_SCQE_SIZE), GFP_KERNEL); 876 if (scq->skb == NULL) {
930 if (scq->skb == NULL) 877 kfree(scq->org);
931 { 878 kfree(scq);
932 kfree(scq->org); 879 return NULL;
933 kfree(scq); 880 }
934 return NULL; 881 scq->num_entries = size / NS_SCQE_SIZE;
935 } 882 scq->base = (ns_scqe *) ALIGN_ADDRESS(scq->org, size);
936 scq->num_entries = size / NS_SCQE_SIZE; 883 scq->next = scq->base;
937 scq->base = (ns_scqe *) ALIGN_ADDRESS(scq->org, size); 884 scq->last = scq->base + (scq->num_entries - 1);
938 scq->next = scq->base; 885 scq->tail = scq->last;
939 scq->last = scq->base + (scq->num_entries - 1); 886 scq->scd = scd;
940 scq->tail = scq->last; 887 scq->num_entries = size / NS_SCQE_SIZE;
941 scq->scd = scd; 888 scq->tbd_count = 0;
942 scq->num_entries = size / NS_SCQE_SIZE; 889 init_waitqueue_head(&scq->scqfull_waitq);
943 scq->tbd_count = 0; 890 scq->full = 0;
944 init_waitqueue_head(&scq->scqfull_waitq); 891 spin_lock_init(&scq->lock);
945 scq->full = 0; 892
946 spin_lock_init(&scq->lock); 893 for (i = 0; i < scq->num_entries; i++)
947 894 scq->skb[i] = NULL;
948 for (i = 0; i < scq->num_entries; i++) 895
949 scq->skb[i] = NULL; 896 return scq;
950
951 return scq;
952} 897}
953 898
954
955
956/* For variable rate SCQ vcc must be NULL */ 899/* For variable rate SCQ vcc must be NULL */
957static void free_scq(scq_info *scq, struct atm_vcc *vcc) 900static void free_scq(scq_info * scq, struct atm_vcc *vcc)
958{ 901{
959 int i; 902 int i;
960 903
961 if (scq->num_entries == VBR_SCQ_NUM_ENTRIES) 904 if (scq->num_entries == VBR_SCQ_NUM_ENTRIES)
962 for (i = 0; i < scq->num_entries; i++) 905 for (i = 0; i < scq->num_entries; i++) {
963 { 906 if (scq->skb[i] != NULL) {
964 if (scq->skb[i] != NULL) 907 vcc = ATM_SKB(scq->skb[i])->vcc;
965 { 908 if (vcc->pop != NULL)
966 vcc = ATM_SKB(scq->skb[i])->vcc; 909 vcc->pop(vcc, scq->skb[i]);
967 if (vcc->pop != NULL) 910 else
968 vcc->pop(vcc, scq->skb[i]); 911 dev_kfree_skb_any(scq->skb[i]);
969 else 912 }
970 dev_kfree_skb_any(scq->skb[i]); 913 } else { /* vcc must be != NULL */
971 } 914
972 } 915 if (vcc == NULL) {
973 else /* vcc must be != NULL */ 916 printk
974 { 917 ("nicstar: free_scq() called with vcc == NULL for fixed rate scq.");
975 if (vcc == NULL) 918 for (i = 0; i < scq->num_entries; i++)
976 { 919 dev_kfree_skb_any(scq->skb[i]);
977 printk("nicstar: free_scq() called with vcc == NULL for fixed rate scq."); 920 } else
978 for (i = 0; i < scq->num_entries; i++) 921 for (i = 0; i < scq->num_entries; i++) {
979 dev_kfree_skb_any(scq->skb[i]); 922 if (scq->skb[i] != NULL) {
980 } 923 if (vcc->pop != NULL)
981 else 924 vcc->pop(vcc, scq->skb[i]);
982 for (i = 0; i < scq->num_entries; i++) 925 else
983 { 926 dev_kfree_skb_any(scq->skb[i]);
984 if (scq->skb[i] != NULL) 927 }
985 { 928 }
986 if (vcc->pop != NULL) 929 }
987 vcc->pop(vcc, scq->skb[i]); 930 kfree(scq->skb);
988 else 931 kfree(scq->org);
989 dev_kfree_skb_any(scq->skb[i]); 932 kfree(scq);
990 }
991 }
992 }
993 kfree(scq->skb);
994 kfree(scq->org);
995 kfree(scq);
996} 933}
997 934
998
999
1000/* The handles passed must be pointers to the sk_buff containing the small 935/* The handles passed must be pointers to the sk_buff containing the small
1001 or large buffer(s) cast to u32. */ 936 or large buffer(s) cast to u32. */
1002static void push_rxbufs(ns_dev *card, struct sk_buff *skb) 937static void push_rxbufs(ns_dev * card, struct sk_buff *skb)
1003{ 938{
1004 struct ns_skb_cb *cb = NS_SKB_CB(skb); 939 struct ns_skb_cb *cb = NS_SKB_CB(skb);
1005 u32 handle1, addr1; 940 u32 handle1, addr1;
1006 u32 handle2, addr2; 941 u32 handle2, addr2;
1007 u32 stat; 942 u32 stat;
1008 unsigned long flags; 943 unsigned long flags;
1009 944
1010 /* *BARF* */ 945 /* *BARF* */
1011 handle2 = addr2 = 0; 946 handle2 = addr2 = 0;
1012 handle1 = (u32)skb; 947 handle1 = (u32) skb;
1013 addr1 = (u32)virt_to_bus(skb->data); 948 addr1 = (u32) virt_to_bus(skb->data);
1014 949
1015#ifdef GENERAL_DEBUG 950#ifdef GENERAL_DEBUG
1016 if (!addr1) 951 if (!addr1)
1017 printk("nicstar%d: push_rxbufs called with addr1 = 0.\n", card->index); 952 printk("nicstar%d: push_rxbufs called with addr1 = 0.\n",
953 card->index);
1018#endif /* GENERAL_DEBUG */ 954#endif /* GENERAL_DEBUG */
1019 955
1020 stat = readl(card->membase + STAT); 956 stat = readl(card->membase + STAT);
1021 card->sbfqc = ns_stat_sfbqc_get(stat); 957 card->sbfqc = ns_stat_sfbqc_get(stat);
1022 card->lbfqc = ns_stat_lfbqc_get(stat); 958 card->lbfqc = ns_stat_lfbqc_get(stat);
1023 if (cb->buf_type == BUF_SM) 959 if (cb->buf_type == BUF_SM) {
1024 { 960 if (!addr2) {
1025 if (!addr2) 961 if (card->sm_addr) {
1026 { 962 addr2 = card->sm_addr;
1027 if (card->sm_addr) 963 handle2 = card->sm_handle;
1028 { 964 card->sm_addr = 0x00000000;
1029 addr2 = card->sm_addr; 965 card->sm_handle = 0x00000000;
1030 handle2 = card->sm_handle; 966 } else { /* (!sm_addr) */
1031 card->sm_addr = 0x00000000; 967
1032 card->sm_handle = 0x00000000; 968 card->sm_addr = addr1;
1033 } 969 card->sm_handle = handle1;
1034 else /* (!sm_addr) */ 970 }
1035 { 971 }
1036 card->sm_addr = addr1; 972 } else { /* buf_type == BUF_LG */
1037 card->sm_handle = handle1; 973
1038 } 974 if (!addr2) {
1039 } 975 if (card->lg_addr) {
1040 } 976 addr2 = card->lg_addr;
1041 else /* buf_type == BUF_LG */ 977 handle2 = card->lg_handle;
1042 { 978 card->lg_addr = 0x00000000;
1043 if (!addr2) 979 card->lg_handle = 0x00000000;
1044 { 980 } else { /* (!lg_addr) */
1045 if (card->lg_addr) 981
1046 { 982 card->lg_addr = addr1;
1047 addr2 = card->lg_addr; 983 card->lg_handle = handle1;
1048 handle2 = card->lg_handle; 984 }
1049 card->lg_addr = 0x00000000; 985 }
1050 card->lg_handle = 0x00000000; 986 }
1051 } 987
1052 else /* (!lg_addr) */ 988 if (addr2) {
1053 { 989 if (cb->buf_type == BUF_SM) {
1054 card->lg_addr = addr1; 990 if (card->sbfqc >= card->sbnr.max) {
1055 card->lg_handle = handle1; 991 skb_unlink((struct sk_buff *)handle1,
1056 } 992 &card->sbpool.queue);
1057 } 993 dev_kfree_skb_any((struct sk_buff *)handle1);
1058 } 994 skb_unlink((struct sk_buff *)handle2,
1059 995 &card->sbpool.queue);
1060 if (addr2) 996 dev_kfree_skb_any((struct sk_buff *)handle2);
1061 { 997 return;
1062 if (cb->buf_type == BUF_SM) 998 } else
1063 { 999 card->sbfqc += 2;
1064 if (card->sbfqc >= card->sbnr.max) 1000 } else { /* (buf_type == BUF_LG) */
1065 { 1001
1066 skb_unlink((struct sk_buff *) handle1, &card->sbpool.queue); 1002 if (card->lbfqc >= card->lbnr.max) {
1067 dev_kfree_skb_any((struct sk_buff *) handle1); 1003 skb_unlink((struct sk_buff *)handle1,
1068 skb_unlink((struct sk_buff *) handle2, &card->sbpool.queue); 1004 &card->lbpool.queue);
1069 dev_kfree_skb_any((struct sk_buff *) handle2); 1005 dev_kfree_skb_any((struct sk_buff *)handle1);
1070 return; 1006 skb_unlink((struct sk_buff *)handle2,
1071 } 1007 &card->lbpool.queue);
1072 else 1008 dev_kfree_skb_any((struct sk_buff *)handle2);
1073 card->sbfqc += 2; 1009 return;
1074 } 1010 } else
1075 else /* (buf_type == BUF_LG) */ 1011 card->lbfqc += 2;
1076 { 1012 }
1077 if (card->lbfqc >= card->lbnr.max) 1013
1078 { 1014 spin_lock_irqsave(&card->res_lock, flags);
1079 skb_unlink((struct sk_buff *) handle1, &card->lbpool.queue); 1015
1080 dev_kfree_skb_any((struct sk_buff *) handle1); 1016 while (CMD_BUSY(card)) ;
1081 skb_unlink((struct sk_buff *) handle2, &card->lbpool.queue); 1017 writel(addr2, card->membase + DR3);
1082 dev_kfree_skb_any((struct sk_buff *) handle2); 1018 writel(handle2, card->membase + DR2);
1083 return; 1019 writel(addr1, card->membase + DR1);
1084 } 1020 writel(handle1, card->membase + DR0);
1085 else 1021 writel(NS_CMD_WRITE_FREEBUFQ | cb->buf_type,
1086 card->lbfqc += 2; 1022 card->membase + CMD);
1087 } 1023
1088 1024 spin_unlock_irqrestore(&card->res_lock, flags);
1089 spin_lock_irqsave(&card->res_lock, flags); 1025
1090 1026 XPRINTK("nicstar%d: Pushing %s buffers at 0x%x and 0x%x.\n",
1091 while (CMD_BUSY(card)); 1027 card->index,
1092 writel(addr2, card->membase + DR3); 1028 (cb->buf_type == BUF_SM ? "small" : "large"), addr1,
1093 writel(handle2, card->membase + DR2); 1029 addr2);
1094 writel(addr1, card->membase + DR1); 1030 }
1095 writel(handle1, card->membase + DR0); 1031
1096 writel(NS_CMD_WRITE_FREEBUFQ | cb->buf_type, card->membase + CMD); 1032 if (!card->efbie && card->sbfqc >= card->sbnr.min &&
1097 1033 card->lbfqc >= card->lbnr.min) {
1098 spin_unlock_irqrestore(&card->res_lock, flags); 1034 card->efbie = 1;
1099 1035 writel((readl(card->membase + CFG) | NS_CFG_EFBIE),
1100 XPRINTK("nicstar%d: Pushing %s buffers at 0x%x and 0x%x.\n", card->index, 1036 card->membase + CFG);
1101 (cb->buf_type == BUF_SM ? "small" : "large"), addr1, addr2); 1037 }
1102 } 1038
1103 1039 return;
1104 if (!card->efbie && card->sbfqc >= card->sbnr.min &&
1105 card->lbfqc >= card->lbnr.min)
1106 {
1107 card->efbie = 1;
1108 writel((readl(card->membase + CFG) | NS_CFG_EFBIE), card->membase + CFG);
1109 }
1110
1111 return;
1112} 1040}
1113 1041
1114
1115
1116static irqreturn_t ns_irq_handler(int irq, void *dev_id) 1042static irqreturn_t ns_irq_handler(int irq, void *dev_id)
1117{ 1043{
1118 u32 stat_r; 1044 u32 stat_r;
1119 ns_dev *card; 1045 ns_dev *card;
1120 struct atm_dev *dev; 1046 struct atm_dev *dev;
1121 unsigned long flags; 1047 unsigned long flags;
1122 1048
1123 card = (ns_dev *) dev_id; 1049 card = (ns_dev *) dev_id;
1124 dev = card->atmdev; 1050 dev = card->atmdev;
1125 card->intcnt++; 1051 card->intcnt++;
1126 1052
1127 PRINTK("nicstar%d: NICStAR generated an interrupt\n", card->index); 1053 PRINTK("nicstar%d: NICStAR generated an interrupt\n", card->index);
1128 1054
1129 spin_lock_irqsave(&card->int_lock, flags); 1055 spin_lock_irqsave(&card->int_lock, flags);
1130 1056
1131 stat_r = readl(card->membase + STAT); 1057 stat_r = readl(card->membase + STAT);
1132 1058
1133 /* Transmit Status Indicator has been written to T. S. Queue */ 1059 /* Transmit Status Indicator has been written to T. S. Queue */
1134 if (stat_r & NS_STAT_TSIF) 1060 if (stat_r & NS_STAT_TSIF) {
1135 { 1061 TXPRINTK("nicstar%d: TSI interrupt\n", card->index);
1136 TXPRINTK("nicstar%d: TSI interrupt\n", card->index); 1062 process_tsq(card);
1137 process_tsq(card); 1063 writel(NS_STAT_TSIF, card->membase + STAT);
1138 writel(NS_STAT_TSIF, card->membase + STAT); 1064 }
1139 } 1065
1140 1066 /* Incomplete CS-PDU has been transmitted */
1141 /* Incomplete CS-PDU has been transmitted */ 1067 if (stat_r & NS_STAT_TXICP) {
1142 if (stat_r & NS_STAT_TXICP) 1068 writel(NS_STAT_TXICP, card->membase + STAT);
1143 { 1069 TXPRINTK("nicstar%d: Incomplete CS-PDU transmitted.\n",
1144 writel(NS_STAT_TXICP, card->membase + STAT); 1070 card->index);
1145 TXPRINTK("nicstar%d: Incomplete CS-PDU transmitted.\n", 1071 }
1146 card->index); 1072
1147 } 1073 /* Transmit Status Queue 7/8 full */
1148 1074 if (stat_r & NS_STAT_TSQF) {
1149 /* Transmit Status Queue 7/8 full */ 1075 writel(NS_STAT_TSQF, card->membase + STAT);
1150 if (stat_r & NS_STAT_TSQF) 1076 PRINTK("nicstar%d: TSQ full.\n", card->index);
1151 { 1077 process_tsq(card);
1152 writel(NS_STAT_TSQF, card->membase + STAT); 1078 }
1153 PRINTK("nicstar%d: TSQ full.\n", card->index); 1079
1154 process_tsq(card); 1080 /* Timer overflow */
1155 } 1081 if (stat_r & NS_STAT_TMROF) {
1156 1082 writel(NS_STAT_TMROF, card->membase + STAT);
1157 /* Timer overflow */ 1083 PRINTK("nicstar%d: Timer overflow.\n", card->index);
1158 if (stat_r & NS_STAT_TMROF) 1084 }
1159 { 1085
1160 writel(NS_STAT_TMROF, card->membase + STAT); 1086 /* PHY device interrupt signal active */
1161 PRINTK("nicstar%d: Timer overflow.\n", card->index); 1087 if (stat_r & NS_STAT_PHYI) {
1162 } 1088 writel(NS_STAT_PHYI, card->membase + STAT);
1163 1089 PRINTK("nicstar%d: PHY interrupt.\n", card->index);
1164 /* PHY device interrupt signal active */ 1090 if (dev->phy && dev->phy->interrupt) {
1165 if (stat_r & NS_STAT_PHYI) 1091 dev->phy->interrupt(dev);
1166 { 1092 }
1167 writel(NS_STAT_PHYI, card->membase + STAT); 1093 }
1168 PRINTK("nicstar%d: PHY interrupt.\n", card->index); 1094
1169 if (dev->phy && dev->phy->interrupt) { 1095 /* Small Buffer Queue is full */
1170 dev->phy->interrupt(dev); 1096 if (stat_r & NS_STAT_SFBQF) {
1171 } 1097 writel(NS_STAT_SFBQF, card->membase + STAT);
1172 } 1098 printk("nicstar%d: Small free buffer queue is full.\n",
1173 1099 card->index);
1174 /* Small Buffer Queue is full */ 1100 }
1175 if (stat_r & NS_STAT_SFBQF) 1101
1176 { 1102 /* Large Buffer Queue is full */
1177 writel(NS_STAT_SFBQF, card->membase + STAT); 1103 if (stat_r & NS_STAT_LFBQF) {
1178 printk("nicstar%d: Small free buffer queue is full.\n", card->index); 1104 writel(NS_STAT_LFBQF, card->membase + STAT);
1179 } 1105 printk("nicstar%d: Large free buffer queue is full.\n",
1180 1106 card->index);
1181 /* Large Buffer Queue is full */ 1107 }
1182 if (stat_r & NS_STAT_LFBQF) 1108
1183 { 1109 /* Receive Status Queue is full */
1184 writel(NS_STAT_LFBQF, card->membase + STAT); 1110 if (stat_r & NS_STAT_RSQF) {
1185 printk("nicstar%d: Large free buffer queue is full.\n", card->index); 1111 writel(NS_STAT_RSQF, card->membase + STAT);
1186 } 1112 printk("nicstar%d: RSQ full.\n", card->index);
1187 1113 process_rsq(card);
1188 /* Receive Status Queue is full */ 1114 }
1189 if (stat_r & NS_STAT_RSQF) 1115
1190 { 1116 /* Complete CS-PDU received */
1191 writel(NS_STAT_RSQF, card->membase + STAT); 1117 if (stat_r & NS_STAT_EOPDU) {
1192 printk("nicstar%d: RSQ full.\n", card->index); 1118 RXPRINTK("nicstar%d: End of CS-PDU received.\n", card->index);
1193 process_rsq(card); 1119 process_rsq(card);
1194 } 1120 writel(NS_STAT_EOPDU, card->membase + STAT);
1195 1121 }
1196 /* Complete CS-PDU received */ 1122
1197 if (stat_r & NS_STAT_EOPDU) 1123 /* Raw cell received */
1198 { 1124 if (stat_r & NS_STAT_RAWCF) {
1199 RXPRINTK("nicstar%d: End of CS-PDU received.\n", card->index); 1125 writel(NS_STAT_RAWCF, card->membase + STAT);
1200 process_rsq(card);
1201 writel(NS_STAT_EOPDU, card->membase + STAT);
1202 }
1203
1204 /* Raw cell received */
1205 if (stat_r & NS_STAT_RAWCF)
1206 {
1207 writel(NS_STAT_RAWCF, card->membase + STAT);
1208#ifndef RCQ_SUPPORT 1126#ifndef RCQ_SUPPORT
1209 printk("nicstar%d: Raw cell received and no support yet...\n", 1127 printk("nicstar%d: Raw cell received and no support yet...\n",
1210 card->index); 1128 card->index);
1211#endif /* RCQ_SUPPORT */ 1129#endif /* RCQ_SUPPORT */
1212 /* NOTE: the following procedure may keep a raw cell pending until the 1130 /* NOTE: the following procedure may keep a raw cell pending until the
1213 next interrupt. As this preliminary support is only meant to 1131 next interrupt. As this preliminary support is only meant to
1214 avoid buffer leakage, this is not an issue. */ 1132 avoid buffer leakage, this is not an issue. */
1215 while (readl(card->membase + RAWCT) != card->rawch) 1133 while (readl(card->membase + RAWCT) != card->rawch) {
1216 { 1134 ns_rcqe *rawcell;
1217 ns_rcqe *rawcell; 1135
1218 1136 rawcell = (ns_rcqe *) bus_to_virt(card->rawch);
1219 rawcell = (ns_rcqe *) bus_to_virt(card->rawch); 1137 if (ns_rcqe_islast(rawcell)) {
1220 if (ns_rcqe_islast(rawcell)) 1138 struct sk_buff *oldbuf;
1221 { 1139
1222 struct sk_buff *oldbuf; 1140 oldbuf = card->rcbuf;
1223 1141 card->rcbuf =
1224 oldbuf = card->rcbuf; 1142 (struct sk_buff *)
1225 card->rcbuf = (struct sk_buff *) ns_rcqe_nextbufhandle(rawcell); 1143 ns_rcqe_nextbufhandle(rawcell);
1226 card->rawch = (u32) virt_to_bus(card->rcbuf->data); 1144 card->rawch =
1227 recycle_rx_buf(card, oldbuf); 1145 (u32) virt_to_bus(card->rcbuf->data);
1228 } 1146 recycle_rx_buf(card, oldbuf);
1229 else 1147 } else
1230 card->rawch += NS_RCQE_SIZE; 1148 card->rawch += NS_RCQE_SIZE;
1231 } 1149 }
1232 } 1150 }
1233 1151
1234 /* Small buffer queue is empty */ 1152 /* Small buffer queue is empty */
1235 if (stat_r & NS_STAT_SFBQE) 1153 if (stat_r & NS_STAT_SFBQE) {
1236 { 1154 int i;
1237 int i; 1155 struct sk_buff *sb;
1238 struct sk_buff *sb; 1156
1239 1157 writel(NS_STAT_SFBQE, card->membase + STAT);
1240 writel(NS_STAT_SFBQE, card->membase + STAT); 1158 printk("nicstar%d: Small free buffer queue empty.\n",
1241 printk("nicstar%d: Small free buffer queue empty.\n", 1159 card->index);
1242 card->index); 1160 for (i = 0; i < card->sbnr.min; i++) {
1243 for (i = 0; i < card->sbnr.min; i++) 1161 sb = dev_alloc_skb(NS_SMSKBSIZE);
1244 { 1162 if (sb == NULL) {
1245 sb = dev_alloc_skb(NS_SMSKBSIZE); 1163 writel(readl(card->membase + CFG) &
1246 if (sb == NULL) 1164 ~NS_CFG_EFBIE, card->membase + CFG);
1247 { 1165 card->efbie = 0;
1248 writel(readl(card->membase + CFG) & ~NS_CFG_EFBIE, card->membase + CFG); 1166 break;
1249 card->efbie = 0; 1167 }
1250 break; 1168 NS_SKB_CB(sb)->buf_type = BUF_SM;
1251 } 1169 skb_queue_tail(&card->sbpool.queue, sb);
1252 NS_SKB_CB(sb)->buf_type = BUF_SM; 1170 skb_reserve(sb, NS_AAL0_HEADER);
1253 skb_queue_tail(&card->sbpool.queue, sb); 1171 push_rxbufs(card, sb);
1254 skb_reserve(sb, NS_AAL0_HEADER); 1172 }
1255 push_rxbufs(card, sb); 1173 card->sbfqc = i;
1256 } 1174 process_rsq(card);
1257 card->sbfqc = i; 1175 }
1258 process_rsq(card); 1176
1259 } 1177 /* Large buffer queue empty */
1260 1178 if (stat_r & NS_STAT_LFBQE) {
1261 /* Large buffer queue empty */ 1179 int i;
1262 if (stat_r & NS_STAT_LFBQE) 1180 struct sk_buff *lb;
1263 { 1181
1264 int i; 1182 writel(NS_STAT_LFBQE, card->membase + STAT);
1265 struct sk_buff *lb; 1183 printk("nicstar%d: Large free buffer queue empty.\n",
1266 1184 card->index);
1267 writel(NS_STAT_LFBQE, card->membase + STAT); 1185 for (i = 0; i < card->lbnr.min; i++) {
1268 printk("nicstar%d: Large free buffer queue empty.\n", 1186 lb = dev_alloc_skb(NS_LGSKBSIZE);
1269 card->index); 1187 if (lb == NULL) {
1270 for (i = 0; i < card->lbnr.min; i++) 1188 writel(readl(card->membase + CFG) &
1271 { 1189 ~NS_CFG_EFBIE, card->membase + CFG);
1272 lb = dev_alloc_skb(NS_LGSKBSIZE); 1190 card->efbie = 0;
1273 if (lb == NULL) 1191 break;
1274 { 1192 }
1275 writel(readl(card->membase + CFG) & ~NS_CFG_EFBIE, card->membase + CFG); 1193 NS_SKB_CB(lb)->buf_type = BUF_LG;
1276 card->efbie = 0; 1194 skb_queue_tail(&card->lbpool.queue, lb);
1277 break; 1195 skb_reserve(lb, NS_SMBUFSIZE);
1278 } 1196 push_rxbufs(card, lb);
1279 NS_SKB_CB(lb)->buf_type = BUF_LG; 1197 }
1280 skb_queue_tail(&card->lbpool.queue, lb); 1198 card->lbfqc = i;
1281 skb_reserve(lb, NS_SMBUFSIZE); 1199 process_rsq(card);
1282 push_rxbufs(card, lb); 1200 }
1283 } 1201
1284 card->lbfqc = i; 1202 /* Receive Status Queue is 7/8 full */
1285 process_rsq(card); 1203 if (stat_r & NS_STAT_RSQAF) {
1286 } 1204 writel(NS_STAT_RSQAF, card->membase + STAT);
1287 1205 RXPRINTK("nicstar%d: RSQ almost full.\n", card->index);
1288 /* Receive Status Queue is 7/8 full */ 1206 process_rsq(card);
1289 if (stat_r & NS_STAT_RSQAF) 1207 }
1290 { 1208
1291 writel(NS_STAT_RSQAF, card->membase + STAT); 1209 spin_unlock_irqrestore(&card->int_lock, flags);
1292 RXPRINTK("nicstar%d: RSQ almost full.\n", card->index); 1210 PRINTK("nicstar%d: end of interrupt service\n", card->index);
1293 process_rsq(card); 1211 return IRQ_HANDLED;
1294 }
1295
1296 spin_unlock_irqrestore(&card->int_lock, flags);
1297 PRINTK("nicstar%d: end of interrupt service\n", card->index);
1298 return IRQ_HANDLED;
1299} 1212}
1300 1213
1301
1302
1303static int ns_open(struct atm_vcc *vcc) 1214static int ns_open(struct atm_vcc *vcc)
1304{ 1215{
1305 ns_dev *card; 1216 ns_dev *card;
1306 vc_map *vc; 1217 vc_map *vc;
1307 unsigned long tmpl, modl; 1218 unsigned long tmpl, modl;
1308 int tcr, tcra; /* target cell rate, and absolute value */ 1219 int tcr, tcra; /* target cell rate, and absolute value */
1309 int n = 0; /* Number of entries in the TST. Initialized to remove 1220 int n = 0; /* Number of entries in the TST. Initialized to remove
1310 the compiler warning. */ 1221 the compiler warning. */
1311 u32 u32d[4]; 1222 u32 u32d[4];
1312 int frscdi = 0; /* Index of the SCD. Initialized to remove the compiler 1223 int frscdi = 0; /* Index of the SCD. Initialized to remove the compiler
1313 warning. How I wish compilers were clever enough to 1224 warning. How I wish compilers were clever enough to
1314 tell which variables can truly be used 1225 tell which variables can truly be used
1315 uninitialized... */ 1226 uninitialized... */
1316 int inuse; /* tx or rx vc already in use by another vcc */ 1227 int inuse; /* tx or rx vc already in use by another vcc */
1317 short vpi = vcc->vpi; 1228 short vpi = vcc->vpi;
1318 int vci = vcc->vci; 1229 int vci = vcc->vci;
1319 1230
1320 card = (ns_dev *) vcc->dev->dev_data; 1231 card = (ns_dev *) vcc->dev->dev_data;
1321 PRINTK("nicstar%d: opening vpi.vci %d.%d \n", card->index, (int) vpi, vci); 1232 PRINTK("nicstar%d: opening vpi.vci %d.%d \n", card->index, (int)vpi,
1322 if (vcc->qos.aal != ATM_AAL5 && vcc->qos.aal != ATM_AAL0) 1233 vci);
1323 { 1234 if (vcc->qos.aal != ATM_AAL5 && vcc->qos.aal != ATM_AAL0) {
1324 PRINTK("nicstar%d: unsupported AAL.\n", card->index); 1235 PRINTK("nicstar%d: unsupported AAL.\n", card->index);
1325 return -EINVAL; 1236 return -EINVAL;
1326 } 1237 }
1327 1238
1328 vc = &(card->vcmap[vpi << card->vcibits | vci]); 1239 vc = &(card->vcmap[vpi << card->vcibits | vci]);
1329 vcc->dev_data = vc; 1240 vcc->dev_data = vc;
1330 1241
1331 inuse = 0; 1242 inuse = 0;
1332 if (vcc->qos.txtp.traffic_class != ATM_NONE && vc->tx) 1243 if (vcc->qos.txtp.traffic_class != ATM_NONE && vc->tx)
1333 inuse = 1; 1244 inuse = 1;
1334 if (vcc->qos.rxtp.traffic_class != ATM_NONE && vc->rx) 1245 if (vcc->qos.rxtp.traffic_class != ATM_NONE && vc->rx)
1335 inuse += 2; 1246 inuse += 2;
1336 if (inuse) 1247 if (inuse) {
1337 { 1248 printk("nicstar%d: %s vci already in use.\n", card->index,
1338 printk("nicstar%d: %s vci already in use.\n", card->index, 1249 inuse == 1 ? "tx" : inuse == 2 ? "rx" : "tx and rx");
1339 inuse == 1 ? "tx" : inuse == 2 ? "rx" : "tx and rx"); 1250 return -EINVAL;
1340 return -EINVAL; 1251 }
1341 } 1252
1342 1253 set_bit(ATM_VF_ADDR, &vcc->flags);
1343 set_bit(ATM_VF_ADDR,&vcc->flags); 1254
1344 1255 /* NOTE: You are not allowed to modify an open connection's QOS. To change
1345 /* NOTE: You are not allowed to modify an open connection's QOS. To change 1256 that, remove the ATM_VF_PARTIAL flag checking. There may be other changes
1346 that, remove the ATM_VF_PARTIAL flag checking. There may be other changes 1257 needed to do that. */
1347 needed to do that. */ 1258 if (!test_bit(ATM_VF_PARTIAL, &vcc->flags)) {
1348 if (!test_bit(ATM_VF_PARTIAL,&vcc->flags)) 1259 scq_info *scq;
1349 { 1260
1350 scq_info *scq; 1261 set_bit(ATM_VF_PARTIAL, &vcc->flags);
1351 1262 if (vcc->qos.txtp.traffic_class == ATM_CBR) {
1352 set_bit(ATM_VF_PARTIAL,&vcc->flags); 1263 /* Check requested cell rate and availability of SCD */
1353 if (vcc->qos.txtp.traffic_class == ATM_CBR) 1264 if (vcc->qos.txtp.max_pcr == 0 && vcc->qos.txtp.pcr == 0
1354 { 1265 && vcc->qos.txtp.min_pcr == 0) {
1355 /* Check requested cell rate and availability of SCD */ 1266 PRINTK
1356 if (vcc->qos.txtp.max_pcr == 0 && vcc->qos.txtp.pcr == 0 && 1267 ("nicstar%d: trying to open a CBR vc with cell rate = 0 \n",
1357 vcc->qos.txtp.min_pcr == 0) 1268 card->index);
1358 { 1269 clear_bit(ATM_VF_PARTIAL, &vcc->flags);
1359 PRINTK("nicstar%d: trying to open a CBR vc with cell rate = 0 \n", 1270 clear_bit(ATM_VF_ADDR, &vcc->flags);
1360 card->index); 1271 return -EINVAL;
1361 clear_bit(ATM_VF_PARTIAL,&vcc->flags); 1272 }
1362 clear_bit(ATM_VF_ADDR,&vcc->flags); 1273
1363 return -EINVAL; 1274 tcr = atm_pcr_goal(&(vcc->qos.txtp));
1364 } 1275 tcra = tcr >= 0 ? tcr : -tcr;
1365 1276
1366 tcr = atm_pcr_goal(&(vcc->qos.txtp)); 1277 PRINTK("nicstar%d: target cell rate = %d.\n",
1367 tcra = tcr >= 0 ? tcr : -tcr; 1278 card->index, vcc->qos.txtp.max_pcr);
1368 1279
1369 PRINTK("nicstar%d: target cell rate = %d.\n", card->index, 1280 tmpl =
1370 vcc->qos.txtp.max_pcr); 1281 (unsigned long)tcra *(unsigned long)
1371 1282 NS_TST_NUM_ENTRIES;
1372 tmpl = (unsigned long)tcra * (unsigned long)NS_TST_NUM_ENTRIES; 1283 modl = tmpl % card->max_pcr;
1373 modl = tmpl % card->max_pcr; 1284
1374 1285 n = (int)(tmpl / card->max_pcr);
1375 n = (int)(tmpl / card->max_pcr); 1286 if (tcr > 0) {
1376 if (tcr > 0) 1287 if (modl > 0)
1377 { 1288 n++;
1378 if (modl > 0) n++; 1289 } else if (tcr == 0) {
1379 } 1290 if ((n =
1380 else if (tcr == 0) 1291 (card->tst_free_entries -
1381 { 1292 NS_TST_RESERVED)) <= 0) {
1382 if ((n = (card->tst_free_entries - NS_TST_RESERVED)) <= 0) 1293 PRINTK
1383 { 1294 ("nicstar%d: no CBR bandwidth free.\n",
1384 PRINTK("nicstar%d: no CBR bandwidth free.\n", card->index); 1295 card->index);
1385 clear_bit(ATM_VF_PARTIAL,&vcc->flags); 1296 clear_bit(ATM_VF_PARTIAL, &vcc->flags);
1386 clear_bit(ATM_VF_ADDR,&vcc->flags); 1297 clear_bit(ATM_VF_ADDR, &vcc->flags);
1387 return -EINVAL; 1298 return -EINVAL;
1388 } 1299 }
1389 } 1300 }
1390 1301
1391 if (n == 0) 1302 if (n == 0) {
1392 { 1303 printk
1393 printk("nicstar%d: selected bandwidth < granularity.\n", card->index); 1304 ("nicstar%d: selected bandwidth < granularity.\n",
1394 clear_bit(ATM_VF_PARTIAL,&vcc->flags); 1305 card->index);
1395 clear_bit(ATM_VF_ADDR,&vcc->flags); 1306 clear_bit(ATM_VF_PARTIAL, &vcc->flags);
1396 return -EINVAL; 1307 clear_bit(ATM_VF_ADDR, &vcc->flags);
1397 } 1308 return -EINVAL;
1398 1309 }
1399 if (n > (card->tst_free_entries - NS_TST_RESERVED)) 1310
1400 { 1311 if (n > (card->tst_free_entries - NS_TST_RESERVED)) {
1401 PRINTK("nicstar%d: not enough free CBR bandwidth.\n", card->index); 1312 PRINTK
1402 clear_bit(ATM_VF_PARTIAL,&vcc->flags); 1313 ("nicstar%d: not enough free CBR bandwidth.\n",
1403 clear_bit(ATM_VF_ADDR,&vcc->flags); 1314 card->index);
1404 return -EINVAL; 1315 clear_bit(ATM_VF_PARTIAL, &vcc->flags);
1405 } 1316 clear_bit(ATM_VF_ADDR, &vcc->flags);
1406 else 1317 return -EINVAL;
1407 card->tst_free_entries -= n; 1318 } else
1408 1319 card->tst_free_entries -= n;
1409 XPRINTK("nicstar%d: writing %d tst entries.\n", card->index, n); 1320
1410 for (frscdi = 0; frscdi < NS_FRSCD_NUM; frscdi++) 1321 XPRINTK("nicstar%d: writing %d tst entries.\n",
1411 { 1322 card->index, n);
1412 if (card->scd2vc[frscdi] == NULL) 1323 for (frscdi = 0; frscdi < NS_FRSCD_NUM; frscdi++) {
1413 { 1324 if (card->scd2vc[frscdi] == NULL) {
1414 card->scd2vc[frscdi] = vc; 1325 card->scd2vc[frscdi] = vc;
1415 break; 1326 break;
1416 } 1327 }
1417 } 1328 }
1418 if (frscdi == NS_FRSCD_NUM) 1329 if (frscdi == NS_FRSCD_NUM) {
1419 { 1330 PRINTK
1420 PRINTK("nicstar%d: no SCD available for CBR channel.\n", card->index); 1331 ("nicstar%d: no SCD available for CBR channel.\n",
1421 card->tst_free_entries += n; 1332 card->index);
1422 clear_bit(ATM_VF_PARTIAL,&vcc->flags); 1333 card->tst_free_entries += n;
1423 clear_bit(ATM_VF_ADDR,&vcc->flags); 1334 clear_bit(ATM_VF_PARTIAL, &vcc->flags);
1424 return -EBUSY; 1335 clear_bit(ATM_VF_ADDR, &vcc->flags);
1425 } 1336 return -EBUSY;
1426 1337 }
1427 vc->cbr_scd = NS_FRSCD + frscdi * NS_FRSCD_SIZE; 1338
1428 1339 vc->cbr_scd = NS_FRSCD + frscdi * NS_FRSCD_SIZE;
1429 scq = get_scq(CBR_SCQSIZE, vc->cbr_scd); 1340
1430 if (scq == NULL) 1341 scq = get_scq(CBR_SCQSIZE, vc->cbr_scd);
1431 { 1342 if (scq == NULL) {
1432 PRINTK("nicstar%d: can't get fixed rate SCQ.\n", card->index); 1343 PRINTK("nicstar%d: can't get fixed rate SCQ.\n",
1433 card->scd2vc[frscdi] = NULL; 1344 card->index);
1434 card->tst_free_entries += n; 1345 card->scd2vc[frscdi] = NULL;
1435 clear_bit(ATM_VF_PARTIAL,&vcc->flags); 1346 card->tst_free_entries += n;
1436 clear_bit(ATM_VF_ADDR,&vcc->flags); 1347 clear_bit(ATM_VF_PARTIAL, &vcc->flags);
1437 return -ENOMEM; 1348 clear_bit(ATM_VF_ADDR, &vcc->flags);
1438 } 1349 return -ENOMEM;
1439 vc->scq = scq; 1350 }
1440 u32d[0] = (u32) virt_to_bus(scq->base); 1351 vc->scq = scq;
1441 u32d[1] = (u32) 0x00000000; 1352 u32d[0] = (u32) virt_to_bus(scq->base);
1442 u32d[2] = (u32) 0xffffffff; 1353 u32d[1] = (u32) 0x00000000;
1443 u32d[3] = (u32) 0x00000000; 1354 u32d[2] = (u32) 0xffffffff;
1444 ns_write_sram(card, vc->cbr_scd, u32d, 4); 1355 u32d[3] = (u32) 0x00000000;
1445 1356 ns_write_sram(card, vc->cbr_scd, u32d, 4);
1446 fill_tst(card, n, vc); 1357
1447 } 1358 fill_tst(card, n, vc);
1448 else if (vcc->qos.txtp.traffic_class == ATM_UBR) 1359 } else if (vcc->qos.txtp.traffic_class == ATM_UBR) {
1449 { 1360 vc->cbr_scd = 0x00000000;
1450 vc->cbr_scd = 0x00000000; 1361 vc->scq = card->scq0;
1451 vc->scq = card->scq0; 1362 }
1452 } 1363
1453 1364 if (vcc->qos.txtp.traffic_class != ATM_NONE) {
1454 if (vcc->qos.txtp.traffic_class != ATM_NONE) 1365 vc->tx = 1;
1455 { 1366 vc->tx_vcc = vcc;
1456 vc->tx = 1; 1367 vc->tbd_count = 0;
1457 vc->tx_vcc = vcc; 1368 }
1458 vc->tbd_count = 0; 1369 if (vcc->qos.rxtp.traffic_class != ATM_NONE) {
1459 } 1370 u32 status;
1460 if (vcc->qos.rxtp.traffic_class != ATM_NONE) 1371
1461 { 1372 vc->rx = 1;
1462 u32 status; 1373 vc->rx_vcc = vcc;
1463 1374 vc->rx_iov = NULL;
1464 vc->rx = 1; 1375
1465 vc->rx_vcc = vcc; 1376 /* Open the connection in hardware */
1466 vc->rx_iov = NULL; 1377 if (vcc->qos.aal == ATM_AAL5)
1467 1378 status = NS_RCTE_AAL5 | NS_RCTE_CONNECTOPEN;
1468 /* Open the connection in hardware */ 1379 else /* vcc->qos.aal == ATM_AAL0 */
1469 if (vcc->qos.aal == ATM_AAL5) 1380 status = NS_RCTE_AAL0 | NS_RCTE_CONNECTOPEN;
1470 status = NS_RCTE_AAL5 | NS_RCTE_CONNECTOPEN;
1471 else /* vcc->qos.aal == ATM_AAL0 */
1472 status = NS_RCTE_AAL0 | NS_RCTE_CONNECTOPEN;
1473#ifdef RCQ_SUPPORT 1381#ifdef RCQ_SUPPORT
1474 status |= NS_RCTE_RAWCELLINTEN; 1382 status |= NS_RCTE_RAWCELLINTEN;
1475#endif /* RCQ_SUPPORT */ 1383#endif /* RCQ_SUPPORT */
1476 ns_write_sram(card, NS_RCT + (vpi << card->vcibits | vci) * 1384 ns_write_sram(card,
1477 NS_RCT_ENTRY_SIZE, &status, 1); 1385 NS_RCT +
1478 } 1386 (vpi << card->vcibits | vci) *
1479 1387 NS_RCT_ENTRY_SIZE, &status, 1);
1480 } 1388 }
1481
1482 set_bit(ATM_VF_READY,&vcc->flags);
1483 return 0;
1484}
1485 1389
1390 }
1486 1391
1392 set_bit(ATM_VF_READY, &vcc->flags);
1393 return 0;
1394}
1487 1395
1488static void ns_close(struct atm_vcc *vcc) 1396static void ns_close(struct atm_vcc *vcc)
1489{ 1397{
1490 vc_map *vc; 1398 vc_map *vc;
1491 ns_dev *card; 1399 ns_dev *card;
1492 u32 data; 1400 u32 data;
1493 int i; 1401 int i;
1494 1402
1495 vc = vcc->dev_data; 1403 vc = vcc->dev_data;
1496 card = vcc->dev->dev_data; 1404 card = vcc->dev->dev_data;
1497 PRINTK("nicstar%d: closing vpi.vci %d.%d \n", card->index, 1405 PRINTK("nicstar%d: closing vpi.vci %d.%d \n", card->index,
1498 (int) vcc->vpi, vcc->vci); 1406 (int)vcc->vpi, vcc->vci);
1499 1407
1500 clear_bit(ATM_VF_READY,&vcc->flags); 1408 clear_bit(ATM_VF_READY, &vcc->flags);
1501 1409
1502 if (vcc->qos.rxtp.traffic_class != ATM_NONE) 1410 if (vcc->qos.rxtp.traffic_class != ATM_NONE) {
1503 { 1411 u32 addr;
1504 u32 addr; 1412 unsigned long flags;
1505 unsigned long flags; 1413
1506 1414 addr =
1507 addr = NS_RCT + (vcc->vpi << card->vcibits | vcc->vci) * NS_RCT_ENTRY_SIZE; 1415 NS_RCT +
1508 spin_lock_irqsave(&card->res_lock, flags); 1416 (vcc->vpi << card->vcibits | vcc->vci) * NS_RCT_ENTRY_SIZE;
1509 while(CMD_BUSY(card)); 1417 spin_lock_irqsave(&card->res_lock, flags);
1510 writel(NS_CMD_CLOSE_CONNECTION | addr << 2, card->membase + CMD); 1418 while (CMD_BUSY(card)) ;
1511 spin_unlock_irqrestore(&card->res_lock, flags); 1419 writel(NS_CMD_CLOSE_CONNECTION | addr << 2,
1512 1420 card->membase + CMD);
1513 vc->rx = 0; 1421 spin_unlock_irqrestore(&card->res_lock, flags);
1514 if (vc->rx_iov != NULL) 1422
1515 { 1423 vc->rx = 0;
1516 struct sk_buff *iovb; 1424 if (vc->rx_iov != NULL) {
1517 u32 stat; 1425 struct sk_buff *iovb;
1518 1426 u32 stat;
1519 stat = readl(card->membase + STAT); 1427
1520 card->sbfqc = ns_stat_sfbqc_get(stat); 1428 stat = readl(card->membase + STAT);
1521 card->lbfqc = ns_stat_lfbqc_get(stat); 1429 card->sbfqc = ns_stat_sfbqc_get(stat);
1522 1430 card->lbfqc = ns_stat_lfbqc_get(stat);
1523 PRINTK("nicstar%d: closing a VC with pending rx buffers.\n", 1431
1524 card->index); 1432 PRINTK
1525 iovb = vc->rx_iov; 1433 ("nicstar%d: closing a VC with pending rx buffers.\n",
1526 recycle_iovec_rx_bufs(card, (struct iovec *) iovb->data, 1434 card->index);
1527 NS_SKB(iovb)->iovcnt); 1435 iovb = vc->rx_iov;
1528 NS_SKB(iovb)->iovcnt = 0; 1436 recycle_iovec_rx_bufs(card, (struct iovec *)iovb->data,
1529 NS_SKB(iovb)->vcc = NULL; 1437 NS_SKB(iovb)->iovcnt);
1530 spin_lock_irqsave(&card->int_lock, flags); 1438 NS_SKB(iovb)->iovcnt = 0;
1531 recycle_iov_buf(card, iovb); 1439 NS_SKB(iovb)->vcc = NULL;
1532 spin_unlock_irqrestore(&card->int_lock, flags); 1440 spin_lock_irqsave(&card->int_lock, flags);
1533 vc->rx_iov = NULL; 1441 recycle_iov_buf(card, iovb);
1534 } 1442 spin_unlock_irqrestore(&card->int_lock, flags);
1535 } 1443 vc->rx_iov = NULL;
1536 1444 }
1537 if (vcc->qos.txtp.traffic_class != ATM_NONE) 1445 }
1538 { 1446
1539 vc->tx = 0; 1447 if (vcc->qos.txtp.traffic_class != ATM_NONE) {
1540 } 1448 vc->tx = 0;
1541 1449 }
1542 if (vcc->qos.txtp.traffic_class == ATM_CBR) 1450
1543 { 1451 if (vcc->qos.txtp.traffic_class == ATM_CBR) {
1544 unsigned long flags; 1452 unsigned long flags;
1545 ns_scqe *scqep; 1453 ns_scqe *scqep;
1546 scq_info *scq; 1454 scq_info *scq;
1547 1455
1548 scq = vc->scq; 1456 scq = vc->scq;
1549 1457
1550 for (;;) 1458 for (;;) {
1551 { 1459 spin_lock_irqsave(&scq->lock, flags);
1552 spin_lock_irqsave(&scq->lock, flags); 1460 scqep = scq->next;
1553 scqep = scq->next; 1461 if (scqep == scq->base)
1554 if (scqep == scq->base) 1462 scqep = scq->last;
1555 scqep = scq->last; 1463 else
1556 else 1464 scqep--;
1557 scqep--; 1465 if (scqep == scq->tail) {
1558 if (scqep == scq->tail) 1466 spin_unlock_irqrestore(&scq->lock, flags);
1559 { 1467 break;
1560 spin_unlock_irqrestore(&scq->lock, flags); 1468 }
1561 break; 1469 /* If the last entry is not a TSR, place one in the SCQ in order to
1562 } 1470 be able to completely drain it and then close. */
1563 /* If the last entry is not a TSR, place one in the SCQ in order to 1471 if (!ns_scqe_is_tsr(scqep) && scq->tail != scq->next) {
1564 be able to completely drain it and then close. */ 1472 ns_scqe tsr;
1565 if (!ns_scqe_is_tsr(scqep) && scq->tail != scq->next) 1473 u32 scdi, scqi;
1566 { 1474 u32 data;
1567 ns_scqe tsr; 1475 int index;
1568 u32 scdi, scqi; 1476
1569 u32 data; 1477 tsr.word_1 = ns_tsr_mkword_1(NS_TSR_INTENABLE);
1570 int index; 1478 scdi = (vc->cbr_scd - NS_FRSCD) / NS_FRSCD_SIZE;
1571 1479 scqi = scq->next - scq->base;
1572 tsr.word_1 = ns_tsr_mkword_1(NS_TSR_INTENABLE); 1480 tsr.word_2 = ns_tsr_mkword_2(scdi, scqi);
1573 scdi = (vc->cbr_scd - NS_FRSCD) / NS_FRSCD_SIZE; 1481 tsr.word_3 = 0x00000000;
1574 scqi = scq->next - scq->base; 1482 tsr.word_4 = 0x00000000;
1575 tsr.word_2 = ns_tsr_mkword_2(scdi, scqi); 1483 *scq->next = tsr;
1576 tsr.word_3 = 0x00000000; 1484 index = (int)scqi;
1577 tsr.word_4 = 0x00000000; 1485 scq->skb[index] = NULL;
1578 *scq->next = tsr; 1486 if (scq->next == scq->last)
1579 index = (int) scqi; 1487 scq->next = scq->base;
1580 scq->skb[index] = NULL; 1488 else
1581 if (scq->next == scq->last) 1489 scq->next++;
1582 scq->next = scq->base; 1490 data = (u32) virt_to_bus(scq->next);
1583 else 1491 ns_write_sram(card, scq->scd, &data, 1);
1584 scq->next++; 1492 }
1585 data = (u32) virt_to_bus(scq->next); 1493 spin_unlock_irqrestore(&scq->lock, flags);
1586 ns_write_sram(card, scq->scd, &data, 1); 1494 schedule();
1587 } 1495 }
1588 spin_unlock_irqrestore(&scq->lock, flags); 1496
1589 schedule(); 1497 /* Free all TST entries */
1590 } 1498 data = NS_TST_OPCODE_VARIABLE;
1591 1499 for (i = 0; i < NS_TST_NUM_ENTRIES; i++) {
1592 /* Free all TST entries */ 1500 if (card->tste2vc[i] == vc) {
1593 data = NS_TST_OPCODE_VARIABLE; 1501 ns_write_sram(card, card->tst_addr + i, &data,
1594 for (i = 0; i < NS_TST_NUM_ENTRIES; i++) 1502 1);
1595 { 1503 card->tste2vc[i] = NULL;
1596 if (card->tste2vc[i] == vc) 1504 card->tst_free_entries++;
1597 { 1505 }
1598 ns_write_sram(card, card->tst_addr + i, &data, 1); 1506 }
1599 card->tste2vc[i] = NULL; 1507
1600 card->tst_free_entries++; 1508 card->scd2vc[(vc->cbr_scd - NS_FRSCD) / NS_FRSCD_SIZE] = NULL;
1601 } 1509 free_scq(vc->scq, vcc);
1602 } 1510 }
1603 1511
1604 card->scd2vc[(vc->cbr_scd - NS_FRSCD) / NS_FRSCD_SIZE] = NULL; 1512 /* remove all references to vcc before deleting it */
1605 free_scq(vc->scq, vcc); 1513 if (vcc->qos.txtp.traffic_class != ATM_NONE) {
1606 } 1514 unsigned long flags;
1607 1515 scq_info *scq = card->scq0;
1608 /* remove all references to vcc before deleting it */ 1516
1609 if (vcc->qos.txtp.traffic_class != ATM_NONE) 1517 spin_lock_irqsave(&scq->lock, flags);
1610 { 1518
1611 unsigned long flags; 1519 for (i = 0; i < scq->num_entries; i++) {
1612 scq_info *scq = card->scq0; 1520 if (scq->skb[i] && ATM_SKB(scq->skb[i])->vcc == vcc) {
1613 1521 ATM_SKB(scq->skb[i])->vcc = NULL;
1614 spin_lock_irqsave(&scq->lock, flags); 1522 atm_return(vcc, scq->skb[i]->truesize);
1615 1523 PRINTK
1616 for(i = 0; i < scq->num_entries; i++) { 1524 ("nicstar: deleted pending vcc mapping\n");
1617 if(scq->skb[i] && ATM_SKB(scq->skb[i])->vcc == vcc) { 1525 }
1618 ATM_SKB(scq->skb[i])->vcc = NULL; 1526 }
1619 atm_return(vcc, scq->skb[i]->truesize); 1527
1620 PRINTK("nicstar: deleted pending vcc mapping\n"); 1528 spin_unlock_irqrestore(&scq->lock, flags);
1621 } 1529 }
1622 } 1530
1623 1531 vcc->dev_data = NULL;
1624 spin_unlock_irqrestore(&scq->lock, flags); 1532 clear_bit(ATM_VF_PARTIAL, &vcc->flags);
1625 } 1533 clear_bit(ATM_VF_ADDR, &vcc->flags);
1626
1627 vcc->dev_data = NULL;
1628 clear_bit(ATM_VF_PARTIAL,&vcc->flags);
1629 clear_bit(ATM_VF_ADDR,&vcc->flags);
1630 1534
1631#ifdef RX_DEBUG 1535#ifdef RX_DEBUG
1632 { 1536 {
1633 u32 stat, cfg; 1537 u32 stat, cfg;
1634 stat = readl(card->membase + STAT); 1538 stat = readl(card->membase + STAT);
1635 cfg = readl(card->membase + CFG); 1539 cfg = readl(card->membase + CFG);
1636 printk("STAT = 0x%08X CFG = 0x%08X \n", stat, cfg); 1540 printk("STAT = 0x%08X CFG = 0x%08X \n", stat, cfg);
1637 printk("TSQ: base = 0x%08X next = 0x%08X last = 0x%08X TSQT = 0x%08X \n", 1541 printk
1638 (u32) card->tsq.base, (u32) card->tsq.next,(u32) card->tsq.last, 1542 ("TSQ: base = 0x%08X next = 0x%08X last = 0x%08X TSQT = 0x%08X \n",
1639 readl(card->membase + TSQT)); 1543 (u32) card->tsq.base, (u32) card->tsq.next,
1640 printk("RSQ: base = 0x%08X next = 0x%08X last = 0x%08X RSQT = 0x%08X \n", 1544 (u32) card->tsq.last, readl(card->membase + TSQT));
1641 (u32) card->rsq.base, (u32) card->rsq.next,(u32) card->rsq.last, 1545 printk
1642 readl(card->membase + RSQT)); 1546 ("RSQ: base = 0x%08X next = 0x%08X last = 0x%08X RSQT = 0x%08X \n",
1643 printk("Empty free buffer queue interrupt %s \n", 1547 (u32) card->rsq.base, (u32) card->rsq.next,
1644 card->efbie ? "enabled" : "disabled"); 1548 (u32) card->rsq.last, readl(card->membase + RSQT));
1645 printk("SBCNT = %d count = %d LBCNT = %d count = %d \n", 1549 printk("Empty free buffer queue interrupt %s \n",
1646 ns_stat_sfbqc_get(stat), card->sbpool.count, 1550 card->efbie ? "enabled" : "disabled");
1647 ns_stat_lfbqc_get(stat), card->lbpool.count); 1551 printk("SBCNT = %d count = %d LBCNT = %d count = %d \n",
1648 printk("hbpool.count = %d iovpool.count = %d \n", 1552 ns_stat_sfbqc_get(stat), card->sbpool.count,
1649 card->hbpool.count, card->iovpool.count); 1553 ns_stat_lfbqc_get(stat), card->lbpool.count);
1650 } 1554 printk("hbpool.count = %d iovpool.count = %d \n",
1555 card->hbpool.count, card->iovpool.count);
1556 }
1651#endif /* RX_DEBUG */ 1557#endif /* RX_DEBUG */
1652} 1558}
1653 1559
1654 1560static void fill_tst(ns_dev * card, int n, vc_map * vc)
1655
1656static void fill_tst(ns_dev *card, int n, vc_map *vc)
1657{ 1561{
1658 u32 new_tst; 1562 u32 new_tst;
1659 unsigned long cl; 1563 unsigned long cl;
1660 int e, r; 1564 int e, r;
1661 u32 data; 1565 u32 data;
1662 1566
1663 /* It would be very complicated to keep the two TSTs synchronized while 1567 /* It would be very complicated to keep the two TSTs synchronized while
1664 assuring that writes are only made to the inactive TST. So, for now I 1568 assuring that writes are only made to the inactive TST. So, for now I
1665 will use only one TST. If problems occur, I will change this again */ 1569 will use only one TST. If problems occur, I will change this again */
1666 1570
1667 new_tst = card->tst_addr; 1571 new_tst = card->tst_addr;
1668 1572
1669 /* Fill procedure */ 1573 /* Fill procedure */
1670 1574
1671 for (e = 0; e < NS_TST_NUM_ENTRIES; e++) 1575 for (e = 0; e < NS_TST_NUM_ENTRIES; e++) {
1672 { 1576 if (card->tste2vc[e] == NULL)
1673 if (card->tste2vc[e] == NULL) 1577 break;
1674 break; 1578 }
1675 } 1579 if (e == NS_TST_NUM_ENTRIES) {
1676 if (e == NS_TST_NUM_ENTRIES) { 1580 printk("nicstar%d: No free TST entries found. \n", card->index);
1677 printk("nicstar%d: No free TST entries found. \n", card->index); 1581 return;
1678 return; 1582 }
1679 } 1583
1680 1584 r = n;
1681 r = n; 1585 cl = NS_TST_NUM_ENTRIES;
1682 cl = NS_TST_NUM_ENTRIES; 1586 data = ns_tste_make(NS_TST_OPCODE_FIXED, vc->cbr_scd);
1683 data = ns_tste_make(NS_TST_OPCODE_FIXED, vc->cbr_scd); 1587
1684 1588 while (r > 0) {
1685 while (r > 0) 1589 if (cl >= NS_TST_NUM_ENTRIES && card->tste2vc[e] == NULL) {
1686 { 1590 card->tste2vc[e] = vc;
1687 if (cl >= NS_TST_NUM_ENTRIES && card->tste2vc[e] == NULL) 1591 ns_write_sram(card, new_tst + e, &data, 1);
1688 { 1592 cl -= NS_TST_NUM_ENTRIES;
1689 card->tste2vc[e] = vc; 1593 r--;
1690 ns_write_sram(card, new_tst + e, &data, 1); 1594 }
1691 cl -= NS_TST_NUM_ENTRIES; 1595
1692 r--; 1596 if (++e == NS_TST_NUM_ENTRIES) {
1693 } 1597 e = 0;
1694 1598 }
1695 if (++e == NS_TST_NUM_ENTRIES) { 1599 cl += n;
1696 e = 0; 1600 }
1697 } 1601
1698 cl += n; 1602 /* End of fill procedure */
1699 } 1603
1700 1604 data = ns_tste_make(NS_TST_OPCODE_END, new_tst);
1701 /* End of fill procedure */ 1605 ns_write_sram(card, new_tst + NS_TST_NUM_ENTRIES, &data, 1);
1702 1606 ns_write_sram(card, card->tst_addr + NS_TST_NUM_ENTRIES, &data, 1);
1703 data = ns_tste_make(NS_TST_OPCODE_END, new_tst); 1607 card->tst_addr = new_tst;
1704 ns_write_sram(card, new_tst + NS_TST_NUM_ENTRIES, &data, 1);
1705 ns_write_sram(card, card->tst_addr + NS_TST_NUM_ENTRIES, &data, 1);
1706 card->tst_addr = new_tst;
1707} 1608}
1708 1609
1709
1710
1711static int ns_send(struct atm_vcc *vcc, struct sk_buff *skb) 1610static int ns_send(struct atm_vcc *vcc, struct sk_buff *skb)
1712{ 1611{
1713 ns_dev *card; 1612 ns_dev *card;
1714 vc_map *vc; 1613 vc_map *vc;
1715 scq_info *scq; 1614 scq_info *scq;
1716 unsigned long buflen; 1615 unsigned long buflen;
1717 ns_scqe scqe; 1616 ns_scqe scqe;
1718 u32 flags; /* TBD flags, not CPU flags */ 1617 u32 flags; /* TBD flags, not CPU flags */
1719 1618
1720 card = vcc->dev->dev_data; 1619 card = vcc->dev->dev_data;
1721 TXPRINTK("nicstar%d: ns_send() called.\n", card->index); 1620 TXPRINTK("nicstar%d: ns_send() called.\n", card->index);
1722 if ((vc = (vc_map *) vcc->dev_data) == NULL) 1621 if ((vc = (vc_map *) vcc->dev_data) == NULL) {
1723 { 1622 printk("nicstar%d: vcc->dev_data == NULL on ns_send().\n",
1724 printk("nicstar%d: vcc->dev_data == NULL on ns_send().\n", card->index); 1623 card->index);
1725 atomic_inc(&vcc->stats->tx_err); 1624 atomic_inc(&vcc->stats->tx_err);
1726 dev_kfree_skb_any(skb); 1625 dev_kfree_skb_any(skb);
1727 return -EINVAL; 1626 return -EINVAL;
1728 } 1627 }
1729
1730 if (!vc->tx)
1731 {
1732 printk("nicstar%d: Trying to transmit on a non-tx VC.\n", card->index);
1733 atomic_inc(&vcc->stats->tx_err);
1734 dev_kfree_skb_any(skb);
1735 return -EINVAL;
1736 }
1737
1738 if (vcc->qos.aal != ATM_AAL5 && vcc->qos.aal != ATM_AAL0)
1739 {
1740 printk("nicstar%d: Only AAL0 and AAL5 are supported.\n", card->index);
1741 atomic_inc(&vcc->stats->tx_err);
1742 dev_kfree_skb_any(skb);
1743 return -EINVAL;
1744 }
1745
1746 if (skb_shinfo(skb)->nr_frags != 0)
1747 {
1748 printk("nicstar%d: No scatter-gather yet.\n", card->index);
1749 atomic_inc(&vcc->stats->tx_err);
1750 dev_kfree_skb_any(skb);
1751 return -EINVAL;
1752 }
1753
1754 ATM_SKB(skb)->vcc = vcc;
1755
1756 if (vcc->qos.aal == ATM_AAL5)
1757 {
1758 buflen = (skb->len + 47 + 8) / 48 * 48; /* Multiple of 48 */
1759 flags = NS_TBD_AAL5;
1760 scqe.word_2 = cpu_to_le32((u32) virt_to_bus(skb->data));
1761 scqe.word_3 = cpu_to_le32((u32) skb->len);
1762 scqe.word_4 = ns_tbd_mkword_4(0, (u32) vcc->vpi, (u32) vcc->vci, 0,
1763 ATM_SKB(skb)->atm_options & ATM_ATMOPT_CLP ? 1 : 0);
1764 flags |= NS_TBD_EOPDU;
1765 }
1766 else /* (vcc->qos.aal == ATM_AAL0) */
1767 {
1768 buflen = ATM_CELL_PAYLOAD; /* i.e., 48 bytes */
1769 flags = NS_TBD_AAL0;
1770 scqe.word_2 = cpu_to_le32((u32) virt_to_bus(skb->data) + NS_AAL0_HEADER);
1771 scqe.word_3 = cpu_to_le32(0x00000000);
1772 if (*skb->data & 0x02) /* Payload type 1 - end of pdu */
1773 flags |= NS_TBD_EOPDU;
1774 scqe.word_4 = cpu_to_le32(*((u32 *) skb->data) & ~NS_TBD_VC_MASK);
1775 /* Force the VPI/VCI to be the same as in VCC struct */
1776 scqe.word_4 |= cpu_to_le32((((u32) vcc->vpi) << NS_TBD_VPI_SHIFT |
1777 ((u32) vcc->vci) << NS_TBD_VCI_SHIFT) &
1778 NS_TBD_VC_MASK);
1779 }
1780
1781 if (vcc->qos.txtp.traffic_class == ATM_CBR)
1782 {
1783 scqe.word_1 = ns_tbd_mkword_1_novbr(flags, (u32) buflen);
1784 scq = ((vc_map *) vcc->dev_data)->scq;
1785 }
1786 else
1787 {
1788 scqe.word_1 = ns_tbd_mkword_1(flags, (u32) 1, (u32) 1, (u32) buflen);
1789 scq = card->scq0;
1790 }
1791
1792 if (push_scqe(card, vc, scq, &scqe, skb) != 0)
1793 {
1794 atomic_inc(&vcc->stats->tx_err);
1795 dev_kfree_skb_any(skb);
1796 return -EIO;
1797 }
1798 atomic_inc(&vcc->stats->tx);
1799
1800 return 0;
1801}
1802
1803 1628
1629 if (!vc->tx) {
1630 printk("nicstar%d: Trying to transmit on a non-tx VC.\n",
1631 card->index);
1632 atomic_inc(&vcc->stats->tx_err);
1633 dev_kfree_skb_any(skb);
1634 return -EINVAL;
1635 }
1804 1636
1805static int push_scqe(ns_dev *card, vc_map *vc, scq_info *scq, ns_scqe *tbd, 1637 if (vcc->qos.aal != ATM_AAL5 && vcc->qos.aal != ATM_AAL0) {
1806 struct sk_buff *skb) 1638 printk("nicstar%d: Only AAL0 and AAL5 are supported.\n",
1807{ 1639 card->index);
1808 unsigned long flags; 1640 atomic_inc(&vcc->stats->tx_err);
1809 ns_scqe tsr; 1641 dev_kfree_skb_any(skb);
1810 u32 scdi, scqi; 1642 return -EINVAL;
1811 int scq_is_vbr; 1643 }
1812 u32 data;
1813 int index;
1814
1815 spin_lock_irqsave(&scq->lock, flags);
1816 while (scq->tail == scq->next)
1817 {
1818 if (in_interrupt()) {
1819 spin_unlock_irqrestore(&scq->lock, flags);
1820 printk("nicstar%d: Error pushing TBD.\n", card->index);
1821 return 1;
1822 }
1823
1824 scq->full = 1;
1825 spin_unlock_irqrestore(&scq->lock, flags);
1826 interruptible_sleep_on_timeout(&scq->scqfull_waitq, SCQFULL_TIMEOUT);
1827 spin_lock_irqsave(&scq->lock, flags);
1828
1829 if (scq->full) {
1830 spin_unlock_irqrestore(&scq->lock, flags);
1831 printk("nicstar%d: Timeout pushing TBD.\n", card->index);
1832 return 1;
1833 }
1834 }
1835 *scq->next = *tbd;
1836 index = (int) (scq->next - scq->base);
1837 scq->skb[index] = skb;
1838 XPRINTK("nicstar%d: sending skb at 0x%x (pos %d).\n",
1839 card->index, (u32) skb, index);
1840 XPRINTK("nicstar%d: TBD written:\n0x%x\n0x%x\n0x%x\n0x%x\n at 0x%x.\n",
1841 card->index, le32_to_cpu(tbd->word_1), le32_to_cpu(tbd->word_2),
1842 le32_to_cpu(tbd->word_3), le32_to_cpu(tbd->word_4),
1843 (u32) scq->next);
1844 if (scq->next == scq->last)
1845 scq->next = scq->base;
1846 else
1847 scq->next++;
1848
1849 vc->tbd_count++;
1850 if (scq->num_entries == VBR_SCQ_NUM_ENTRIES)
1851 {
1852 scq->tbd_count++;
1853 scq_is_vbr = 1;
1854 }
1855 else
1856 scq_is_vbr = 0;
1857
1858 if (vc->tbd_count >= MAX_TBD_PER_VC || scq->tbd_count >= MAX_TBD_PER_SCQ)
1859 {
1860 int has_run = 0;
1861
1862 while (scq->tail == scq->next)
1863 {
1864 if (in_interrupt()) {
1865 data = (u32) virt_to_bus(scq->next);
1866 ns_write_sram(card, scq->scd, &data, 1);
1867 spin_unlock_irqrestore(&scq->lock, flags);
1868 printk("nicstar%d: Error pushing TSR.\n", card->index);
1869 return 0;
1870 }
1871
1872 scq->full = 1;
1873 if (has_run++) break;
1874 spin_unlock_irqrestore(&scq->lock, flags);
1875 interruptible_sleep_on_timeout(&scq->scqfull_waitq, SCQFULL_TIMEOUT);
1876 spin_lock_irqsave(&scq->lock, flags);
1877 }
1878
1879 if (!scq->full)
1880 {
1881 tsr.word_1 = ns_tsr_mkword_1(NS_TSR_INTENABLE);
1882 if (scq_is_vbr)
1883 scdi = NS_TSR_SCDISVBR;
1884 else
1885 scdi = (vc->cbr_scd - NS_FRSCD) / NS_FRSCD_SIZE;
1886 scqi = scq->next - scq->base;
1887 tsr.word_2 = ns_tsr_mkword_2(scdi, scqi);
1888 tsr.word_3 = 0x00000000;
1889 tsr.word_4 = 0x00000000;
1890
1891 *scq->next = tsr;
1892 index = (int) scqi;
1893 scq->skb[index] = NULL;
1894 XPRINTK("nicstar%d: TSR written:\n0x%x\n0x%x\n0x%x\n0x%x\n at 0x%x.\n",
1895 card->index, le32_to_cpu(tsr.word_1), le32_to_cpu(tsr.word_2),
1896 le32_to_cpu(tsr.word_3), le32_to_cpu(tsr.word_4),
1897 (u32) scq->next);
1898 if (scq->next == scq->last)
1899 scq->next = scq->base;
1900 else
1901 scq->next++;
1902 vc->tbd_count = 0;
1903 scq->tbd_count = 0;
1904 }
1905 else
1906 PRINTK("nicstar%d: Timeout pushing TSR.\n", card->index);
1907 }
1908 data = (u32) virt_to_bus(scq->next);
1909 ns_write_sram(card, scq->scd, &data, 1);
1910
1911 spin_unlock_irqrestore(&scq->lock, flags);
1912
1913 return 0;
1914}
1915 1644
1645 if (skb_shinfo(skb)->nr_frags != 0) {
1646 printk("nicstar%d: No scatter-gather yet.\n", card->index);
1647 atomic_inc(&vcc->stats->tx_err);
1648 dev_kfree_skb_any(skb);
1649 return -EINVAL;
1650 }
1651
1652 ATM_SKB(skb)->vcc = vcc;
1653
1654 if (vcc->qos.aal == ATM_AAL5) {
1655 buflen = (skb->len + 47 + 8) / 48 * 48; /* Multiple of 48 */
1656 flags = NS_TBD_AAL5;
1657 scqe.word_2 = cpu_to_le32((u32) virt_to_bus(skb->data));
1658 scqe.word_3 = cpu_to_le32((u32) skb->len);
1659 scqe.word_4 =
1660 ns_tbd_mkword_4(0, (u32) vcc->vpi, (u32) vcc->vci, 0,
1661 ATM_SKB(skb)->
1662 atm_options & ATM_ATMOPT_CLP ? 1 : 0);
1663 flags |= NS_TBD_EOPDU;
1664 } else { /* (vcc->qos.aal == ATM_AAL0) */
1665
1666 buflen = ATM_CELL_PAYLOAD; /* i.e., 48 bytes */
1667 flags = NS_TBD_AAL0;
1668 scqe.word_2 =
1669 cpu_to_le32((u32) virt_to_bus(skb->data) + NS_AAL0_HEADER);
1670 scqe.word_3 = cpu_to_le32(0x00000000);
1671 if (*skb->data & 0x02) /* Payload type 1 - end of pdu */
1672 flags |= NS_TBD_EOPDU;
1673 scqe.word_4 =
1674 cpu_to_le32(*((u32 *) skb->data) & ~NS_TBD_VC_MASK);
1675 /* Force the VPI/VCI to be the same as in VCC struct */
1676 scqe.word_4 |=
1677 cpu_to_le32((((u32) vcc->
1678 vpi) << NS_TBD_VPI_SHIFT | ((u32) vcc->
1679 vci) <<
1680 NS_TBD_VCI_SHIFT) & NS_TBD_VC_MASK);
1681 }
1682
1683 if (vcc->qos.txtp.traffic_class == ATM_CBR) {
1684 scqe.word_1 = ns_tbd_mkword_1_novbr(flags, (u32) buflen);
1685 scq = ((vc_map *) vcc->dev_data)->scq;
1686 } else {
1687 scqe.word_1 =
1688 ns_tbd_mkword_1(flags, (u32) 1, (u32) 1, (u32) buflen);
1689 scq = card->scq0;
1690 }
1691
1692 if (push_scqe(card, vc, scq, &scqe, skb) != 0) {
1693 atomic_inc(&vcc->stats->tx_err);
1694 dev_kfree_skb_any(skb);
1695 return -EIO;
1696 }
1697 atomic_inc(&vcc->stats->tx);
1916 1698
1699 return 0;
1700}
1917 1701
1918static void process_tsq(ns_dev *card) 1702static int push_scqe(ns_dev * card, vc_map * vc, scq_info * scq, ns_scqe * tbd,
1703 struct sk_buff *skb)
1919{ 1704{
1920 u32 scdi; 1705 unsigned long flags;
1921 scq_info *scq; 1706 ns_scqe tsr;
1922 ns_tsi *previous = NULL, *one_ahead, *two_ahead; 1707 u32 scdi, scqi;
1923 int serviced_entries; /* flag indicating at least on entry was serviced */ 1708 int scq_is_vbr;
1924 1709 u32 data;
1925 serviced_entries = 0; 1710 int index;
1926 1711
1927 if (card->tsq.next == card->tsq.last) 1712 spin_lock_irqsave(&scq->lock, flags);
1928 one_ahead = card->tsq.base; 1713 while (scq->tail == scq->next) {
1929 else 1714 if (in_interrupt()) {
1930 one_ahead = card->tsq.next + 1; 1715 spin_unlock_irqrestore(&scq->lock, flags);
1931 1716 printk("nicstar%d: Error pushing TBD.\n", card->index);
1932 if (one_ahead == card->tsq.last) 1717 return 1;
1933 two_ahead = card->tsq.base; 1718 }
1934 else 1719
1935 two_ahead = one_ahead + 1; 1720 scq->full = 1;
1936 1721 spin_unlock_irqrestore(&scq->lock, flags);
1937 while (!ns_tsi_isempty(card->tsq.next) || !ns_tsi_isempty(one_ahead) || 1722 interruptible_sleep_on_timeout(&scq->scqfull_waitq,
1938 !ns_tsi_isempty(two_ahead)) 1723 SCQFULL_TIMEOUT);
1939 /* At most two empty, as stated in the 77201 errata */ 1724 spin_lock_irqsave(&scq->lock, flags);
1940 { 1725
1941 serviced_entries = 1; 1726 if (scq->full) {
1942 1727 spin_unlock_irqrestore(&scq->lock, flags);
1943 /* Skip the one or two possible empty entries */ 1728 printk("nicstar%d: Timeout pushing TBD.\n",
1944 while (ns_tsi_isempty(card->tsq.next)) { 1729 card->index);
1945 if (card->tsq.next == card->tsq.last) 1730 return 1;
1946 card->tsq.next = card->tsq.base; 1731 }
1947 else 1732 }
1948 card->tsq.next++; 1733 *scq->next = *tbd;
1949 } 1734 index = (int)(scq->next - scq->base);
1950 1735 scq->skb[index] = skb;
1951 if (!ns_tsi_tmrof(card->tsq.next)) 1736 XPRINTK("nicstar%d: sending skb at 0x%x (pos %d).\n",
1952 { 1737 card->index, (u32) skb, index);
1953 scdi = ns_tsi_getscdindex(card->tsq.next); 1738 XPRINTK("nicstar%d: TBD written:\n0x%x\n0x%x\n0x%x\n0x%x\n at 0x%x.\n",
1954 if (scdi == NS_TSI_SCDISVBR) 1739 card->index, le32_to_cpu(tbd->word_1), le32_to_cpu(tbd->word_2),
1955 scq = card->scq0; 1740 le32_to_cpu(tbd->word_3), le32_to_cpu(tbd->word_4),
1956 else 1741 (u32) scq->next);
1957 { 1742 if (scq->next == scq->last)
1958 if (card->scd2vc[scdi] == NULL) 1743 scq->next = scq->base;
1959 { 1744 else
1960 printk("nicstar%d: could not find VC from SCD index.\n", 1745 scq->next++;
1961 card->index); 1746
1962 ns_tsi_init(card->tsq.next); 1747 vc->tbd_count++;
1963 return; 1748 if (scq->num_entries == VBR_SCQ_NUM_ENTRIES) {
1964 } 1749 scq->tbd_count++;
1965 scq = card->scd2vc[scdi]->scq; 1750 scq_is_vbr = 1;
1966 } 1751 } else
1967 drain_scq(card, scq, ns_tsi_getscqpos(card->tsq.next)); 1752 scq_is_vbr = 0;
1968 scq->full = 0; 1753
1969 wake_up_interruptible(&(scq->scqfull_waitq)); 1754 if (vc->tbd_count >= MAX_TBD_PER_VC
1970 } 1755 || scq->tbd_count >= MAX_TBD_PER_SCQ) {
1971 1756 int has_run = 0;
1972 ns_tsi_init(card->tsq.next); 1757
1973 previous = card->tsq.next; 1758 while (scq->tail == scq->next) {
1974 if (card->tsq.next == card->tsq.last) 1759 if (in_interrupt()) {
1975 card->tsq.next = card->tsq.base; 1760 data = (u32) virt_to_bus(scq->next);
1976 else 1761 ns_write_sram(card, scq->scd, &data, 1);
1977 card->tsq.next++; 1762 spin_unlock_irqrestore(&scq->lock, flags);
1978 1763 printk("nicstar%d: Error pushing TSR.\n",
1979 if (card->tsq.next == card->tsq.last) 1764 card->index);
1980 one_ahead = card->tsq.base; 1765 return 0;
1981 else 1766 }
1982 one_ahead = card->tsq.next + 1; 1767
1983 1768 scq->full = 1;
1984 if (one_ahead == card->tsq.last) 1769 if (has_run++)
1985 two_ahead = card->tsq.base; 1770 break;
1986 else 1771 spin_unlock_irqrestore(&scq->lock, flags);
1987 two_ahead = one_ahead + 1; 1772 interruptible_sleep_on_timeout(&scq->scqfull_waitq,
1988 } 1773 SCQFULL_TIMEOUT);
1989 1774 spin_lock_irqsave(&scq->lock, flags);
1990 if (serviced_entries) { 1775 }
1991 writel((((u32) previous) - ((u32) card->tsq.base)), 1776
1992 card->membase + TSQH); 1777 if (!scq->full) {
1993 } 1778 tsr.word_1 = ns_tsr_mkword_1(NS_TSR_INTENABLE);
1779 if (scq_is_vbr)
1780 scdi = NS_TSR_SCDISVBR;
1781 else
1782 scdi = (vc->cbr_scd - NS_FRSCD) / NS_FRSCD_SIZE;
1783 scqi = scq->next - scq->base;
1784 tsr.word_2 = ns_tsr_mkword_2(scdi, scqi);
1785 tsr.word_3 = 0x00000000;
1786 tsr.word_4 = 0x00000000;
1787
1788 *scq->next = tsr;
1789 index = (int)scqi;
1790 scq->skb[index] = NULL;
1791 XPRINTK
1792 ("nicstar%d: TSR written:\n0x%x\n0x%x\n0x%x\n0x%x\n at 0x%x.\n",
1793 card->index, le32_to_cpu(tsr.word_1),
1794 le32_to_cpu(tsr.word_2), le32_to_cpu(tsr.word_3),
1795 le32_to_cpu(tsr.word_4), (u32) scq->next);
1796 if (scq->next == scq->last)
1797 scq->next = scq->base;
1798 else
1799 scq->next++;
1800 vc->tbd_count = 0;
1801 scq->tbd_count = 0;
1802 } else
1803 PRINTK("nicstar%d: Timeout pushing TSR.\n",
1804 card->index);
1805 }
1806 data = (u32) virt_to_bus(scq->next);
1807 ns_write_sram(card, scq->scd, &data, 1);
1808
1809 spin_unlock_irqrestore(&scq->lock, flags);
1810
1811 return 0;
1994} 1812}
1995 1813
1996 1814static void process_tsq(ns_dev * card)
1997
1998static void drain_scq(ns_dev *card, scq_info *scq, int pos)
1999{ 1815{
2000 struct atm_vcc *vcc; 1816 u32 scdi;
2001 struct sk_buff *skb; 1817 scq_info *scq;
2002 int i; 1818 ns_tsi *previous = NULL, *one_ahead, *two_ahead;
2003 unsigned long flags; 1819 int serviced_entries; /* flag indicating at least on entry was serviced */
2004 1820
2005 XPRINTK("nicstar%d: drain_scq() called, scq at 0x%x, pos %d.\n", 1821 serviced_entries = 0;
2006 card->index, (u32) scq, pos); 1822
2007 if (pos >= scq->num_entries) 1823 if (card->tsq.next == card->tsq.last)
2008 { 1824 one_ahead = card->tsq.base;
2009 printk("nicstar%d: Bad index on drain_scq().\n", card->index); 1825 else
2010 return; 1826 one_ahead = card->tsq.next + 1;
2011 } 1827
2012 1828 if (one_ahead == card->tsq.last)
2013 spin_lock_irqsave(&scq->lock, flags); 1829 two_ahead = card->tsq.base;
2014 i = (int) (scq->tail - scq->base); 1830 else
2015 if (++i == scq->num_entries) 1831 two_ahead = one_ahead + 1;
2016 i = 0; 1832
2017 while (i != pos) 1833 while (!ns_tsi_isempty(card->tsq.next) || !ns_tsi_isempty(one_ahead) ||
2018 { 1834 !ns_tsi_isempty(two_ahead))
2019 skb = scq->skb[i]; 1835 /* At most two empty, as stated in the 77201 errata */
2020 XPRINTK("nicstar%d: freeing skb at 0x%x (index %d).\n", 1836 {
2021 card->index, (u32) skb, i); 1837 serviced_entries = 1;
2022 if (skb != NULL) 1838
2023 { 1839 /* Skip the one or two possible empty entries */
2024 vcc = ATM_SKB(skb)->vcc; 1840 while (ns_tsi_isempty(card->tsq.next)) {
2025 if (vcc && vcc->pop != NULL) { 1841 if (card->tsq.next == card->tsq.last)
2026 vcc->pop(vcc, skb); 1842 card->tsq.next = card->tsq.base;
2027 } else { 1843 else
2028 dev_kfree_skb_irq(skb); 1844 card->tsq.next++;
2029 } 1845 }
2030 scq->skb[i] = NULL; 1846
2031 } 1847 if (!ns_tsi_tmrof(card->tsq.next)) {
2032 if (++i == scq->num_entries) 1848 scdi = ns_tsi_getscdindex(card->tsq.next);
2033 i = 0; 1849 if (scdi == NS_TSI_SCDISVBR)
2034 } 1850 scq = card->scq0;
2035 scq->tail = scq->base + pos; 1851 else {
2036 spin_unlock_irqrestore(&scq->lock, flags); 1852 if (card->scd2vc[scdi] == NULL) {
1853 printk
1854 ("nicstar%d: could not find VC from SCD index.\n",
1855 card->index);
1856 ns_tsi_init(card->tsq.next);
1857 return;
1858 }
1859 scq = card->scd2vc[scdi]->scq;
1860 }
1861 drain_scq(card, scq, ns_tsi_getscqpos(card->tsq.next));
1862 scq->full = 0;
1863 wake_up_interruptible(&(scq->scqfull_waitq));
1864 }
1865
1866 ns_tsi_init(card->tsq.next);
1867 previous = card->tsq.next;
1868 if (card->tsq.next == card->tsq.last)
1869 card->tsq.next = card->tsq.base;
1870 else
1871 card->tsq.next++;
1872
1873 if (card->tsq.next == card->tsq.last)
1874 one_ahead = card->tsq.base;
1875 else
1876 one_ahead = card->tsq.next + 1;
1877
1878 if (one_ahead == card->tsq.last)
1879 two_ahead = card->tsq.base;
1880 else
1881 two_ahead = one_ahead + 1;
1882 }
1883
1884 if (serviced_entries) {
1885 writel((((u32) previous) - ((u32) card->tsq.base)),
1886 card->membase + TSQH);
1887 }
2037} 1888}
2038 1889
2039 1890static void drain_scq(ns_dev * card, scq_info * scq, int pos)
2040
2041static void process_rsq(ns_dev *card)
2042{ 1891{
2043 ns_rsqe *previous; 1892 struct atm_vcc *vcc;
2044 1893 struct sk_buff *skb;
2045 if (!ns_rsqe_valid(card->rsq.next)) 1894 int i;
2046 return; 1895 unsigned long flags;
2047 do { 1896
2048 dequeue_rx(card, card->rsq.next); 1897 XPRINTK("nicstar%d: drain_scq() called, scq at 0x%x, pos %d.\n",
2049 ns_rsqe_init(card->rsq.next); 1898 card->index, (u32) scq, pos);
2050 previous = card->rsq.next; 1899 if (pos >= scq->num_entries) {
2051 if (card->rsq.next == card->rsq.last) 1900 printk("nicstar%d: Bad index on drain_scq().\n", card->index);
2052 card->rsq.next = card->rsq.base; 1901 return;
2053 else 1902 }
2054 card->rsq.next++; 1903
2055 } while (ns_rsqe_valid(card->rsq.next)); 1904 spin_lock_irqsave(&scq->lock, flags);
2056 writel((((u32) previous) - ((u32) card->rsq.base)), 1905 i = (int)(scq->tail - scq->base);
2057 card->membase + RSQH); 1906 if (++i == scq->num_entries)
1907 i = 0;
1908 while (i != pos) {
1909 skb = scq->skb[i];
1910 XPRINTK("nicstar%d: freeing skb at 0x%x (index %d).\n",
1911 card->index, (u32) skb, i);
1912 if (skb != NULL) {
1913 vcc = ATM_SKB(skb)->vcc;
1914 if (vcc && vcc->pop != NULL) {
1915 vcc->pop(vcc, skb);
1916 } else {
1917 dev_kfree_skb_irq(skb);
1918 }
1919 scq->skb[i] = NULL;
1920 }
1921 if (++i == scq->num_entries)
1922 i = 0;
1923 }
1924 scq->tail = scq->base + pos;
1925 spin_unlock_irqrestore(&scq->lock, flags);
2058} 1926}
2059 1927
1928static void process_rsq(ns_dev * card)
1929{
1930 ns_rsqe *previous;
1931
1932 if (!ns_rsqe_valid(card->rsq.next))
1933 return;
1934 do {
1935 dequeue_rx(card, card->rsq.next);
1936 ns_rsqe_init(card->rsq.next);
1937 previous = card->rsq.next;
1938 if (card->rsq.next == card->rsq.last)
1939 card->rsq.next = card->rsq.base;
1940 else
1941 card->rsq.next++;
1942 } while (ns_rsqe_valid(card->rsq.next));
1943 writel((((u32) previous) - ((u32) card->rsq.base)),
1944 card->membase + RSQH);
1945}
2060 1946
2061 1947static void dequeue_rx(ns_dev * card, ns_rsqe * rsqe)
2062static void dequeue_rx(ns_dev *card, ns_rsqe *rsqe)
2063{ 1948{
2064 u32 vpi, vci; 1949 u32 vpi, vci;
2065 vc_map *vc; 1950 vc_map *vc;
2066 struct sk_buff *iovb; 1951 struct sk_buff *iovb;
2067 struct iovec *iov; 1952 struct iovec *iov;
2068 struct atm_vcc *vcc; 1953 struct atm_vcc *vcc;
2069 struct sk_buff *skb; 1954 struct sk_buff *skb;
2070 unsigned short aal5_len; 1955 unsigned short aal5_len;
2071 int len; 1956 int len;
2072 u32 stat; 1957 u32 stat;
2073 1958
2074 stat = readl(card->membase + STAT); 1959 stat = readl(card->membase + STAT);
2075 card->sbfqc = ns_stat_sfbqc_get(stat); 1960 card->sbfqc = ns_stat_sfbqc_get(stat);
2076 card->lbfqc = ns_stat_lfbqc_get(stat); 1961 card->lbfqc = ns_stat_lfbqc_get(stat);
2077 1962
2078 skb = (struct sk_buff *) le32_to_cpu(rsqe->buffer_handle); 1963 skb = (struct sk_buff *)le32_to_cpu(rsqe->buffer_handle);
2079 vpi = ns_rsqe_vpi(rsqe); 1964 vpi = ns_rsqe_vpi(rsqe);
2080 vci = ns_rsqe_vci(rsqe); 1965 vci = ns_rsqe_vci(rsqe);
2081 if (vpi >= 1UL << card->vpibits || vci >= 1UL << card->vcibits) 1966 if (vpi >= 1UL << card->vpibits || vci >= 1UL << card->vcibits) {
2082 { 1967 printk("nicstar%d: SDU received for out-of-range vc %d.%d.\n",
2083 printk("nicstar%d: SDU received for out-of-range vc %d.%d.\n", 1968 card->index, vpi, vci);
2084 card->index, vpi, vci); 1969 recycle_rx_buf(card, skb);
2085 recycle_rx_buf(card, skb); 1970 return;
2086 return; 1971 }
2087 } 1972
2088 1973 vc = &(card->vcmap[vpi << card->vcibits | vci]);
2089 vc = &(card->vcmap[vpi << card->vcibits | vci]); 1974 if (!vc->rx) {
2090 if (!vc->rx) 1975 RXPRINTK("nicstar%d: SDU received on non-rx vc %d.%d.\n",
2091 { 1976 card->index, vpi, vci);
2092 RXPRINTK("nicstar%d: SDU received on non-rx vc %d.%d.\n", 1977 recycle_rx_buf(card, skb);
2093 card->index, vpi, vci); 1978 return;
2094 recycle_rx_buf(card, skb); 1979 }
2095 return; 1980
2096 } 1981 vcc = vc->rx_vcc;
2097 1982
2098 vcc = vc->rx_vcc; 1983 if (vcc->qos.aal == ATM_AAL0) {
2099 1984 struct sk_buff *sb;
2100 if (vcc->qos.aal == ATM_AAL0) 1985 unsigned char *cell;
2101 { 1986 int i;
2102 struct sk_buff *sb; 1987
2103 unsigned char *cell; 1988 cell = skb->data;
2104 int i; 1989 for (i = ns_rsqe_cellcount(rsqe); i; i--) {
2105 1990 if ((sb = dev_alloc_skb(NS_SMSKBSIZE)) == NULL) {
2106 cell = skb->data; 1991 printk
2107 for (i = ns_rsqe_cellcount(rsqe); i; i--) 1992 ("nicstar%d: Can't allocate buffers for aal0.\n",
2108 { 1993 card->index);
2109 if ((sb = dev_alloc_skb(NS_SMSKBSIZE)) == NULL) 1994 atomic_add(i, &vcc->stats->rx_drop);
2110 { 1995 break;
2111 printk("nicstar%d: Can't allocate buffers for aal0.\n", 1996 }
2112 card->index); 1997 if (!atm_charge(vcc, sb->truesize)) {
2113 atomic_add(i,&vcc->stats->rx_drop); 1998 RXPRINTK
2114 break; 1999 ("nicstar%d: atm_charge() dropped aal0 packets.\n",
2115 } 2000 card->index);
2116 if (!atm_charge(vcc, sb->truesize)) 2001 atomic_add(i - 1, &vcc->stats->rx_drop); /* already increased by 1 */
2117 { 2002 dev_kfree_skb_any(sb);
2118 RXPRINTK("nicstar%d: atm_charge() dropped aal0 packets.\n", 2003 break;
2119 card->index); 2004 }
2120 atomic_add(i-1,&vcc->stats->rx_drop); /* already increased by 1 */ 2005 /* Rebuild the header */
2121 dev_kfree_skb_any(sb); 2006 *((u32 *) sb->data) = le32_to_cpu(rsqe->word_1) << 4 |
2122 break; 2007 (ns_rsqe_clp(rsqe) ? 0x00000001 : 0x00000000);
2123 } 2008 if (i == 1 && ns_rsqe_eopdu(rsqe))
2124 /* Rebuild the header */ 2009 *((u32 *) sb->data) |= 0x00000002;
2125 *((u32 *) sb->data) = le32_to_cpu(rsqe->word_1) << 4 | 2010 skb_put(sb, NS_AAL0_HEADER);
2126 (ns_rsqe_clp(rsqe) ? 0x00000001 : 0x00000000); 2011 memcpy(skb_tail_pointer(sb), cell, ATM_CELL_PAYLOAD);
2127 if (i == 1 && ns_rsqe_eopdu(rsqe)) 2012 skb_put(sb, ATM_CELL_PAYLOAD);
2128 *((u32 *) sb->data) |= 0x00000002; 2013 ATM_SKB(sb)->vcc = vcc;
2129 skb_put(sb, NS_AAL0_HEADER); 2014 __net_timestamp(sb);
2130 memcpy(skb_tail_pointer(sb), cell, ATM_CELL_PAYLOAD); 2015 vcc->push(vcc, sb);
2131 skb_put(sb, ATM_CELL_PAYLOAD); 2016 atomic_inc(&vcc->stats->rx);
2132 ATM_SKB(sb)->vcc = vcc; 2017 cell += ATM_CELL_PAYLOAD;
2133 __net_timestamp(sb); 2018 }
2134 vcc->push(vcc, sb); 2019
2135 atomic_inc(&vcc->stats->rx); 2020 recycle_rx_buf(card, skb);
2136 cell += ATM_CELL_PAYLOAD; 2021 return;
2137 } 2022 }
2138 2023
2139 recycle_rx_buf(card, skb); 2024 /* To reach this point, the AAL layer can only be AAL5 */
2140 return; 2025
2141 } 2026 if ((iovb = vc->rx_iov) == NULL) {
2142 2027 iovb = skb_dequeue(&(card->iovpool.queue));
2143 /* To reach this point, the AAL layer can only be AAL5 */ 2028 if (iovb == NULL) { /* No buffers in the queue */
2144 2029 iovb = alloc_skb(NS_IOVBUFSIZE, GFP_ATOMIC);
2145 if ((iovb = vc->rx_iov) == NULL) 2030 if (iovb == NULL) {
2146 { 2031 printk("nicstar%d: Out of iovec buffers.\n",
2147 iovb = skb_dequeue(&(card->iovpool.queue)); 2032 card->index);
2148 if (iovb == NULL) /* No buffers in the queue */ 2033 atomic_inc(&vcc->stats->rx_drop);
2149 { 2034 recycle_rx_buf(card, skb);
2150 iovb = alloc_skb(NS_IOVBUFSIZE, GFP_ATOMIC); 2035 return;
2151 if (iovb == NULL) 2036 }
2152 { 2037 NS_SKB_CB(iovb)->buf_type = BUF_NONE;
2153 printk("nicstar%d: Out of iovec buffers.\n", card->index); 2038 } else if (--card->iovpool.count < card->iovnr.min) {
2154 atomic_inc(&vcc->stats->rx_drop); 2039 struct sk_buff *new_iovb;
2155 recycle_rx_buf(card, skb); 2040 if ((new_iovb =
2156 return; 2041 alloc_skb(NS_IOVBUFSIZE, GFP_ATOMIC)) != NULL) {
2157 } 2042 NS_SKB_CB(iovb)->buf_type = BUF_NONE;
2158 NS_SKB_CB(iovb)->buf_type = BUF_NONE; 2043 skb_queue_tail(&card->iovpool.queue, new_iovb);
2159 } 2044 card->iovpool.count++;
2160 else 2045 }
2161 if (--card->iovpool.count < card->iovnr.min) 2046 }
2162 { 2047 vc->rx_iov = iovb;
2163 struct sk_buff *new_iovb; 2048 NS_SKB(iovb)->iovcnt = 0;
2164 if ((new_iovb = alloc_skb(NS_IOVBUFSIZE, GFP_ATOMIC)) != NULL) 2049 iovb->len = 0;
2165 { 2050 iovb->data = iovb->head;
2166 NS_SKB_CB(iovb)->buf_type = BUF_NONE; 2051 skb_reset_tail_pointer(iovb);
2167 skb_queue_tail(&card->iovpool.queue, new_iovb); 2052 NS_SKB(iovb)->vcc = vcc;
2168 card->iovpool.count++; 2053 /* IMPORTANT: a pointer to the sk_buff containing the small or large
2169 } 2054 buffer is stored as iovec base, NOT a pointer to the
2170 } 2055 small or large buffer itself. */
2171 vc->rx_iov = iovb; 2056 } else if (NS_SKB(iovb)->iovcnt >= NS_MAX_IOVECS) {
2172 NS_SKB(iovb)->iovcnt = 0; 2057 printk("nicstar%d: received too big AAL5 SDU.\n", card->index);
2173 iovb->len = 0; 2058 atomic_inc(&vcc->stats->rx_err);
2174 iovb->data = iovb->head; 2059 recycle_iovec_rx_bufs(card, (struct iovec *)iovb->data,
2175 skb_reset_tail_pointer(iovb); 2060 NS_MAX_IOVECS);
2176 NS_SKB(iovb)->vcc = vcc; 2061 NS_SKB(iovb)->iovcnt = 0;
2177 /* IMPORTANT: a pointer to the sk_buff containing the small or large 2062 iovb->len = 0;
2178 buffer is stored as iovec base, NOT a pointer to the 2063 iovb->data = iovb->head;
2179 small or large buffer itself. */ 2064 skb_reset_tail_pointer(iovb);
2180 } 2065 NS_SKB(iovb)->vcc = vcc;
2181 else if (NS_SKB(iovb)->iovcnt >= NS_MAX_IOVECS) 2066 }
2182 { 2067 iov = &((struct iovec *)iovb->data)[NS_SKB(iovb)->iovcnt++];
2183 printk("nicstar%d: received too big AAL5 SDU.\n", card->index); 2068 iov->iov_base = (void *)skb;
2184 atomic_inc(&vcc->stats->rx_err); 2069 iov->iov_len = ns_rsqe_cellcount(rsqe) * 48;
2185 recycle_iovec_rx_bufs(card, (struct iovec *) iovb->data, NS_MAX_IOVECS); 2070 iovb->len += iov->iov_len;
2186 NS_SKB(iovb)->iovcnt = 0; 2071
2187 iovb->len = 0; 2072 if (NS_SKB(iovb)->iovcnt == 1) {
2188 iovb->data = iovb->head; 2073 if (NS_SKB_CB(skb)->buf_type != BUF_SM) {
2189 skb_reset_tail_pointer(iovb); 2074 printk
2190 NS_SKB(iovb)->vcc = vcc; 2075 ("nicstar%d: Expected a small buffer, and this is not one.\n",
2191 } 2076 card->index);
2192 iov = &((struct iovec *) iovb->data)[NS_SKB(iovb)->iovcnt++]; 2077 which_list(card, skb);
2193 iov->iov_base = (void *) skb; 2078 atomic_inc(&vcc->stats->rx_err);
2194 iov->iov_len = ns_rsqe_cellcount(rsqe) * 48; 2079 recycle_rx_buf(card, skb);
2195 iovb->len += iov->iov_len; 2080 vc->rx_iov = NULL;
2196 2081 recycle_iov_buf(card, iovb);
2197 if (NS_SKB(iovb)->iovcnt == 1) 2082 return;
2198 { 2083 }
2199 if (NS_SKB_CB(skb)->buf_type != BUF_SM) 2084 } else { /* NS_SKB(iovb)->iovcnt >= 2 */
2200 { 2085
2201 printk("nicstar%d: Expected a small buffer, and this is not one.\n", 2086 if (NS_SKB_CB(skb)->buf_type != BUF_LG) {
2202 card->index); 2087 printk
2203 which_list(card, skb); 2088 ("nicstar%d: Expected a large buffer, and this is not one.\n",
2204 atomic_inc(&vcc->stats->rx_err); 2089 card->index);
2205 recycle_rx_buf(card, skb); 2090 which_list(card, skb);
2206 vc->rx_iov = NULL; 2091 atomic_inc(&vcc->stats->rx_err);
2207 recycle_iov_buf(card, iovb); 2092 recycle_iovec_rx_bufs(card, (struct iovec *)iovb->data,
2208 return; 2093 NS_SKB(iovb)->iovcnt);
2209 } 2094 vc->rx_iov = NULL;
2210 } 2095 recycle_iov_buf(card, iovb);
2211 else /* NS_SKB(iovb)->iovcnt >= 2 */ 2096 return;
2212 { 2097 }
2213 if (NS_SKB_CB(skb)->buf_type != BUF_LG) 2098 }
2214 { 2099
2215 printk("nicstar%d: Expected a large buffer, and this is not one.\n", 2100 if (ns_rsqe_eopdu(rsqe)) {
2216 card->index); 2101 /* This works correctly regardless of the endianness of the host */
2217 which_list(card, skb); 2102 unsigned char *L1L2 = (unsigned char *)((u32) skb->data +
2218 atomic_inc(&vcc->stats->rx_err); 2103 iov->iov_len - 6);
2219 recycle_iovec_rx_bufs(card, (struct iovec *) iovb->data, 2104 aal5_len = L1L2[0] << 8 | L1L2[1];
2220 NS_SKB(iovb)->iovcnt); 2105 len = (aal5_len == 0x0000) ? 0x10000 : aal5_len;
2221 vc->rx_iov = NULL; 2106 if (ns_rsqe_crcerr(rsqe) ||
2222 recycle_iov_buf(card, iovb); 2107 len + 8 > iovb->len || len + (47 + 8) < iovb->len) {
2223 return; 2108 printk("nicstar%d: AAL5 CRC error", card->index);
2224 } 2109 if (len + 8 > iovb->len || len + (47 + 8) < iovb->len)
2225 } 2110 printk(" - PDU size mismatch.\n");
2226 2111 else
2227 if (ns_rsqe_eopdu(rsqe)) 2112 printk(".\n");
2228 { 2113 atomic_inc(&vcc->stats->rx_err);
2229 /* This works correctly regardless of the endianness of the host */ 2114 recycle_iovec_rx_bufs(card, (struct iovec *)iovb->data,
2230 unsigned char *L1L2 = (unsigned char *)((u32)skb->data + 2115 NS_SKB(iovb)->iovcnt);
2231 iov->iov_len - 6); 2116 vc->rx_iov = NULL;
2232 aal5_len = L1L2[0] << 8 | L1L2[1]; 2117 recycle_iov_buf(card, iovb);
2233 len = (aal5_len == 0x0000) ? 0x10000 : aal5_len; 2118 return;
2234 if (ns_rsqe_crcerr(rsqe) || 2119 }
2235 len + 8 > iovb->len || len + (47 + 8) < iovb->len) 2120
2236 { 2121 /* By this point we (hopefully) have a complete SDU without errors. */
2237 printk("nicstar%d: AAL5 CRC error", card->index); 2122
2238 if (len + 8 > iovb->len || len + (47 + 8) < iovb->len) 2123 if (NS_SKB(iovb)->iovcnt == 1) { /* Just a small buffer */
2239 printk(" - PDU size mismatch.\n"); 2124 /* skb points to a small buffer */
2240 else 2125 if (!atm_charge(vcc, skb->truesize)) {
2241 printk(".\n"); 2126 push_rxbufs(card, skb);
2242 atomic_inc(&vcc->stats->rx_err); 2127 atomic_inc(&vcc->stats->rx_drop);
2243 recycle_iovec_rx_bufs(card, (struct iovec *) iovb->data, 2128 } else {
2244 NS_SKB(iovb)->iovcnt); 2129 skb_put(skb, len);
2245 vc->rx_iov = NULL; 2130 dequeue_sm_buf(card, skb);
2246 recycle_iov_buf(card, iovb);
2247 return;
2248 }
2249
2250 /* By this point we (hopefully) have a complete SDU without errors. */
2251
2252 if (NS_SKB(iovb)->iovcnt == 1) /* Just a small buffer */
2253 {
2254 /* skb points to a small buffer */
2255 if (!atm_charge(vcc, skb->truesize))
2256 {
2257 push_rxbufs(card, skb);
2258 atomic_inc(&vcc->stats->rx_drop);
2259 }
2260 else
2261 {
2262 skb_put(skb, len);
2263 dequeue_sm_buf(card, skb);
2264#ifdef NS_USE_DESTRUCTORS 2131#ifdef NS_USE_DESTRUCTORS
2265 skb->destructor = ns_sb_destructor; 2132 skb->destructor = ns_sb_destructor;
2266#endif /* NS_USE_DESTRUCTORS */ 2133#endif /* NS_USE_DESTRUCTORS */
2267 ATM_SKB(skb)->vcc = vcc; 2134 ATM_SKB(skb)->vcc = vcc;
2268 __net_timestamp(skb); 2135 __net_timestamp(skb);
2269 vcc->push(vcc, skb); 2136 vcc->push(vcc, skb);
2270 atomic_inc(&vcc->stats->rx); 2137 atomic_inc(&vcc->stats->rx);
2271 } 2138 }
2272 } 2139 } else if (NS_SKB(iovb)->iovcnt == 2) { /* One small plus one large buffer */
2273 else if (NS_SKB(iovb)->iovcnt == 2) /* One small plus one large buffer */ 2140 struct sk_buff *sb;
2274 { 2141
2275 struct sk_buff *sb; 2142 sb = (struct sk_buff *)(iov - 1)->iov_base;
2276 2143 /* skb points to a large buffer */
2277 sb = (struct sk_buff *) (iov - 1)->iov_base; 2144
2278 /* skb points to a large buffer */ 2145 if (len <= NS_SMBUFSIZE) {
2279 2146 if (!atm_charge(vcc, sb->truesize)) {
2280 if (len <= NS_SMBUFSIZE) 2147 push_rxbufs(card, sb);
2281 { 2148 atomic_inc(&vcc->stats->rx_drop);
2282 if (!atm_charge(vcc, sb->truesize)) 2149 } else {
2283 { 2150 skb_put(sb, len);
2284 push_rxbufs(card, sb); 2151 dequeue_sm_buf(card, sb);
2285 atomic_inc(&vcc->stats->rx_drop);
2286 }
2287 else
2288 {
2289 skb_put(sb, len);
2290 dequeue_sm_buf(card, sb);
2291#ifdef NS_USE_DESTRUCTORS 2152#ifdef NS_USE_DESTRUCTORS
2292 sb->destructor = ns_sb_destructor; 2153 sb->destructor = ns_sb_destructor;
2293#endif /* NS_USE_DESTRUCTORS */ 2154#endif /* NS_USE_DESTRUCTORS */
2294 ATM_SKB(sb)->vcc = vcc; 2155 ATM_SKB(sb)->vcc = vcc;
2295 __net_timestamp(sb); 2156 __net_timestamp(sb);
2296 vcc->push(vcc, sb); 2157 vcc->push(vcc, sb);
2297 atomic_inc(&vcc->stats->rx); 2158 atomic_inc(&vcc->stats->rx);
2298 } 2159 }
2299 2160
2300 push_rxbufs(card, skb); 2161 push_rxbufs(card, skb);
2301 2162
2302 } 2163 } else { /* len > NS_SMBUFSIZE, the usual case */
2303 else /* len > NS_SMBUFSIZE, the usual case */ 2164
2304 { 2165 if (!atm_charge(vcc, skb->truesize)) {
2305 if (!atm_charge(vcc, skb->truesize)) 2166 push_rxbufs(card, skb);
2306 { 2167 atomic_inc(&vcc->stats->rx_drop);
2307 push_rxbufs(card, skb); 2168 } else {
2308 atomic_inc(&vcc->stats->rx_drop); 2169 dequeue_lg_buf(card, skb);
2309 }
2310 else
2311 {
2312 dequeue_lg_buf(card, skb);
2313#ifdef NS_USE_DESTRUCTORS 2170#ifdef NS_USE_DESTRUCTORS
2314 skb->destructor = ns_lb_destructor; 2171 skb->destructor = ns_lb_destructor;
2315#endif /* NS_USE_DESTRUCTORS */ 2172#endif /* NS_USE_DESTRUCTORS */
2316 skb_push(skb, NS_SMBUFSIZE); 2173 skb_push(skb, NS_SMBUFSIZE);
2317 skb_copy_from_linear_data(sb, skb->data, NS_SMBUFSIZE); 2174 skb_copy_from_linear_data(sb, skb->data,
2318 skb_put(skb, len - NS_SMBUFSIZE); 2175 NS_SMBUFSIZE);
2319 ATM_SKB(skb)->vcc = vcc; 2176 skb_put(skb, len - NS_SMBUFSIZE);
2320 __net_timestamp(skb); 2177 ATM_SKB(skb)->vcc = vcc;
2321 vcc->push(vcc, skb); 2178 __net_timestamp(skb);
2322 atomic_inc(&vcc->stats->rx); 2179 vcc->push(vcc, skb);
2323 } 2180 atomic_inc(&vcc->stats->rx);
2324 2181 }
2325 push_rxbufs(card, sb); 2182
2326 2183 push_rxbufs(card, sb);
2327 } 2184
2328 2185 }
2329 } 2186
2330 else /* Must push a huge buffer */ 2187 } else { /* Must push a huge buffer */
2331 { 2188
2332 struct sk_buff *hb, *sb, *lb; 2189 struct sk_buff *hb, *sb, *lb;
2333 int remaining, tocopy; 2190 int remaining, tocopy;
2334 int j; 2191 int j;
2335 2192
2336 hb = skb_dequeue(&(card->hbpool.queue)); 2193 hb = skb_dequeue(&(card->hbpool.queue));
2337 if (hb == NULL) /* No buffers in the queue */ 2194 if (hb == NULL) { /* No buffers in the queue */
2338 { 2195
2339 2196 hb = dev_alloc_skb(NS_HBUFSIZE);
2340 hb = dev_alloc_skb(NS_HBUFSIZE); 2197 if (hb == NULL) {
2341 if (hb == NULL) 2198 printk
2342 { 2199 ("nicstar%d: Out of huge buffers.\n",
2343 printk("nicstar%d: Out of huge buffers.\n", card->index); 2200 card->index);
2344 atomic_inc(&vcc->stats->rx_drop); 2201 atomic_inc(&vcc->stats->rx_drop);
2345 recycle_iovec_rx_bufs(card, (struct iovec *) iovb->data, 2202 recycle_iovec_rx_bufs(card,
2346 NS_SKB(iovb)->iovcnt); 2203 (struct iovec *)
2347 vc->rx_iov = NULL; 2204 iovb->data,
2348 recycle_iov_buf(card, iovb); 2205 NS_SKB(iovb)->
2349 return; 2206 iovcnt);
2350 } 2207 vc->rx_iov = NULL;
2351 else if (card->hbpool.count < card->hbnr.min) 2208 recycle_iov_buf(card, iovb);
2352 { 2209 return;
2353 struct sk_buff *new_hb; 2210 } else if (card->hbpool.count < card->hbnr.min) {
2354 if ((new_hb = dev_alloc_skb(NS_HBUFSIZE)) != NULL) 2211 struct sk_buff *new_hb;
2355 { 2212 if ((new_hb =
2356 skb_queue_tail(&card->hbpool.queue, new_hb); 2213 dev_alloc_skb(NS_HBUFSIZE)) !=
2357 card->hbpool.count++; 2214 NULL) {
2358 } 2215 skb_queue_tail(&card->hbpool.
2359 } 2216 queue, new_hb);
2360 NS_SKB_CB(hb)->buf_type = BUF_NONE; 2217 card->hbpool.count++;
2361 } 2218 }
2362 else 2219 }
2363 if (--card->hbpool.count < card->hbnr.min) 2220 NS_SKB_CB(hb)->buf_type = BUF_NONE;
2364 { 2221 } else if (--card->hbpool.count < card->hbnr.min) {
2365 struct sk_buff *new_hb; 2222 struct sk_buff *new_hb;
2366 if ((new_hb = dev_alloc_skb(NS_HBUFSIZE)) != NULL) 2223 if ((new_hb =
2367 { 2224 dev_alloc_skb(NS_HBUFSIZE)) != NULL) {
2368 NS_SKB_CB(new_hb)->buf_type = BUF_NONE; 2225 NS_SKB_CB(new_hb)->buf_type = BUF_NONE;
2369 skb_queue_tail(&card->hbpool.queue, new_hb); 2226 skb_queue_tail(&card->hbpool.queue,
2370 card->hbpool.count++; 2227 new_hb);
2371 } 2228 card->hbpool.count++;
2372 if (card->hbpool.count < card->hbnr.min) 2229 }
2373 { 2230 if (card->hbpool.count < card->hbnr.min) {
2374 if ((new_hb = dev_alloc_skb(NS_HBUFSIZE)) != NULL) 2231 if ((new_hb =
2375 { 2232 dev_alloc_skb(NS_HBUFSIZE)) !=
2376 NS_SKB_CB(new_hb)->buf_type = BUF_NONE; 2233 NULL) {
2377 skb_queue_tail(&card->hbpool.queue, new_hb); 2234 NS_SKB_CB(new_hb)->buf_type =
2378 card->hbpool.count++; 2235 BUF_NONE;
2379 } 2236 skb_queue_tail(&card->hbpool.
2380 } 2237 queue, new_hb);
2381 } 2238 card->hbpool.count++;
2382 2239 }
2383 iov = (struct iovec *) iovb->data; 2240 }
2384 2241 }
2385 if (!atm_charge(vcc, hb->truesize)) 2242
2386 { 2243 iov = (struct iovec *)iovb->data;
2387 recycle_iovec_rx_bufs(card, iov, NS_SKB(iovb)->iovcnt); 2244
2388 if (card->hbpool.count < card->hbnr.max) 2245 if (!atm_charge(vcc, hb->truesize)) {
2389 { 2246 recycle_iovec_rx_bufs(card, iov,
2390 skb_queue_tail(&card->hbpool.queue, hb); 2247 NS_SKB(iovb)->iovcnt);
2391 card->hbpool.count++; 2248 if (card->hbpool.count < card->hbnr.max) {
2392 } 2249 skb_queue_tail(&card->hbpool.queue, hb);
2393 else 2250 card->hbpool.count++;
2394 dev_kfree_skb_any(hb); 2251 } else
2395 atomic_inc(&vcc->stats->rx_drop); 2252 dev_kfree_skb_any(hb);
2396 } 2253 atomic_inc(&vcc->stats->rx_drop);
2397 else 2254 } else {
2398 { 2255 /* Copy the small buffer to the huge buffer */
2399 /* Copy the small buffer to the huge buffer */ 2256 sb = (struct sk_buff *)iov->iov_base;
2400 sb = (struct sk_buff *) iov->iov_base; 2257 skb_copy_from_linear_data(sb, hb->data,
2401 skb_copy_from_linear_data(sb, hb->data, iov->iov_len); 2258 iov->iov_len);
2402 skb_put(hb, iov->iov_len); 2259 skb_put(hb, iov->iov_len);
2403 remaining = len - iov->iov_len; 2260 remaining = len - iov->iov_len;
2404 iov++; 2261 iov++;
2405 /* Free the small buffer */ 2262 /* Free the small buffer */
2406 push_rxbufs(card, sb); 2263 push_rxbufs(card, sb);
2407 2264
2408 /* Copy all large buffers to the huge buffer and free them */ 2265 /* Copy all large buffers to the huge buffer and free them */
2409 for (j = 1; j < NS_SKB(iovb)->iovcnt; j++) 2266 for (j = 1; j < NS_SKB(iovb)->iovcnt; j++) {
2410 { 2267 lb = (struct sk_buff *)iov->iov_base;
2411 lb = (struct sk_buff *) iov->iov_base; 2268 tocopy =
2412 tocopy = min_t(int, remaining, iov->iov_len); 2269 min_t(int, remaining, iov->iov_len);
2413 skb_copy_from_linear_data(lb, skb_tail_pointer(hb), tocopy); 2270 skb_copy_from_linear_data(lb,
2414 skb_put(hb, tocopy); 2271 skb_tail_pointer
2415 iov++; 2272 (hb), tocopy);
2416 remaining -= tocopy; 2273 skb_put(hb, tocopy);
2417 push_rxbufs(card, lb); 2274 iov++;
2418 } 2275 remaining -= tocopy;
2276 push_rxbufs(card, lb);
2277 }
2419#ifdef EXTRA_DEBUG 2278#ifdef EXTRA_DEBUG
2420 if (remaining != 0 || hb->len != len) 2279 if (remaining != 0 || hb->len != len)
2421 printk("nicstar%d: Huge buffer len mismatch.\n", card->index); 2280 printk
2281 ("nicstar%d: Huge buffer len mismatch.\n",
2282 card->index);
2422#endif /* EXTRA_DEBUG */ 2283#endif /* EXTRA_DEBUG */
2423 ATM_SKB(hb)->vcc = vcc; 2284 ATM_SKB(hb)->vcc = vcc;
2424#ifdef NS_USE_DESTRUCTORS 2285#ifdef NS_USE_DESTRUCTORS
2425 hb->destructor = ns_hb_destructor; 2286 hb->destructor = ns_hb_destructor;
2426#endif /* NS_USE_DESTRUCTORS */ 2287#endif /* NS_USE_DESTRUCTORS */
2427 __net_timestamp(hb); 2288 __net_timestamp(hb);
2428 vcc->push(vcc, hb); 2289 vcc->push(vcc, hb);
2429 atomic_inc(&vcc->stats->rx); 2290 atomic_inc(&vcc->stats->rx);
2430 } 2291 }
2431 } 2292 }
2432 2293
2433 vc->rx_iov = NULL; 2294 vc->rx_iov = NULL;
2434 recycle_iov_buf(card, iovb); 2295 recycle_iov_buf(card, iovb);
2435 } 2296 }
2436 2297
2437} 2298}
2438 2299
2439
2440
2441#ifdef NS_USE_DESTRUCTORS 2300#ifdef NS_USE_DESTRUCTORS
2442 2301
2443static void ns_sb_destructor(struct sk_buff *sb) 2302static void ns_sb_destructor(struct sk_buff *sb)
2444{ 2303{
2445 ns_dev *card; 2304 ns_dev *card;
2446 u32 stat; 2305 u32 stat;
2447 2306
2448 card = (ns_dev *) ATM_SKB(sb)->vcc->dev->dev_data; 2307 card = (ns_dev *) ATM_SKB(sb)->vcc->dev->dev_data;
2449 stat = readl(card->membase + STAT); 2308 stat = readl(card->membase + STAT);
2450 card->sbfqc = ns_stat_sfbqc_get(stat); 2309 card->sbfqc = ns_stat_sfbqc_get(stat);
2451 card->lbfqc = ns_stat_lfbqc_get(stat); 2310 card->lbfqc = ns_stat_lfbqc_get(stat);
2452 2311
2453 do 2312 do {
2454 { 2313 sb = __dev_alloc_skb(NS_SMSKBSIZE, GFP_KERNEL);
2455 sb = __dev_alloc_skb(NS_SMSKBSIZE, GFP_KERNEL); 2314 if (sb == NULL)
2456 if (sb == NULL) 2315 break;
2457 break; 2316 NS_SKB_CB(sb)->buf_type = BUF_SM;
2458 NS_SKB_CB(sb)->buf_type = BUF_SM; 2317 skb_queue_tail(&card->sbpool.queue, sb);
2459 skb_queue_tail(&card->sbpool.queue, sb); 2318 skb_reserve(sb, NS_AAL0_HEADER);
2460 skb_reserve(sb, NS_AAL0_HEADER); 2319 push_rxbufs(card, sb);
2461 push_rxbufs(card, sb); 2320 } while (card->sbfqc < card->sbnr.min);
2462 } while (card->sbfqc < card->sbnr.min);
2463} 2321}
2464 2322
2465
2466
2467static void ns_lb_destructor(struct sk_buff *lb) 2323static void ns_lb_destructor(struct sk_buff *lb)
2468{ 2324{
2469 ns_dev *card; 2325 ns_dev *card;
2470 u32 stat; 2326 u32 stat;
2471 2327
2472 card = (ns_dev *) ATM_SKB(lb)->vcc->dev->dev_data; 2328 card = (ns_dev *) ATM_SKB(lb)->vcc->dev->dev_data;
2473 stat = readl(card->membase + STAT); 2329 stat = readl(card->membase + STAT);
2474 card->sbfqc = ns_stat_sfbqc_get(stat); 2330 card->sbfqc = ns_stat_sfbqc_get(stat);
2475 card->lbfqc = ns_stat_lfbqc_get(stat); 2331 card->lbfqc = ns_stat_lfbqc_get(stat);
2476 2332
2477 do 2333 do {
2478 { 2334 lb = __dev_alloc_skb(NS_LGSKBSIZE, GFP_KERNEL);
2479 lb = __dev_alloc_skb(NS_LGSKBSIZE, GFP_KERNEL); 2335 if (lb == NULL)
2480 if (lb == NULL) 2336 break;
2481 break; 2337 NS_SKB_CB(lb)->buf_type = BUF_LG;
2482 NS_SKB_CB(lb)->buf_type = BUF_LG; 2338 skb_queue_tail(&card->lbpool.queue, lb);
2483 skb_queue_tail(&card->lbpool.queue, lb); 2339 skb_reserve(lb, NS_SMBUFSIZE);
2484 skb_reserve(lb, NS_SMBUFSIZE); 2340 push_rxbufs(card, lb);
2485 push_rxbufs(card, lb); 2341 } while (card->lbfqc < card->lbnr.min);
2486 } while (card->lbfqc < card->lbnr.min);
2487} 2342}
2488 2343
2489
2490
2491static void ns_hb_destructor(struct sk_buff *hb) 2344static void ns_hb_destructor(struct sk_buff *hb)
2492{ 2345{
2493 ns_dev *card; 2346 ns_dev *card;
2494 2347
2495 card = (ns_dev *) ATM_SKB(hb)->vcc->dev->dev_data; 2348 card = (ns_dev *) ATM_SKB(hb)->vcc->dev->dev_data;
2496 2349
2497 while (card->hbpool.count < card->hbnr.init) 2350 while (card->hbpool.count < card->hbnr.init) {
2498 { 2351 hb = __dev_alloc_skb(NS_HBUFSIZE, GFP_KERNEL);
2499 hb = __dev_alloc_skb(NS_HBUFSIZE, GFP_KERNEL); 2352 if (hb == NULL)
2500 if (hb == NULL) 2353 break;
2501 break; 2354 NS_SKB_CB(hb)->buf_type = BUF_NONE;
2502 NS_SKB_CB(hb)->buf_type = BUF_NONE; 2355 skb_queue_tail(&card->hbpool.queue, hb);
2503 skb_queue_tail(&card->hbpool.queue, hb); 2356 card->hbpool.count++;
2504 card->hbpool.count++; 2357 }
2505 }
2506} 2358}
2507 2359
2508#endif /* NS_USE_DESTRUCTORS */ 2360#endif /* NS_USE_DESTRUCTORS */
2509 2361
2510 2362static void recycle_rx_buf(ns_dev * card, struct sk_buff *skb)
2511static void recycle_rx_buf(ns_dev *card, struct sk_buff *skb)
2512{ 2363{
2513 struct ns_skb_cb *cb = NS_SKB_CB(skb); 2364 struct ns_skb_cb *cb = NS_SKB_CB(skb);
2514 2365
2515 if (unlikely(cb->buf_type == BUF_NONE)) { 2366 if (unlikely(cb->buf_type == BUF_NONE)) {
2516 printk("nicstar%d: What kind of rx buffer is this?\n", card->index); 2367 printk("nicstar%d: What kind of rx buffer is this?\n",
2368 card->index);
2517 dev_kfree_skb_any(skb); 2369 dev_kfree_skb_any(skb);
2518 } else 2370 } else
2519 push_rxbufs(card, skb); 2371 push_rxbufs(card, skb);
2520} 2372}
2521 2373
2522 2374static void recycle_iovec_rx_bufs(ns_dev * card, struct iovec *iov, int count)
2523static void recycle_iovec_rx_bufs(ns_dev *card, struct iovec *iov, int count)
2524{ 2375{
2525 while (count-- > 0) 2376 while (count-- > 0)
2526 recycle_rx_buf(card, (struct sk_buff *) (iov++)->iov_base); 2377 recycle_rx_buf(card, (struct sk_buff *)(iov++)->iov_base);
2527} 2378}
2528 2379
2529 2380static void recycle_iov_buf(ns_dev * card, struct sk_buff *iovb)
2530static void recycle_iov_buf(ns_dev *card, struct sk_buff *iovb)
2531{ 2381{
2532 if (card->iovpool.count < card->iovnr.max) 2382 if (card->iovpool.count < card->iovnr.max) {
2533 { 2383 skb_queue_tail(&card->iovpool.queue, iovb);
2534 skb_queue_tail(&card->iovpool.queue, iovb); 2384 card->iovpool.count++;
2535 card->iovpool.count++; 2385 } else
2536 } 2386 dev_kfree_skb_any(iovb);
2537 else
2538 dev_kfree_skb_any(iovb);
2539} 2387}
2540 2388
2541 2389static void dequeue_sm_buf(ns_dev * card, struct sk_buff *sb)
2542
2543static void dequeue_sm_buf(ns_dev *card, struct sk_buff *sb)
2544{ 2390{
2545 skb_unlink(sb, &card->sbpool.queue); 2391 skb_unlink(sb, &card->sbpool.queue);
2546#ifdef NS_USE_DESTRUCTORS 2392#ifdef NS_USE_DESTRUCTORS
2547 if (card->sbfqc < card->sbnr.min) 2393 if (card->sbfqc < card->sbnr.min)
2548#else 2394#else
2549 if (card->sbfqc < card->sbnr.init) 2395 if (card->sbfqc < card->sbnr.init) {
2550 { 2396 struct sk_buff *new_sb;
2551 struct sk_buff *new_sb; 2397 if ((new_sb = dev_alloc_skb(NS_SMSKBSIZE)) != NULL) {
2552 if ((new_sb = dev_alloc_skb(NS_SMSKBSIZE)) != NULL) 2398 NS_SKB_CB(new_sb)->buf_type = BUF_SM;
2553 { 2399 skb_queue_tail(&card->sbpool.queue, new_sb);
2554 NS_SKB_CB(new_sb)->buf_type = BUF_SM; 2400 skb_reserve(new_sb, NS_AAL0_HEADER);
2555 skb_queue_tail(&card->sbpool.queue, new_sb); 2401 push_rxbufs(card, new_sb);
2556 skb_reserve(new_sb, NS_AAL0_HEADER); 2402 }
2557 push_rxbufs(card, new_sb); 2403 }
2558 } 2404 if (card->sbfqc < card->sbnr.init)
2559 }
2560 if (card->sbfqc < card->sbnr.init)
2561#endif /* NS_USE_DESTRUCTORS */ 2405#endif /* NS_USE_DESTRUCTORS */
2562 { 2406 {
2563 struct sk_buff *new_sb; 2407 struct sk_buff *new_sb;
2564 if ((new_sb = dev_alloc_skb(NS_SMSKBSIZE)) != NULL) 2408 if ((new_sb = dev_alloc_skb(NS_SMSKBSIZE)) != NULL) {
2565 { 2409 NS_SKB_CB(new_sb)->buf_type = BUF_SM;
2566 NS_SKB_CB(new_sb)->buf_type = BUF_SM; 2410 skb_queue_tail(&card->sbpool.queue, new_sb);
2567 skb_queue_tail(&card->sbpool.queue, new_sb); 2411 skb_reserve(new_sb, NS_AAL0_HEADER);
2568 skb_reserve(new_sb, NS_AAL0_HEADER); 2412 push_rxbufs(card, new_sb);
2569 push_rxbufs(card, new_sb); 2413 }
2570 } 2414 }
2571 }
2572} 2415}
2573 2416
2574 2417static void dequeue_lg_buf(ns_dev * card, struct sk_buff *lb)
2575
2576static void dequeue_lg_buf(ns_dev *card, struct sk_buff *lb)
2577{ 2418{
2578 skb_unlink(lb, &card->lbpool.queue); 2419 skb_unlink(lb, &card->lbpool.queue);
2579#ifdef NS_USE_DESTRUCTORS 2420#ifdef NS_USE_DESTRUCTORS
2580 if (card->lbfqc < card->lbnr.min) 2421 if (card->lbfqc < card->lbnr.min)
2581#else 2422#else
2582 if (card->lbfqc < card->lbnr.init) 2423 if (card->lbfqc < card->lbnr.init) {
2583 { 2424 struct sk_buff *new_lb;
2584 struct sk_buff *new_lb; 2425 if ((new_lb = dev_alloc_skb(NS_LGSKBSIZE)) != NULL) {
2585 if ((new_lb = dev_alloc_skb(NS_LGSKBSIZE)) != NULL) 2426 NS_SKB_CB(new_lb)->buf_type = BUF_LG;
2586 { 2427 skb_queue_tail(&card->lbpool.queue, new_lb);
2587 NS_SKB_CB(new_lb)->buf_type = BUF_LG; 2428 skb_reserve(new_lb, NS_SMBUFSIZE);
2588 skb_queue_tail(&card->lbpool.queue, new_lb); 2429 push_rxbufs(card, new_lb);
2589 skb_reserve(new_lb, NS_SMBUFSIZE); 2430 }
2590 push_rxbufs(card, new_lb); 2431 }
2591 } 2432 if (card->lbfqc < card->lbnr.init)
2592 }
2593 if (card->lbfqc < card->lbnr.init)
2594#endif /* NS_USE_DESTRUCTORS */ 2433#endif /* NS_USE_DESTRUCTORS */
2595 { 2434 {
2596 struct sk_buff *new_lb; 2435 struct sk_buff *new_lb;
2597 if ((new_lb = dev_alloc_skb(NS_LGSKBSIZE)) != NULL) 2436 if ((new_lb = dev_alloc_skb(NS_LGSKBSIZE)) != NULL) {
2598 { 2437 NS_SKB_CB(new_lb)->buf_type = BUF_LG;
2599 NS_SKB_CB(new_lb)->buf_type = BUF_LG; 2438 skb_queue_tail(&card->lbpool.queue, new_lb);
2600 skb_queue_tail(&card->lbpool.queue, new_lb); 2439 skb_reserve(new_lb, NS_SMBUFSIZE);
2601 skb_reserve(new_lb, NS_SMBUFSIZE); 2440 push_rxbufs(card, new_lb);
2602 push_rxbufs(card, new_lb); 2441 }
2603 } 2442 }
2604 }
2605} 2443}
2606 2444
2607 2445static int ns_proc_read(struct atm_dev *dev, loff_t * pos, char *page)
2608
2609static int ns_proc_read(struct atm_dev *dev, loff_t *pos, char *page)
2610{ 2446{
2611 u32 stat; 2447 u32 stat;
2612 ns_dev *card; 2448 ns_dev *card;
2613 int left; 2449 int left;
2614 2450
2615 left = (int) *pos; 2451 left = (int)*pos;
2616 card = (ns_dev *) dev->dev_data; 2452 card = (ns_dev *) dev->dev_data;
2617 stat = readl(card->membase + STAT); 2453 stat = readl(card->membase + STAT);
2618 if (!left--) 2454 if (!left--)
2619 return sprintf(page, "Pool count min init max \n"); 2455 return sprintf(page, "Pool count min init max \n");
2620 if (!left--) 2456 if (!left--)
2621 return sprintf(page, "Small %5d %5d %5d %5d \n", 2457 return sprintf(page, "Small %5d %5d %5d %5d \n",
2622 ns_stat_sfbqc_get(stat), card->sbnr.min, card->sbnr.init, 2458 ns_stat_sfbqc_get(stat), card->sbnr.min,
2623 card->sbnr.max); 2459 card->sbnr.init, card->sbnr.max);
2624 if (!left--) 2460 if (!left--)
2625 return sprintf(page, "Large %5d %5d %5d %5d \n", 2461 return sprintf(page, "Large %5d %5d %5d %5d \n",
2626 ns_stat_lfbqc_get(stat), card->lbnr.min, card->lbnr.init, 2462 ns_stat_lfbqc_get(stat), card->lbnr.min,
2627 card->lbnr.max); 2463 card->lbnr.init, card->lbnr.max);
2628 if (!left--) 2464 if (!left--)
2629 return sprintf(page, "Huge %5d %5d %5d %5d \n", card->hbpool.count, 2465 return sprintf(page, "Huge %5d %5d %5d %5d \n",
2630 card->hbnr.min, card->hbnr.init, card->hbnr.max); 2466 card->hbpool.count, card->hbnr.min,
2631 if (!left--) 2467 card->hbnr.init, card->hbnr.max);
2632 return sprintf(page, "Iovec %5d %5d %5d %5d \n", card->iovpool.count, 2468 if (!left--)
2633 card->iovnr.min, card->iovnr.init, card->iovnr.max); 2469 return sprintf(page, "Iovec %5d %5d %5d %5d \n",
2634 if (!left--) 2470 card->iovpool.count, card->iovnr.min,
2635 { 2471 card->iovnr.init, card->iovnr.max);
2636 int retval; 2472 if (!left--) {
2637 retval = sprintf(page, "Interrupt counter: %u \n", card->intcnt); 2473 int retval;
2638 card->intcnt = 0; 2474 retval =
2639 return retval; 2475 sprintf(page, "Interrupt counter: %u \n", card->intcnt);
2640 } 2476 card->intcnt = 0;
2477 return retval;
2478 }
2641#if 0 2479#if 0
2642 /* Dump 25.6 Mbps PHY registers */ 2480 /* Dump 25.6 Mbps PHY registers */
2643 /* Now there's a 25.6 Mbps PHY driver this code isn't needed. I left it 2481 /* Now there's a 25.6 Mbps PHY driver this code isn't needed. I left it
2644 here just in case it's needed for debugging. */ 2482 here just in case it's needed for debugging. */
2645 if (card->max_pcr == ATM_25_PCR && !left--) 2483 if (card->max_pcr == ATM_25_PCR && !left--) {
2646 { 2484 u32 phy_regs[4];
2647 u32 phy_regs[4]; 2485 u32 i;
2648 u32 i; 2486
2649 2487 for (i = 0; i < 4; i++) {
2650 for (i = 0; i < 4; i++) 2488 while (CMD_BUSY(card)) ;
2651 { 2489 writel(NS_CMD_READ_UTILITY | 0x00000200 | i,
2652 while (CMD_BUSY(card)); 2490 card->membase + CMD);
2653 writel(NS_CMD_READ_UTILITY | 0x00000200 | i, card->membase + CMD); 2491 while (CMD_BUSY(card)) ;
2654 while (CMD_BUSY(card)); 2492 phy_regs[i] = readl(card->membase + DR0) & 0x000000FF;
2655 phy_regs[i] = readl(card->membase + DR0) & 0x000000FF; 2493 }
2656 } 2494
2657 2495 return sprintf(page, "PHY regs: 0x%02X 0x%02X 0x%02X 0x%02X \n",
2658 return sprintf(page, "PHY regs: 0x%02X 0x%02X 0x%02X 0x%02X \n", 2496 phy_regs[0], phy_regs[1], phy_regs[2],
2659 phy_regs[0], phy_regs[1], phy_regs[2], phy_regs[3]); 2497 phy_regs[3]);
2660 } 2498 }
2661#endif /* 0 - Dump 25.6 Mbps PHY registers */ 2499#endif /* 0 - Dump 25.6 Mbps PHY registers */
2662#if 0 2500#if 0
2663 /* Dump TST */ 2501 /* Dump TST */
2664 if (left-- < NS_TST_NUM_ENTRIES) 2502 if (left-- < NS_TST_NUM_ENTRIES) {
2665 { 2503 if (card->tste2vc[left + 1] == NULL)
2666 if (card->tste2vc[left + 1] == NULL) 2504 return sprintf(page, "%5d - VBR/UBR \n", left + 1);
2667 return sprintf(page, "%5d - VBR/UBR \n", left + 1); 2505 else
2668 else 2506 return sprintf(page, "%5d - %d %d \n", left + 1,
2669 return sprintf(page, "%5d - %d %d \n", left + 1, 2507 card->tste2vc[left + 1]->tx_vcc->vpi,
2670 card->tste2vc[left + 1]->tx_vcc->vpi, 2508 card->tste2vc[left + 1]->tx_vcc->vci);
2671 card->tste2vc[left + 1]->tx_vcc->vci); 2509 }
2672 }
2673#endif /* 0 */ 2510#endif /* 0 */
2674 return 0; 2511 return 0;
2675} 2512}
2676 2513
2677 2514static int ns_ioctl(struct atm_dev *dev, unsigned int cmd, void __user * arg)
2678
2679static int ns_ioctl(struct atm_dev *dev, unsigned int cmd, void __user *arg)
2680{ 2515{
2681 ns_dev *card; 2516 ns_dev *card;
2682 pool_levels pl; 2517 pool_levels pl;
2683 long btype; 2518 long btype;
2684 unsigned long flags; 2519 unsigned long flags;
2685 2520
2686 card = dev->dev_data; 2521 card = dev->dev_data;
2687 switch (cmd) 2522 switch (cmd) {
2688 { 2523 case NS_GETPSTAT:
2689 case NS_GETPSTAT: 2524 if (get_user
2690 if (get_user(pl.buftype, &((pool_levels __user *) arg)->buftype)) 2525 (pl.buftype, &((pool_levels __user *) arg)->buftype))
2691 return -EFAULT; 2526 return -EFAULT;
2692 switch (pl.buftype) 2527 switch (pl.buftype) {
2693 { 2528 case NS_BUFTYPE_SMALL:
2694 case NS_BUFTYPE_SMALL: 2529 pl.count =
2695 pl.count = ns_stat_sfbqc_get(readl(card->membase + STAT)); 2530 ns_stat_sfbqc_get(readl(card->membase + STAT));
2696 pl.level.min = card->sbnr.min; 2531 pl.level.min = card->sbnr.min;
2697 pl.level.init = card->sbnr.init; 2532 pl.level.init = card->sbnr.init;
2698 pl.level.max = card->sbnr.max; 2533 pl.level.max = card->sbnr.max;
2699 break; 2534 break;
2700 2535
2701 case NS_BUFTYPE_LARGE: 2536 case NS_BUFTYPE_LARGE:
2702 pl.count = ns_stat_lfbqc_get(readl(card->membase + STAT)); 2537 pl.count =
2703 pl.level.min = card->lbnr.min; 2538 ns_stat_lfbqc_get(readl(card->membase + STAT));
2704 pl.level.init = card->lbnr.init; 2539 pl.level.min = card->lbnr.min;
2705 pl.level.max = card->lbnr.max; 2540 pl.level.init = card->lbnr.init;
2706 break; 2541 pl.level.max = card->lbnr.max;
2707 2542 break;
2708 case NS_BUFTYPE_HUGE: 2543
2709 pl.count = card->hbpool.count; 2544 case NS_BUFTYPE_HUGE:
2710 pl.level.min = card->hbnr.min; 2545 pl.count = card->hbpool.count;
2711 pl.level.init = card->hbnr.init; 2546 pl.level.min = card->hbnr.min;
2712 pl.level.max = card->hbnr.max; 2547 pl.level.init = card->hbnr.init;
2713 break; 2548 pl.level.max = card->hbnr.max;
2714 2549 break;
2715 case NS_BUFTYPE_IOVEC: 2550
2716 pl.count = card->iovpool.count; 2551 case NS_BUFTYPE_IOVEC:
2717 pl.level.min = card->iovnr.min; 2552 pl.count = card->iovpool.count;
2718 pl.level.init = card->iovnr.init; 2553 pl.level.min = card->iovnr.min;
2719 pl.level.max = card->iovnr.max; 2554 pl.level.init = card->iovnr.init;
2720 break; 2555 pl.level.max = card->iovnr.max;
2721 2556 break;
2722 default: 2557
2723 return -ENOIOCTLCMD; 2558 default:
2724 2559 return -ENOIOCTLCMD;
2725 } 2560
2726 if (!copy_to_user((pool_levels __user *) arg, &pl, sizeof(pl))) 2561 }
2727 return (sizeof(pl)); 2562 if (!copy_to_user((pool_levels __user *) arg, &pl, sizeof(pl)))
2728 else 2563 return (sizeof(pl));
2729 return -EFAULT; 2564 else
2730 2565 return -EFAULT;
2731 case NS_SETBUFLEV: 2566
2732 if (!capable(CAP_NET_ADMIN)) 2567 case NS_SETBUFLEV:
2733 return -EPERM; 2568 if (!capable(CAP_NET_ADMIN))
2734 if (copy_from_user(&pl, (pool_levels __user *) arg, sizeof(pl))) 2569 return -EPERM;
2735 return -EFAULT; 2570 if (copy_from_user(&pl, (pool_levels __user *) arg, sizeof(pl)))
2736 if (pl.level.min >= pl.level.init || pl.level.init >= pl.level.max) 2571 return -EFAULT;
2737 return -EINVAL; 2572 if (pl.level.min >= pl.level.init
2738 if (pl.level.min == 0) 2573 || pl.level.init >= pl.level.max)
2739 return -EINVAL; 2574 return -EINVAL;
2740 switch (pl.buftype) 2575 if (pl.level.min == 0)
2741 { 2576 return -EINVAL;
2742 case NS_BUFTYPE_SMALL: 2577 switch (pl.buftype) {
2743 if (pl.level.max > TOP_SB) 2578 case NS_BUFTYPE_SMALL:
2744 return -EINVAL; 2579 if (pl.level.max > TOP_SB)
2745 card->sbnr.min = pl.level.min; 2580 return -EINVAL;
2746 card->sbnr.init = pl.level.init; 2581 card->sbnr.min = pl.level.min;
2747 card->sbnr.max = pl.level.max; 2582 card->sbnr.init = pl.level.init;
2748 break; 2583 card->sbnr.max = pl.level.max;
2749 2584 break;
2750 case NS_BUFTYPE_LARGE: 2585
2751 if (pl.level.max > TOP_LB) 2586 case NS_BUFTYPE_LARGE:
2752 return -EINVAL; 2587 if (pl.level.max > TOP_LB)
2753 card->lbnr.min = pl.level.min; 2588 return -EINVAL;
2754 card->lbnr.init = pl.level.init; 2589 card->lbnr.min = pl.level.min;
2755 card->lbnr.max = pl.level.max; 2590 card->lbnr.init = pl.level.init;
2756 break; 2591 card->lbnr.max = pl.level.max;
2757 2592 break;
2758 case NS_BUFTYPE_HUGE: 2593
2759 if (pl.level.max > TOP_HB) 2594 case NS_BUFTYPE_HUGE:
2760 return -EINVAL; 2595 if (pl.level.max > TOP_HB)
2761 card->hbnr.min = pl.level.min; 2596 return -EINVAL;
2762 card->hbnr.init = pl.level.init; 2597 card->hbnr.min = pl.level.min;
2763 card->hbnr.max = pl.level.max; 2598 card->hbnr.init = pl.level.init;
2764 break; 2599 card->hbnr.max = pl.level.max;
2765 2600 break;
2766 case NS_BUFTYPE_IOVEC: 2601
2767 if (pl.level.max > TOP_IOVB) 2602 case NS_BUFTYPE_IOVEC:
2768 return -EINVAL; 2603 if (pl.level.max > TOP_IOVB)
2769 card->iovnr.min = pl.level.min; 2604 return -EINVAL;
2770 card->iovnr.init = pl.level.init; 2605 card->iovnr.min = pl.level.min;
2771 card->iovnr.max = pl.level.max; 2606 card->iovnr.init = pl.level.init;
2772 break; 2607 card->iovnr.max = pl.level.max;
2773 2608 break;
2774 default: 2609
2775 return -EINVAL; 2610 default:
2776 2611 return -EINVAL;
2777 } 2612
2778 return 0; 2613 }
2779 2614 return 0;
2780 case NS_ADJBUFLEV: 2615
2781 if (!capable(CAP_NET_ADMIN)) 2616 case NS_ADJBUFLEV:
2782 return -EPERM; 2617 if (!capable(CAP_NET_ADMIN))
2783 btype = (long) arg; /* a long is the same size as a pointer or bigger */ 2618 return -EPERM;
2784 switch (btype) 2619 btype = (long)arg; /* a long is the same size as a pointer or bigger */
2785 { 2620 switch (btype) {
2786 case NS_BUFTYPE_SMALL: 2621 case NS_BUFTYPE_SMALL:
2787 while (card->sbfqc < card->sbnr.init) 2622 while (card->sbfqc < card->sbnr.init) {
2788 { 2623 struct sk_buff *sb;
2789 struct sk_buff *sb; 2624
2790 2625 sb = __dev_alloc_skb(NS_SMSKBSIZE, GFP_KERNEL);
2791 sb = __dev_alloc_skb(NS_SMSKBSIZE, GFP_KERNEL); 2626 if (sb == NULL)
2792 if (sb == NULL) 2627 return -ENOMEM;
2793 return -ENOMEM; 2628 NS_SKB_CB(sb)->buf_type = BUF_SM;
2794 NS_SKB_CB(sb)->buf_type = BUF_SM; 2629 skb_queue_tail(&card->sbpool.queue, sb);
2795 skb_queue_tail(&card->sbpool.queue, sb); 2630 skb_reserve(sb, NS_AAL0_HEADER);
2796 skb_reserve(sb, NS_AAL0_HEADER); 2631 push_rxbufs(card, sb);
2797 push_rxbufs(card, sb); 2632 }
2798 } 2633 break;
2799 break; 2634
2800 2635 case NS_BUFTYPE_LARGE:
2801 case NS_BUFTYPE_LARGE: 2636 while (card->lbfqc < card->lbnr.init) {
2802 while (card->lbfqc < card->lbnr.init) 2637 struct sk_buff *lb;
2803 { 2638
2804 struct sk_buff *lb; 2639 lb = __dev_alloc_skb(NS_LGSKBSIZE, GFP_KERNEL);
2805 2640 if (lb == NULL)
2806 lb = __dev_alloc_skb(NS_LGSKBSIZE, GFP_KERNEL); 2641 return -ENOMEM;
2807 if (lb == NULL) 2642 NS_SKB_CB(lb)->buf_type = BUF_LG;
2808 return -ENOMEM; 2643 skb_queue_tail(&card->lbpool.queue, lb);
2809 NS_SKB_CB(lb)->buf_type = BUF_LG; 2644 skb_reserve(lb, NS_SMBUFSIZE);
2810 skb_queue_tail(&card->lbpool.queue, lb); 2645 push_rxbufs(card, lb);
2811 skb_reserve(lb, NS_SMBUFSIZE); 2646 }
2812 push_rxbufs(card, lb); 2647 break;
2813 } 2648
2814 break; 2649 case NS_BUFTYPE_HUGE:
2815 2650 while (card->hbpool.count > card->hbnr.init) {
2816 case NS_BUFTYPE_HUGE: 2651 struct sk_buff *hb;
2817 while (card->hbpool.count > card->hbnr.init) 2652
2818 { 2653 spin_lock_irqsave(&card->int_lock, flags);
2819 struct sk_buff *hb; 2654 hb = skb_dequeue(&card->hbpool.queue);
2820 2655 card->hbpool.count--;
2821 spin_lock_irqsave(&card->int_lock, flags); 2656 spin_unlock_irqrestore(&card->int_lock, flags);
2822 hb = skb_dequeue(&card->hbpool.queue); 2657 if (hb == NULL)
2823 card->hbpool.count--; 2658 printk
2824 spin_unlock_irqrestore(&card->int_lock, flags); 2659 ("nicstar%d: huge buffer count inconsistent.\n",
2825 if (hb == NULL) 2660 card->index);
2826 printk("nicstar%d: huge buffer count inconsistent.\n", 2661 else
2827 card->index); 2662 dev_kfree_skb_any(hb);
2828 else 2663
2829 dev_kfree_skb_any(hb); 2664 }
2830 2665 while (card->hbpool.count < card->hbnr.init) {
2831 } 2666 struct sk_buff *hb;
2832 while (card->hbpool.count < card->hbnr.init) 2667
2833 { 2668 hb = __dev_alloc_skb(NS_HBUFSIZE, GFP_KERNEL);
2834 struct sk_buff *hb; 2669 if (hb == NULL)
2835 2670 return -ENOMEM;
2836 hb = __dev_alloc_skb(NS_HBUFSIZE, GFP_KERNEL); 2671 NS_SKB_CB(hb)->buf_type = BUF_NONE;
2837 if (hb == NULL) 2672 spin_lock_irqsave(&card->int_lock, flags);
2838 return -ENOMEM; 2673 skb_queue_tail(&card->hbpool.queue, hb);
2839 NS_SKB_CB(hb)->buf_type = BUF_NONE; 2674 card->hbpool.count++;
2840 spin_lock_irqsave(&card->int_lock, flags); 2675 spin_unlock_irqrestore(&card->int_lock, flags);
2841 skb_queue_tail(&card->hbpool.queue, hb); 2676 }
2842 card->hbpool.count++; 2677 break;
2843 spin_unlock_irqrestore(&card->int_lock, flags); 2678
2844 } 2679 case NS_BUFTYPE_IOVEC:
2845 break; 2680 while (card->iovpool.count > card->iovnr.init) {
2846 2681 struct sk_buff *iovb;
2847 case NS_BUFTYPE_IOVEC: 2682
2848 while (card->iovpool.count > card->iovnr.init) 2683 spin_lock_irqsave(&card->int_lock, flags);
2849 { 2684 iovb = skb_dequeue(&card->iovpool.queue);
2850 struct sk_buff *iovb; 2685 card->iovpool.count--;
2851 2686 spin_unlock_irqrestore(&card->int_lock, flags);
2852 spin_lock_irqsave(&card->int_lock, flags); 2687 if (iovb == NULL)
2853 iovb = skb_dequeue(&card->iovpool.queue); 2688 printk
2854 card->iovpool.count--; 2689 ("nicstar%d: iovec buffer count inconsistent.\n",
2855 spin_unlock_irqrestore(&card->int_lock, flags); 2690 card->index);
2856 if (iovb == NULL) 2691 else
2857 printk("nicstar%d: iovec buffer count inconsistent.\n", 2692 dev_kfree_skb_any(iovb);
2858 card->index); 2693
2859 else 2694 }
2860 dev_kfree_skb_any(iovb); 2695 while (card->iovpool.count < card->iovnr.init) {
2861 2696 struct sk_buff *iovb;
2862 } 2697
2863 while (card->iovpool.count < card->iovnr.init) 2698 iovb = alloc_skb(NS_IOVBUFSIZE, GFP_KERNEL);
2864 { 2699 if (iovb == NULL)
2865 struct sk_buff *iovb; 2700 return -ENOMEM;
2866 2701 NS_SKB_CB(iovb)->buf_type = BUF_NONE;
2867 iovb = alloc_skb(NS_IOVBUFSIZE, GFP_KERNEL); 2702 spin_lock_irqsave(&card->int_lock, flags);
2868 if (iovb == NULL) 2703 skb_queue_tail(&card->iovpool.queue, iovb);
2869 return -ENOMEM; 2704 card->iovpool.count++;
2870 NS_SKB_CB(iovb)->buf_type = BUF_NONE; 2705 spin_unlock_irqrestore(&card->int_lock, flags);
2871 spin_lock_irqsave(&card->int_lock, flags); 2706 }
2872 skb_queue_tail(&card->iovpool.queue, iovb); 2707 break;
2873 card->iovpool.count++; 2708
2874 spin_unlock_irqrestore(&card->int_lock, flags); 2709 default:
2875 } 2710 return -EINVAL;
2876 break; 2711
2877 2712 }
2878 default: 2713 return 0;
2879 return -EINVAL; 2714
2880 2715 default:
2881 } 2716 if (dev->phy && dev->phy->ioctl) {
2882 return 0; 2717 return dev->phy->ioctl(dev, cmd, arg);
2883 2718 } else {
2884 default: 2719 printk("nicstar%d: %s == NULL \n", card->index,
2885 if (dev->phy && dev->phy->ioctl) { 2720 dev->phy ? "dev->phy->ioctl" : "dev->phy");
2886 return dev->phy->ioctl(dev, cmd, arg); 2721 return -ENOIOCTLCMD;
2887 } 2722 }
2888 else { 2723 }
2889 printk("nicstar%d: %s == NULL \n", card->index,
2890 dev->phy ? "dev->phy->ioctl" : "dev->phy");
2891 return -ENOIOCTLCMD;
2892 }
2893 }
2894} 2724}
2895 2725
2896 2726static void which_list(ns_dev * card, struct sk_buff *skb)
2897static void which_list(ns_dev *card, struct sk_buff *skb)
2898{ 2727{
2899 printk("skb buf_type: 0x%08x\n", NS_SKB_CB(skb)->buf_type); 2728 printk("skb buf_type: 0x%08x\n", NS_SKB_CB(skb)->buf_type);
2900} 2729}
2901 2730
2902
2903static void ns_poll(unsigned long arg) 2731static void ns_poll(unsigned long arg)
2904{ 2732{
2905 int i; 2733 int i;
2906 ns_dev *card; 2734 ns_dev *card;
2907 unsigned long flags; 2735 unsigned long flags;
2908 u32 stat_r, stat_w; 2736 u32 stat_r, stat_w;
2909 2737
2910 PRINTK("nicstar: Entering ns_poll().\n"); 2738 PRINTK("nicstar: Entering ns_poll().\n");
2911 for (i = 0; i < num_cards; i++) 2739 for (i = 0; i < num_cards; i++) {
2912 { 2740 card = cards[i];
2913 card = cards[i]; 2741 if (spin_is_locked(&card->int_lock)) {
2914 if (spin_is_locked(&card->int_lock)) { 2742 /* Probably it isn't worth spinning */
2915 /* Probably it isn't worth spinning */ 2743 continue;
2916 continue; 2744 }
2917 } 2745 spin_lock_irqsave(&card->int_lock, flags);
2918 spin_lock_irqsave(&card->int_lock, flags); 2746
2919 2747 stat_w = 0;
2920 stat_w = 0; 2748 stat_r = readl(card->membase + STAT);
2921 stat_r = readl(card->membase + STAT); 2749 if (stat_r & NS_STAT_TSIF)
2922 if (stat_r & NS_STAT_TSIF) 2750 stat_w |= NS_STAT_TSIF;
2923 stat_w |= NS_STAT_TSIF; 2751 if (stat_r & NS_STAT_EOPDU)
2924 if (stat_r & NS_STAT_EOPDU) 2752 stat_w |= NS_STAT_EOPDU;
2925 stat_w |= NS_STAT_EOPDU; 2753
2926 2754 process_tsq(card);
2927 process_tsq(card); 2755 process_rsq(card);
2928 process_rsq(card); 2756
2929 2757 writel(stat_w, card->membase + STAT);
2930 writel(stat_w, card->membase + STAT); 2758 spin_unlock_irqrestore(&card->int_lock, flags);
2931 spin_unlock_irqrestore(&card->int_lock, flags); 2759 }
2932 } 2760 mod_timer(&ns_timer, jiffies + NS_POLL_PERIOD);
2933 mod_timer(&ns_timer, jiffies + NS_POLL_PERIOD); 2761 PRINTK("nicstar: Leaving ns_poll().\n");
2934 PRINTK("nicstar: Leaving ns_poll().\n");
2935} 2762}
2936 2763
2937
2938
2939static int ns_parse_mac(char *mac, unsigned char *esi) 2764static int ns_parse_mac(char *mac, unsigned char *esi)
2940{ 2765{
2941 int i, j; 2766 int i, j;
2942 short byte1, byte0; 2767 short byte1, byte0;
2943 2768
2944 if (mac == NULL || esi == NULL) 2769 if (mac == NULL || esi == NULL)
2945 return -1; 2770 return -1;
2946 j = 0; 2771 j = 0;
2947 for (i = 0; i < 6; i++) 2772 for (i = 0; i < 6; i++) {
2948 { 2773 if ((byte1 = ns_h2i(mac[j++])) < 0)
2949 if ((byte1 = ns_h2i(mac[j++])) < 0) 2774 return -1;
2950 return -1; 2775 if ((byte0 = ns_h2i(mac[j++])) < 0)
2951 if ((byte0 = ns_h2i(mac[j++])) < 0) 2776 return -1;
2952 return -1; 2777 esi[i] = (unsigned char)(byte1 * 16 + byte0);
2953 esi[i] = (unsigned char) (byte1 * 16 + byte0); 2778 if (i < 5) {
2954 if (i < 5) 2779 if (mac[j++] != ':')
2955 { 2780 return -1;
2956 if (mac[j++] != ':') 2781 }
2957 return -1; 2782 }
2958 } 2783 return 0;
2959 }
2960 return 0;
2961} 2784}
2962 2785
2963
2964
2965static short ns_h2i(char c) 2786static short ns_h2i(char c)
2966{ 2787{
2967 if (c >= '0' && c <= '9') 2788 if (c >= '0' && c <= '9')
2968 return (short) (c - '0'); 2789 return (short)(c - '0');
2969 if (c >= 'A' && c <= 'F') 2790 if (c >= 'A' && c <= 'F')
2970 return (short) (c - 'A' + 10); 2791 return (short)(c - 'A' + 10);
2971 if (c >= 'a' && c <= 'f') 2792 if (c >= 'a' && c <= 'f')
2972 return (short) (c - 'a' + 10); 2793 return (short)(c - 'a' + 10);
2973 return -1; 2794 return -1;
2974} 2795}
2975 2796
2976
2977
2978static void ns_phy_put(struct atm_dev *dev, unsigned char value, 2797static void ns_phy_put(struct atm_dev *dev, unsigned char value,
2979 unsigned long addr) 2798 unsigned long addr)
2980{ 2799{
2981 ns_dev *card; 2800 ns_dev *card;
2982 unsigned long flags; 2801 unsigned long flags;
2983 2802
2984 card = dev->dev_data; 2803 card = dev->dev_data;
2985 spin_lock_irqsave(&card->res_lock, flags); 2804 spin_lock_irqsave(&card->res_lock, flags);
2986 while(CMD_BUSY(card)); 2805 while (CMD_BUSY(card)) ;
2987 writel((unsigned long) value, card->membase + DR0); 2806 writel((unsigned long)value, card->membase + DR0);
2988 writel(NS_CMD_WRITE_UTILITY | 0x00000200 | (addr & 0x000000FF), 2807 writel(NS_CMD_WRITE_UTILITY | 0x00000200 | (addr & 0x000000FF),
2989 card->membase + CMD); 2808 card->membase + CMD);
2990 spin_unlock_irqrestore(&card->res_lock, flags); 2809 spin_unlock_irqrestore(&card->res_lock, flags);
2991} 2810}
2992 2811
2993
2994
2995static unsigned char ns_phy_get(struct atm_dev *dev, unsigned long addr) 2812static unsigned char ns_phy_get(struct atm_dev *dev, unsigned long addr)
2996{ 2813{
2997 ns_dev *card; 2814 ns_dev *card;
2998 unsigned long flags; 2815 unsigned long flags;
2999 unsigned long data; 2816 unsigned long data;
3000 2817
3001 card = dev->dev_data; 2818 card = dev->dev_data;
3002 spin_lock_irqsave(&card->res_lock, flags); 2819 spin_lock_irqsave(&card->res_lock, flags);
3003 while(CMD_BUSY(card)); 2820 while (CMD_BUSY(card)) ;
3004 writel(NS_CMD_READ_UTILITY | 0x00000200 | (addr & 0x000000FF), 2821 writel(NS_CMD_READ_UTILITY | 0x00000200 | (addr & 0x000000FF),
3005 card->membase + CMD); 2822 card->membase + CMD);
3006 while(CMD_BUSY(card)); 2823 while (CMD_BUSY(card)) ;
3007 data = readl(card->membase + DR0) & 0x000000FF; 2824 data = readl(card->membase + DR0) & 0x000000FF;
3008 spin_unlock_irqrestore(&card->res_lock, flags); 2825 spin_unlock_irqrestore(&card->res_lock, flags);
3009 return (unsigned char) data; 2826 return (unsigned char)data;
3010} 2827}
3011 2828
3012
3013
3014module_init(nicstar_init); 2829module_init(nicstar_init);
3015module_exit(nicstar_cleanup); 2830module_exit(nicstar_cleanup);
diff --git a/drivers/atm/nicstar.h b/drivers/atm/nicstar.h
index 6010e3daa6a2..43eb2db1fb88 100644
--- a/drivers/atm/nicstar.h
+++ b/drivers/atm/nicstar.h
@@ -1,5 +1,4 @@
1/****************************************************************************** 1/*
2 *
3 * nicstar.h 2 * nicstar.h
4 * 3 *
5 * Header file for the nicstar device driver. 4 * Header file for the nicstar device driver.
@@ -8,15 +7,12 @@
8 * PowerPC support by Jay Talbott (jay_talbott@mcg.mot.com) April 1999 7 * PowerPC support by Jay Talbott (jay_talbott@mcg.mot.com) April 1999
9 * 8 *
10 * (C) INESC 1998 9 * (C) INESC 1998
11 * 10 */
12 ******************************************************************************/
13
14 11
15#ifndef _LINUX_NICSTAR_H_ 12#ifndef _LINUX_NICSTAR_H_
16#define _LINUX_NICSTAR_H_ 13#define _LINUX_NICSTAR_H_
17 14
18 15/* Includes */
19/* Includes *******************************************************************/
20 16
21#include <linux/types.h> 17#include <linux/types.h>
22#include <linux/pci.h> 18#include <linux/pci.h>
@@ -25,12 +21,11 @@
25#include <linux/atmdev.h> 21#include <linux/atmdev.h>
26#include <linux/atm_nicstar.h> 22#include <linux/atm_nicstar.h>
27 23
28 24/* Options */
29/* Options ********************************************************************/
30 25
31#define NS_MAX_CARDS 4 /* Maximum number of NICStAR based cards 26#define NS_MAX_CARDS 4 /* Maximum number of NICStAR based cards
32 controlled by the device driver. Must 27 controlled by the device driver. Must
33 be <= 5 */ 28 be <= 5 */
34 29
35#undef RCQ_SUPPORT /* Do not define this for now */ 30#undef RCQ_SUPPORT /* Do not define this for now */
36 31
@@ -43,7 +38,7 @@
43#define NS_VPIBITS 2 /* 0, 1, 2, or 8 */ 38#define NS_VPIBITS 2 /* 0, 1, 2, or 8 */
44 39
45#define NS_MAX_RCTSIZE 4096 /* Number of entries. 4096 or 16384. 40#define NS_MAX_RCTSIZE 4096 /* Number of entries. 4096 or 16384.
46 Define 4096 only if (all) your card(s) 41 Define 4096 only if (all) your card(s)
47 have 32K x 32bit SRAM, in which case 42 have 32K x 32bit SRAM, in which case
48 setting this to 16384 will just waste a 43 setting this to 16384 will just waste a
49 lot of memory. 44 lot of memory.
@@ -51,33 +46,32 @@
51 128K x 32bit SRAM will limit the maximum 46 128K x 32bit SRAM will limit the maximum
52 VCI. */ 47 VCI. */
53 48
54/*#define NS_PCI_LATENCY 64*/ /* Must be a multiple of 32 */ 49 /*#define NS_PCI_LATENCY 64*//* Must be a multiple of 32 */
55 50
56 /* Number of buffers initially allocated */ 51 /* Number of buffers initially allocated */
57#define NUM_SB 32 /* Must be even */ 52#define NUM_SB 32 /* Must be even */
58#define NUM_LB 24 /* Must be even */ 53#define NUM_LB 24 /* Must be even */
59#define NUM_HB 8 /* Pre-allocated huge buffers */ 54#define NUM_HB 8 /* Pre-allocated huge buffers */
60#define NUM_IOVB 48 /* Iovec buffers */ 55#define NUM_IOVB 48 /* Iovec buffers */
61 56
62 /* Lower level for count of buffers */ 57 /* Lower level for count of buffers */
63#define MIN_SB 8 /* Must be even */ 58#define MIN_SB 8 /* Must be even */
64#define MIN_LB 8 /* Must be even */ 59#define MIN_LB 8 /* Must be even */
65#define MIN_HB 6 60#define MIN_HB 6
66#define MIN_IOVB 8 61#define MIN_IOVB 8
67 62
68 /* Upper level for count of buffers */ 63 /* Upper level for count of buffers */
69#define MAX_SB 64 /* Must be even, <= 508 */ 64#define MAX_SB 64 /* Must be even, <= 508 */
70#define MAX_LB 48 /* Must be even, <= 508 */ 65#define MAX_LB 48 /* Must be even, <= 508 */
71#define MAX_HB 10 66#define MAX_HB 10
72#define MAX_IOVB 80 67#define MAX_IOVB 80
73 68
74 /* These are the absolute maximum allowed for the ioctl() */ 69 /* These are the absolute maximum allowed for the ioctl() */
75#define TOP_SB 256 /* Must be even, <= 508 */ 70#define TOP_SB 256 /* Must be even, <= 508 */
76#define TOP_LB 128 /* Must be even, <= 508 */ 71#define TOP_LB 128 /* Must be even, <= 508 */
77#define TOP_HB 64 72#define TOP_HB 64
78#define TOP_IOVB 256 73#define TOP_IOVB 256
79 74
80
81#define MAX_TBD_PER_VC 1 /* Number of TBDs before a TSR */ 75#define MAX_TBD_PER_VC 1 /* Number of TBDs before a TSR */
82#define MAX_TBD_PER_SCQ 10 /* Only meaningful for variable rate SCQs */ 76#define MAX_TBD_PER_SCQ 10 /* Only meaningful for variable rate SCQs */
83 77
@@ -89,15 +83,12 @@
89 83
90#define PCR_TOLERANCE (1.0001) 84#define PCR_TOLERANCE (1.0001)
91 85
92 86/* ESI stuff */
93
94/* ESI stuff ******************************************************************/
95 87
96#define NICSTAR_EPROM_MAC_ADDR_OFFSET 0x6C 88#define NICSTAR_EPROM_MAC_ADDR_OFFSET 0x6C
97#define NICSTAR_EPROM_MAC_ADDR_OFFSET_ALT 0xF6 89#define NICSTAR_EPROM_MAC_ADDR_OFFSET_ALT 0xF6
98 90
99 91/* #defines */
100/* #defines *******************************************************************/
101 92
102#define NS_IOREMAP_SIZE 4096 93#define NS_IOREMAP_SIZE 4096
103 94
@@ -123,22 +114,19 @@
123#define NS_SMSKBSIZE (NS_SMBUFSIZE + NS_AAL0_HEADER) 114#define NS_SMSKBSIZE (NS_SMBUFSIZE + NS_AAL0_HEADER)
124#define NS_LGSKBSIZE (NS_SMBUFSIZE + NS_LGBUFSIZE) 115#define NS_LGSKBSIZE (NS_SMBUFSIZE + NS_LGBUFSIZE)
125 116
117/* NICStAR structures located in host memory */
126 118
127/* NICStAR structures located in host memory **********************************/ 119/*
128 120 * RSQ - Receive Status Queue
129
130
131/* RSQ - Receive Status Queue
132 * 121 *
133 * Written by the NICStAR, read by the device driver. 122 * Written by the NICStAR, read by the device driver.
134 */ 123 */
135 124
136typedef struct ns_rsqe 125typedef struct ns_rsqe {
137{ 126 u32 word_1;
138 u32 word_1; 127 u32 buffer_handle;
139 u32 buffer_handle; 128 u32 final_aal5_crc32;
140 u32 final_aal5_crc32; 129 u32 word_4;
141 u32 word_4;
142} ns_rsqe; 130} ns_rsqe;
143 131
144#define ns_rsqe_vpi(ns_rsqep) \ 132#define ns_rsqe_vpi(ns_rsqep) \
@@ -175,30 +163,27 @@ typedef struct ns_rsqe
175#define ns_rsqe_cellcount(ns_rsqep) \ 163#define ns_rsqe_cellcount(ns_rsqep) \
176 (le32_to_cpu((ns_rsqep)->word_4) & 0x000001FF) 164 (le32_to_cpu((ns_rsqep)->word_4) & 0x000001FF)
177#define ns_rsqe_init(ns_rsqep) \ 165#define ns_rsqe_init(ns_rsqep) \
178 ((ns_rsqep)->word_4 = cpu_to_le32(0x00000000)) 166 ((ns_rsqep)->word_4 = cpu_to_le32(0x00000000))
179 167
180#define NS_RSQ_NUM_ENTRIES (NS_RSQSIZE / 16) 168#define NS_RSQ_NUM_ENTRIES (NS_RSQSIZE / 16)
181#define NS_RSQ_ALIGNMENT NS_RSQSIZE 169#define NS_RSQ_ALIGNMENT NS_RSQSIZE
182 170
183 171/*
184 172 * RCQ - Raw Cell Queue
185/* RCQ - Raw Cell Queue
186 * 173 *
187 * Written by the NICStAR, read by the device driver. 174 * Written by the NICStAR, read by the device driver.
188 */ 175 */
189 176
190typedef struct cell_payload 177typedef struct cell_payload {
191{ 178 u32 word[12];
192 u32 word[12];
193} cell_payload; 179} cell_payload;
194 180
195typedef struct ns_rcqe 181typedef struct ns_rcqe {
196{ 182 u32 word_1;
197 u32 word_1; 183 u32 word_2;
198 u32 word_2; 184 u32 word_3;
199 u32 word_3; 185 u32 word_4;
200 u32 word_4; 186 cell_payload payload;
201 cell_payload payload;
202} ns_rcqe; 187} ns_rcqe;
203 188
204#define NS_RCQE_SIZE 64 /* bytes */ 189#define NS_RCQE_SIZE 64 /* bytes */
@@ -210,28 +195,25 @@ typedef struct ns_rcqe
210#define ns_rcqe_nextbufhandle(ns_rcqep) \ 195#define ns_rcqe_nextbufhandle(ns_rcqep) \
211 (le32_to_cpu((ns_rcqep)->word_2)) 196 (le32_to_cpu((ns_rcqep)->word_2))
212 197
213 198/*
214 199 * SCQ - Segmentation Channel Queue
215/* SCQ - Segmentation Channel Queue
216 * 200 *
217 * Written by the device driver, read by the NICStAR. 201 * Written by the device driver, read by the NICStAR.
218 */ 202 */
219 203
220typedef struct ns_scqe 204typedef struct ns_scqe {
221{ 205 u32 word_1;
222 u32 word_1; 206 u32 word_2;
223 u32 word_2; 207 u32 word_3;
224 u32 word_3; 208 u32 word_4;
225 u32 word_4;
226} ns_scqe; 209} ns_scqe;
227 210
228 /* NOTE: SCQ entries can be either a TBD (Transmit Buffer Descriptors) 211 /* NOTE: SCQ entries can be either a TBD (Transmit Buffer Descriptors)
229 or TSR (Transmit Status Requests) */ 212 or TSR (Transmit Status Requests) */
230 213
231#define NS_SCQE_TYPE_TBD 0x00000000 214#define NS_SCQE_TYPE_TBD 0x00000000
232#define NS_SCQE_TYPE_TSR 0x80000000 215#define NS_SCQE_TYPE_TSR 0x80000000
233 216
234
235#define NS_TBD_EOPDU 0x40000000 217#define NS_TBD_EOPDU 0x40000000
236#define NS_TBD_AAL0 0x00000000 218#define NS_TBD_AAL0 0x00000000
237#define NS_TBD_AAL34 0x04000000 219#define NS_TBD_AAL34 0x04000000
@@ -253,10 +235,9 @@ typedef struct ns_scqe
253#define ns_tbd_mkword_4(gfc, vpi, vci, pt, clp) \ 235#define ns_tbd_mkword_4(gfc, vpi, vci, pt, clp) \
254 (cpu_to_le32((gfc) << 28 | (vpi) << 20 | (vci) << 4 | (pt) << 1 | (clp))) 236 (cpu_to_le32((gfc) << 28 | (vpi) << 20 | (vci) << 4 | (pt) << 1 | (clp)))
255 237
256
257#define NS_TSR_INTENABLE 0x20000000 238#define NS_TSR_INTENABLE 0x20000000
258 239
259#define NS_TSR_SCDISVBR 0xFFFF /* Use as scdi for VBR SCD */ 240#define NS_TSR_SCDISVBR 0xFFFF /* Use as scdi for VBR SCD */
260 241
261#define ns_tsr_mkword_1(flags) \ 242#define ns_tsr_mkword_1(flags) \
262 (cpu_to_le32(NS_SCQE_TYPE_TSR | (flags))) 243 (cpu_to_le32(NS_SCQE_TYPE_TSR | (flags)))
@@ -273,22 +254,20 @@ typedef struct ns_scqe
273 254
274#define NS_SCQE_SIZE 16 255#define NS_SCQE_SIZE 16
275 256
276 257/*
277 258 * TSQ - Transmit Status Queue
278/* TSQ - Transmit Status Queue
279 * 259 *
280 * Written by the NICStAR, read by the device driver. 260 * Written by the NICStAR, read by the device driver.
281 */ 261 */
282 262
283typedef struct ns_tsi 263typedef struct ns_tsi {
284{ 264 u32 word_1;
285 u32 word_1; 265 u32 word_2;
286 u32 word_2;
287} ns_tsi; 266} ns_tsi;
288 267
289 /* NOTE: The first word can be a status word copied from the TSR which 268 /* NOTE: The first word can be a status word copied from the TSR which
290 originated the TSI, or a timer overflow indicator. In this last 269 originated the TSI, or a timer overflow indicator. In this last
291 case, the value of the first word is all zeroes. */ 270 case, the value of the first word is all zeroes. */
292 271
293#define NS_TSI_EMPTY 0x80000000 272#define NS_TSI_EMPTY 0x80000000
294#define NS_TSI_TIMESTAMP_MASK 0x00FFFFFF 273#define NS_TSI_TIMESTAMP_MASK 0x00FFFFFF
@@ -301,12 +280,10 @@ typedef struct ns_tsi
301#define ns_tsi_init(ns_tsip) \ 280#define ns_tsi_init(ns_tsip) \
302 ((ns_tsip)->word_2 = cpu_to_le32(NS_TSI_EMPTY)) 281 ((ns_tsip)->word_2 = cpu_to_le32(NS_TSI_EMPTY))
303 282
304
305#define NS_TSQSIZE 8192 283#define NS_TSQSIZE 8192
306#define NS_TSQ_NUM_ENTRIES 1024 284#define NS_TSQ_NUM_ENTRIES 1024
307#define NS_TSQ_ALIGNMENT 8192 285#define NS_TSQ_ALIGNMENT 8192
308 286
309
310#define NS_TSI_SCDISVBR NS_TSR_SCDISVBR 287#define NS_TSI_SCDISVBR NS_TSR_SCDISVBR
311 288
312#define ns_tsi_tmrof(ns_tsip) \ 289#define ns_tsi_tmrof(ns_tsip) \
@@ -316,26 +293,22 @@ typedef struct ns_tsi
316#define ns_tsi_getscqpos(ns_tsip) \ 293#define ns_tsi_getscqpos(ns_tsip) \
317 (le32_to_cpu((ns_tsip)->word_1) & 0x00007FFF) 294 (le32_to_cpu((ns_tsip)->word_1) & 0x00007FFF)
318 295
296/* NICStAR structures located in local SRAM */
319 297
320 298/*
321/* NICStAR structures located in local SRAM ***********************************/ 299 * RCT - Receive Connection Table
322
323
324
325/* RCT - Receive Connection Table
326 * 300 *
327 * Written by both the NICStAR and the device driver. 301 * Written by both the NICStAR and the device driver.
328 */ 302 */
329 303
330typedef struct ns_rcte 304typedef struct ns_rcte {
331{ 305 u32 word_1;
332 u32 word_1; 306 u32 buffer_handle;
333 u32 buffer_handle; 307 u32 dma_address;
334 u32 dma_address; 308 u32 aal5_crc32;
335 u32 aal5_crc32;
336} ns_rcte; 309} ns_rcte;
337 310
338#define NS_RCTE_BSFB 0x00200000 /* Rev. D only */ 311#define NS_RCTE_BSFB 0x00200000 /* Rev. D only */
339#define NS_RCTE_NZGFC 0x00100000 312#define NS_RCTE_NZGFC 0x00100000
340#define NS_RCTE_CONNECTOPEN 0x00080000 313#define NS_RCTE_CONNECTOPEN 0x00080000
341#define NS_RCTE_AALMASK 0x00070000 314#define NS_RCTE_AALMASK 0x00070000
@@ -358,25 +331,21 @@ typedef struct ns_rcte
358#define NS_RCT_ENTRY_SIZE 4 /* Number of dwords */ 331#define NS_RCT_ENTRY_SIZE 4 /* Number of dwords */
359 332
360 /* NOTE: We could make macros to contruct the first word of the RCTE, 333 /* NOTE: We could make macros to contruct the first word of the RCTE,
361 but that doesn't seem to make much sense... */ 334 but that doesn't seem to make much sense... */
362
363
364 335
365/* FBD - Free Buffer Descriptor 336/*
337 * FBD - Free Buffer Descriptor
366 * 338 *
367 * Written by the device driver using via the command register. 339 * Written by the device driver using via the command register.
368 */ 340 */
369 341
370typedef struct ns_fbd 342typedef struct ns_fbd {
371{ 343 u32 buffer_handle;
372 u32 buffer_handle; 344 u32 dma_address;
373 u32 dma_address;
374} ns_fbd; 345} ns_fbd;
375 346
376 347/*
377 348 * TST - Transmit Schedule Table
378
379/* TST - Transmit Schedule Table
380 * 349 *
381 * Written by the device driver. 350 * Written by the device driver.
382 */ 351 */
@@ -385,40 +354,38 @@ typedef u32 ns_tste;
385 354
386#define NS_TST_OPCODE_MASK 0x60000000 355#define NS_TST_OPCODE_MASK 0x60000000
387 356
388#define NS_TST_OPCODE_NULL 0x00000000 /* Insert null cell */ 357#define NS_TST_OPCODE_NULL 0x00000000 /* Insert null cell */
389#define NS_TST_OPCODE_FIXED 0x20000000 /* Cell from a fixed rate channel */ 358#define NS_TST_OPCODE_FIXED 0x20000000 /* Cell from a fixed rate channel */
390#define NS_TST_OPCODE_VARIABLE 0x40000000 359#define NS_TST_OPCODE_VARIABLE 0x40000000
391#define NS_TST_OPCODE_END 0x60000000 /* Jump */ 360#define NS_TST_OPCODE_END 0x60000000 /* Jump */
392 361
393#define ns_tste_make(opcode, sramad) (opcode | sramad) 362#define ns_tste_make(opcode, sramad) (opcode | sramad)
394 363
395 /* NOTE: 364 /* NOTE:
396 365
397 - When the opcode is FIXED, sramad specifies the SRAM address of the 366 - When the opcode is FIXED, sramad specifies the SRAM address of the
398 SCD for that fixed rate channel. 367 SCD for that fixed rate channel.
399 - When the opcode is END, sramad specifies the SRAM address of the 368 - When the opcode is END, sramad specifies the SRAM address of the
400 location of the next TST entry to read. 369 location of the next TST entry to read.
401 */ 370 */
402 371
403 372/*
404 373 * SCD - Segmentation Channel Descriptor
405/* SCD - Segmentation Channel Descriptor
406 * 374 *
407 * Written by both the device driver and the NICStAR 375 * Written by both the device driver and the NICStAR
408 */ 376 */
409 377
410typedef struct ns_scd 378typedef struct ns_scd {
411{ 379 u32 word_1;
412 u32 word_1; 380 u32 word_2;
413 u32 word_2; 381 u32 partial_aal5_crc;
414 u32 partial_aal5_crc; 382 u32 reserved;
415 u32 reserved; 383 ns_scqe cache_a;
416 ns_scqe cache_a; 384 ns_scqe cache_b;
417 ns_scqe cache_b;
418} ns_scd; 385} ns_scd;
419 386
420#define NS_SCD_BASE_MASK_VAR 0xFFFFE000 /* Variable rate */ 387#define NS_SCD_BASE_MASK_VAR 0xFFFFE000 /* Variable rate */
421#define NS_SCD_BASE_MASK_FIX 0xFFFFFC00 /* Fixed rate */ 388#define NS_SCD_BASE_MASK_FIX 0xFFFFFC00 /* Fixed rate */
422#define NS_SCD_TAIL_MASK_VAR 0x00001FF0 389#define NS_SCD_TAIL_MASK_VAR 0x00001FF0
423#define NS_SCD_TAIL_MASK_FIX 0x000003F0 390#define NS_SCD_TAIL_MASK_FIX 0x000003F0
424#define NS_SCD_HEAD_MASK_VAR 0x00001FF0 391#define NS_SCD_HEAD_MASK_VAR 0x00001FF0
@@ -426,13 +393,9 @@ typedef struct ns_scd
426#define NS_SCD_XMITFOREVER 0x02000000 393#define NS_SCD_XMITFOREVER 0x02000000
427 394
428 /* NOTE: There are other fields in word 2 of the SCD, but as they should 395 /* NOTE: There are other fields in word 2 of the SCD, but as they should
429 not be needed in the device driver they are not defined here. */ 396 not be needed in the device driver they are not defined here. */
430
431
432
433
434/* NICStAR local SRAM memory map **********************************************/
435 397
398/* NICStAR local SRAM memory map */
436 399
437#define NS_RCT 0x00000 400#define NS_RCT 0x00000
438#define NS_RCT_32_END 0x03FFF 401#define NS_RCT_32_END 0x03FFF
@@ -455,100 +418,93 @@ typedef struct ns_scd
455#define NS_LGFBQ 0x1FC00 418#define NS_LGFBQ 0x1FC00
456#define NS_LGFBQ_END 0x1FFFF 419#define NS_LGFBQ_END 0x1FFFF
457 420
458 421/* NISCtAR operation registers */
459
460/* NISCtAR operation registers ************************************************/
461
462 422
463/* See Section 3.4 of `IDT77211 NICStAR User Manual' from www.idt.com */ 423/* See Section 3.4 of `IDT77211 NICStAR User Manual' from www.idt.com */
464 424
465enum ns_regs 425enum ns_regs {
466{ 426 DR0 = 0x00, /* Data Register 0 R/W */
467 DR0 = 0x00, /* Data Register 0 R/W*/ 427 DR1 = 0x04, /* Data Register 1 W */
468 DR1 = 0x04, /* Data Register 1 W */ 428 DR2 = 0x08, /* Data Register 2 W */
469 DR2 = 0x08, /* Data Register 2 W */ 429 DR3 = 0x0C, /* Data Register 3 W */
470 DR3 = 0x0C, /* Data Register 3 W */ 430 CMD = 0x10, /* Command W */
471 CMD = 0x10, /* Command W */ 431 CFG = 0x14, /* Configuration R/W */
472 CFG = 0x14, /* Configuration R/W */ 432 STAT = 0x18, /* Status R/W */
473 STAT = 0x18, /* Status R/W */ 433 RSQB = 0x1C, /* Receive Status Queue Base W */
474 RSQB = 0x1C, /* Receive Status Queue Base W */ 434 RSQT = 0x20, /* Receive Status Queue Tail R */
475 RSQT = 0x20, /* Receive Status Queue Tail R */ 435 RSQH = 0x24, /* Receive Status Queue Head W */
476 RSQH = 0x24, /* Receive Status Queue Head W */ 436 CDC = 0x28, /* Cell Drop Counter R/clear */
477 CDC = 0x28, /* Cell Drop Counter R/clear */ 437 VPEC = 0x2C, /* VPI/VCI Lookup Error Count R/clear */
478 VPEC = 0x2C, /* VPI/VCI Lookup Error Count R/clear */ 438 ICC = 0x30, /* Invalid Cell Count R/clear */
479 ICC = 0x30, /* Invalid Cell Count R/clear */ 439 RAWCT = 0x34, /* Raw Cell Tail R */
480 RAWCT = 0x34, /* Raw Cell Tail R */ 440 TMR = 0x38, /* Timer R */
481 TMR = 0x38, /* Timer R */ 441 TSTB = 0x3C, /* Transmit Schedule Table Base R/W */
482 TSTB = 0x3C, /* Transmit Schedule Table Base R/W */ 442 TSQB = 0x40, /* Transmit Status Queue Base W */
483 TSQB = 0x40, /* Transmit Status Queue Base W */ 443 TSQT = 0x44, /* Transmit Status Queue Tail R */
484 TSQT = 0x44, /* Transmit Status Queue Tail R */ 444 TSQH = 0x48, /* Transmit Status Queue Head W */
485 TSQH = 0x48, /* Transmit Status Queue Head W */ 445 GP = 0x4C, /* General Purpose R/W */
486 GP = 0x4C, /* General Purpose R/W */ 446 VPM = 0x50 /* VPI/VCI Mask W */
487 VPM = 0x50 /* VPI/VCI Mask W */
488}; 447};
489 448
490 449/* NICStAR commands issued to the CMD register */
491/* NICStAR commands issued to the CMD register ********************************/
492
493 450
494/* Top 4 bits are command opcode, lower 28 are parameters. */ 451/* Top 4 bits are command opcode, lower 28 are parameters. */
495 452
496#define NS_CMD_NO_OPERATION 0x00000000 453#define NS_CMD_NO_OPERATION 0x00000000
497 /* params always 0 */ 454 /* params always 0 */
498 455
499#define NS_CMD_OPENCLOSE_CONNECTION 0x20000000 456#define NS_CMD_OPENCLOSE_CONNECTION 0x20000000
500 /* b19{1=open,0=close} b18-2{SRAM addr} */ 457 /* b19{1=open,0=close} b18-2{SRAM addr} */
501 458
502#define NS_CMD_WRITE_SRAM 0x40000000 459#define NS_CMD_WRITE_SRAM 0x40000000
503 /* b18-2{SRAM addr} b1-0{burst size} */ 460 /* b18-2{SRAM addr} b1-0{burst size} */
504 461
505#define NS_CMD_READ_SRAM 0x50000000 462#define NS_CMD_READ_SRAM 0x50000000
506 /* b18-2{SRAM addr} */ 463 /* b18-2{SRAM addr} */
507 464
508#define NS_CMD_WRITE_FREEBUFQ 0x60000000 465#define NS_CMD_WRITE_FREEBUFQ 0x60000000
509 /* b0{large buf indicator} */ 466 /* b0{large buf indicator} */
510 467
511#define NS_CMD_READ_UTILITY 0x80000000 468#define NS_CMD_READ_UTILITY 0x80000000
512 /* b8{1=select UTL_CS1} b9{1=select UTL_CS0} b7-0{bus addr} */ 469 /* b8{1=select UTL_CS1} b9{1=select UTL_CS0} b7-0{bus addr} */
513 470
514#define NS_CMD_WRITE_UTILITY 0x90000000 471#define NS_CMD_WRITE_UTILITY 0x90000000
515 /* b8{1=select UTL_CS1} b9{1=select UTL_CS0} b7-0{bus addr} */ 472 /* b8{1=select UTL_CS1} b9{1=select UTL_CS0} b7-0{bus addr} */
516 473
517#define NS_CMD_OPEN_CONNECTION (NS_CMD_OPENCLOSE_CONNECTION | 0x00080000) 474#define NS_CMD_OPEN_CONNECTION (NS_CMD_OPENCLOSE_CONNECTION | 0x00080000)
518#define NS_CMD_CLOSE_CONNECTION NS_CMD_OPENCLOSE_CONNECTION 475#define NS_CMD_CLOSE_CONNECTION NS_CMD_OPENCLOSE_CONNECTION
519 476
520 477/* NICStAR configuration bits */
521/* NICStAR configuration bits *************************************************/ 478
522 479#define NS_CFG_SWRST 0x80000000 /* Software Reset */
523#define NS_CFG_SWRST 0x80000000 /* Software Reset */ 480#define NS_CFG_RXPATH 0x20000000 /* Receive Path Enable */
524#define NS_CFG_RXPATH 0x20000000 /* Receive Path Enable */ 481#define NS_CFG_SMBUFSIZE_MASK 0x18000000 /* Small Receive Buffer Size */
525#define NS_CFG_SMBUFSIZE_MASK 0x18000000 /* Small Receive Buffer Size */ 482#define NS_CFG_LGBUFSIZE_MASK 0x06000000 /* Large Receive Buffer Size */
526#define NS_CFG_LGBUFSIZE_MASK 0x06000000 /* Large Receive Buffer Size */ 483#define NS_CFG_EFBIE 0x01000000 /* Empty Free Buffer Queue
527#define NS_CFG_EFBIE 0x01000000 /* Empty Free Buffer Queue 484 Interrupt Enable */
528 Interrupt Enable */ 485#define NS_CFG_RSQSIZE_MASK 0x00C00000 /* Receive Status Queue Size */
529#define NS_CFG_RSQSIZE_MASK 0x00C00000 /* Receive Status Queue Size */ 486#define NS_CFG_ICACCEPT 0x00200000 /* Invalid Cell Accept */
530#define NS_CFG_ICACCEPT 0x00200000 /* Invalid Cell Accept */ 487#define NS_CFG_IGNOREGFC 0x00100000 /* Ignore General Flow Control */
531#define NS_CFG_IGNOREGFC 0x00100000 /* Ignore General Flow Control */ 488#define NS_CFG_VPIBITS_MASK 0x000C0000 /* VPI/VCI Bits Size Select */
532#define NS_CFG_VPIBITS_MASK 0x000C0000 /* VPI/VCI Bits Size Select */ 489#define NS_CFG_RCTSIZE_MASK 0x00030000 /* Receive Connection Table Size */
533#define NS_CFG_RCTSIZE_MASK 0x00030000 /* Receive Connection Table Size */ 490#define NS_CFG_VCERRACCEPT 0x00008000 /* VPI/VCI Error Cell Accept */
534#define NS_CFG_VCERRACCEPT 0x00008000 /* VPI/VCI Error Cell Accept */ 491#define NS_CFG_RXINT_MASK 0x00007000 /* End of Receive PDU Interrupt
535#define NS_CFG_RXINT_MASK 0x00007000 /* End of Receive PDU Interrupt 492 Handling */
536 Handling */ 493#define NS_CFG_RAWIE 0x00000800 /* Raw Cell Qu' Interrupt Enable */
537#define NS_CFG_RAWIE 0x00000800 /* Raw Cell Qu' Interrupt Enable */ 494#define NS_CFG_RSQAFIE 0x00000400 /* Receive Queue Almost Full
538#define NS_CFG_RSQAFIE 0x00000400 /* Receive Queue Almost Full 495 Interrupt Enable */
539 Interrupt Enable */ 496#define NS_CFG_RXRM 0x00000200 /* Receive RM Cells */
540#define NS_CFG_RXRM 0x00000200 /* Receive RM Cells */ 497#define NS_CFG_TMRROIE 0x00000080 /* Timer Roll Over Interrupt
541#define NS_CFG_TMRROIE 0x00000080 /* Timer Roll Over Interrupt 498 Enable */
542 Enable */ 499#define NS_CFG_TXEN 0x00000020 /* Transmit Operation Enable */
543#define NS_CFG_TXEN 0x00000020 /* Transmit Operation Enable */ 500#define NS_CFG_TXIE 0x00000010 /* Transmit Status Interrupt
544#define NS_CFG_TXIE 0x00000010 /* Transmit Status Interrupt 501 Enable */
545 Enable */ 502#define NS_CFG_TXURIE 0x00000008 /* Transmit Under-run Interrupt
546#define NS_CFG_TXURIE 0x00000008 /* Transmit Under-run Interrupt 503 Enable */
547 Enable */ 504#define NS_CFG_UMODE 0x00000004 /* Utopia Mode (cell/byte) Select */
548#define NS_CFG_UMODE 0x00000004 /* Utopia Mode (cell/byte) Select */ 505#define NS_CFG_TSQFIE 0x00000002 /* Transmit Status Queue Full
549#define NS_CFG_TSQFIE 0x00000002 /* Transmit Status Queue Full 506 Interrupt Enable */
550 Interrupt Enable */ 507#define NS_CFG_PHYIE 0x00000001 /* PHY Interrupt Enable */
551#define NS_CFG_PHYIE 0x00000001 /* PHY Interrupt Enable */
552 508
553#define NS_CFG_SMBUFSIZE_48 0x00000000 509#define NS_CFG_SMBUFSIZE_48 0x00000000
554#define NS_CFG_SMBUFSIZE_96 0x08000000 510#define NS_CFG_SMBUFSIZE_96 0x08000000
@@ -579,33 +535,29 @@ enum ns_regs
579#define NS_CFG_RXINT_624US 0x00003000 535#define NS_CFG_RXINT_624US 0x00003000
580#define NS_CFG_RXINT_899US 0x00004000 536#define NS_CFG_RXINT_899US 0x00004000
581 537
582 538/* NICStAR STATus bits */
583/* NICStAR STATus bits ********************************************************/ 539
584 540#define NS_STAT_SFBQC_MASK 0xFF000000 /* hi 8 bits Small Buffer Queue Count */
585#define NS_STAT_SFBQC_MASK 0xFF000000 /* hi 8 bits Small Buffer Queue Count */ 541#define NS_STAT_LFBQC_MASK 0x00FF0000 /* hi 8 bits Large Buffer Queue Count */
586#define NS_STAT_LFBQC_MASK 0x00FF0000 /* hi 8 bits Large Buffer Queue Count */ 542#define NS_STAT_TSIF 0x00008000 /* Transmit Status Queue Indicator */
587#define NS_STAT_TSIF 0x00008000 /* Transmit Status Queue Indicator */ 543#define NS_STAT_TXICP 0x00004000 /* Transmit Incomplete PDU */
588#define NS_STAT_TXICP 0x00004000 /* Transmit Incomplete PDU */ 544#define NS_STAT_TSQF 0x00001000 /* Transmit Status Queue Full */
589#define NS_STAT_TSQF 0x00001000 /* Transmit Status Queue Full */ 545#define NS_STAT_TMROF 0x00000800 /* Timer Overflow */
590#define NS_STAT_TMROF 0x00000800 /* Timer Overflow */ 546#define NS_STAT_PHYI 0x00000400 /* PHY Device Interrupt */
591#define NS_STAT_PHYI 0x00000400 /* PHY Device Interrupt */ 547#define NS_STAT_CMDBZ 0x00000200 /* Command Busy */
592#define NS_STAT_CMDBZ 0x00000200 /* Command Busy */ 548#define NS_STAT_SFBQF 0x00000100 /* Small Buffer Queue Full */
593#define NS_STAT_SFBQF 0x00000100 /* Small Buffer Queue Full */ 549#define NS_STAT_LFBQF 0x00000080 /* Large Buffer Queue Full */
594#define NS_STAT_LFBQF 0x00000080 /* Large Buffer Queue Full */ 550#define NS_STAT_RSQF 0x00000040 /* Receive Status Queue Full */
595#define NS_STAT_RSQF 0x00000040 /* Receive Status Queue Full */ 551#define NS_STAT_EOPDU 0x00000020 /* End of PDU */
596#define NS_STAT_EOPDU 0x00000020 /* End of PDU */ 552#define NS_STAT_RAWCF 0x00000010 /* Raw Cell Flag */
597#define NS_STAT_RAWCF 0x00000010 /* Raw Cell Flag */ 553#define NS_STAT_SFBQE 0x00000008 /* Small Buffer Queue Empty */
598#define NS_STAT_SFBQE 0x00000008 /* Small Buffer Queue Empty */ 554#define NS_STAT_LFBQE 0x00000004 /* Large Buffer Queue Empty */
599#define NS_STAT_LFBQE 0x00000004 /* Large Buffer Queue Empty */ 555#define NS_STAT_RSQAF 0x00000002 /* Receive Status Queue Almost Full */
600#define NS_STAT_RSQAF 0x00000002 /* Receive Status Queue Almost Full */
601 556
602#define ns_stat_sfbqc_get(stat) (((stat) & NS_STAT_SFBQC_MASK) >> 23) 557#define ns_stat_sfbqc_get(stat) (((stat) & NS_STAT_SFBQC_MASK) >> 23)
603#define ns_stat_lfbqc_get(stat) (((stat) & NS_STAT_LFBQC_MASK) >> 15) 558#define ns_stat_lfbqc_get(stat) (((stat) & NS_STAT_LFBQC_MASK) >> 15)
604 559
605 560/* #defines which depend on other #defines */
606
607/* #defines which depend on other #defines ************************************/
608
609 561
610#define NS_TST0 NS_TST_FRSCD 562#define NS_TST0 NS_TST_FRSCD
611#define NS_TST1 (NS_TST_FRSCD + NS_TST_NUM_ENTRIES + 1) 563#define NS_TST1 (NS_TST_FRSCD + NS_TST_NUM_ENTRIES + 1)
@@ -672,8 +624,7 @@ enum ns_regs
672#define NS_CFG_TSQFIE_OPT 0x00000000 624#define NS_CFG_TSQFIE_OPT 0x00000000
673#endif /* ENABLE_TSQFIE */ 625#endif /* ENABLE_TSQFIE */
674 626
675 627/* PCI stuff */
676/* PCI stuff ******************************************************************/
677 628
678#ifndef PCI_VENDOR_ID_IDT 629#ifndef PCI_VENDOR_ID_IDT
679#define PCI_VENDOR_ID_IDT 0x111D 630#define PCI_VENDOR_ID_IDT 0x111D
@@ -683,138 +634,119 @@ enum ns_regs
683#define PCI_DEVICE_ID_IDT_IDT77201 0x0001 634#define PCI_DEVICE_ID_IDT_IDT77201 0x0001
684#endif /* PCI_DEVICE_ID_IDT_IDT77201 */ 635#endif /* PCI_DEVICE_ID_IDT_IDT77201 */
685 636
686 637/* Device driver structures */
687
688/* Device driver structures ***************************************************/
689
690 638
691struct ns_skb_cb { 639struct ns_skb_cb {
692 u32 buf_type; /* BUF_SM/BUF_LG/BUF_NONE */ 640 u32 buf_type; /* BUF_SM/BUF_LG/BUF_NONE */
693}; 641};
694 642
695#define NS_SKB_CB(skb) ((struct ns_skb_cb *)((skb)->cb)) 643#define NS_SKB_CB(skb) ((struct ns_skb_cb *)((skb)->cb))
696 644
697typedef struct tsq_info 645typedef struct tsq_info {
698{ 646 void *org;
699 void *org; 647 ns_tsi *base;
700 ns_tsi *base; 648 ns_tsi *next;
701 ns_tsi *next; 649 ns_tsi *last;
702 ns_tsi *last;
703} tsq_info; 650} tsq_info;
704 651
705 652typedef struct scq_info {
706typedef struct scq_info 653 void *org;
707{ 654 ns_scqe *base;
708 void *org; 655 ns_scqe *last;
709 ns_scqe *base; 656 ns_scqe *next;
710 ns_scqe *last; 657 volatile ns_scqe *tail; /* Not related to the nicstar register */
711 ns_scqe *next; 658 unsigned num_entries;
712 volatile ns_scqe *tail; /* Not related to the nicstar register */ 659 struct sk_buff **skb; /* Pointer to an array of pointers
713 unsigned num_entries; 660 to the sk_buffs used for tx */
714 struct sk_buff **skb; /* Pointer to an array of pointers 661 u32 scd; /* SRAM address of the corresponding
715 to the sk_buffs used for tx */ 662 SCD */
716 u32 scd; /* SRAM address of the corresponding 663 int tbd_count; /* Only meaningful on variable rate */
717 SCD */ 664 wait_queue_head_t scqfull_waitq;
718 int tbd_count; /* Only meaningful on variable rate */ 665 volatile char full; /* SCQ full indicator */
719 wait_queue_head_t scqfull_waitq; 666 spinlock_t lock; /* SCQ spinlock */
720 volatile char full; /* SCQ full indicator */
721 spinlock_t lock; /* SCQ spinlock */
722} scq_info; 667} scq_info;
723 668
724 669typedef struct rsq_info {
725 670 void *org;
726typedef struct rsq_info 671 ns_rsqe *base;
727{ 672 ns_rsqe *next;
728 void *org; 673 ns_rsqe *last;
729 ns_rsqe *base;
730 ns_rsqe *next;
731 ns_rsqe *last;
732} rsq_info; 674} rsq_info;
733 675
734 676typedef struct skb_pool {
735typedef struct skb_pool 677 volatile int count; /* number of buffers in the queue */
736{ 678 struct sk_buff_head queue;
737 volatile int count; /* number of buffers in the queue */
738 struct sk_buff_head queue;
739} skb_pool; 679} skb_pool;
740 680
741/* NOTE: for small and large buffer pools, the count is not used, as the 681/* NOTE: for small and large buffer pools, the count is not used, as the
742 actual value used for buffer management is the one read from the 682 actual value used for buffer management is the one read from the
743 card. */ 683 card. */
744 684
745 685typedef struct vc_map {
746typedef struct vc_map 686 volatile unsigned int tx:1; /* TX vc? */
747{ 687 volatile unsigned int rx:1; /* RX vc? */
748 volatile unsigned int tx:1; /* TX vc? */ 688 struct atm_vcc *tx_vcc, *rx_vcc;
749 volatile unsigned int rx:1; /* RX vc? */ 689 struct sk_buff *rx_iov; /* RX iovector skb */
750 struct atm_vcc *tx_vcc, *rx_vcc; 690 scq_info *scq; /* To keep track of the SCQ */
751 struct sk_buff *rx_iov; /* RX iovector skb */ 691 u32 cbr_scd; /* SRAM address of the corresponding
752 scq_info *scq; /* To keep track of the SCQ */ 692 SCD. 0x00000000 for UBR/VBR/ABR */
753 u32 cbr_scd; /* SRAM address of the corresponding 693 int tbd_count;
754 SCD. 0x00000000 for UBR/VBR/ABR */
755 int tbd_count;
756} vc_map; 694} vc_map;
757 695
758 696struct ns_skb_data {
759struct ns_skb_data
760{
761 struct atm_vcc *vcc; 697 struct atm_vcc *vcc;
762 int iovcnt; 698 int iovcnt;
763}; 699};
764 700
765#define NS_SKB(skb) (((struct ns_skb_data *) (skb)->cb)) 701#define NS_SKB(skb) (((struct ns_skb_data *) (skb)->cb))
766 702
767 703typedef struct ns_dev {
768typedef struct ns_dev 704 int index; /* Card ID to the device driver */
769{ 705 int sram_size; /* In k x 32bit words. 32 or 128 */
770 int index; /* Card ID to the device driver */ 706 void __iomem *membase; /* Card's memory base address */
771 int sram_size; /* In k x 32bit words. 32 or 128 */ 707 unsigned long max_pcr;
772 void __iomem *membase; /* Card's memory base address */ 708 int rct_size; /* Number of entries */
773 unsigned long max_pcr; 709 int vpibits;
774 int rct_size; /* Number of entries */ 710 int vcibits;
775 int vpibits; 711 struct pci_dev *pcidev;
776 int vcibits; 712 struct atm_dev *atmdev;
777 struct pci_dev *pcidev; 713 tsq_info tsq;
778 struct atm_dev *atmdev; 714 rsq_info rsq;
779 tsq_info tsq; 715 scq_info *scq0, *scq1, *scq2; /* VBR SCQs */
780 rsq_info rsq; 716 skb_pool sbpool; /* Small buffers */
781 scq_info *scq0, *scq1, *scq2; /* VBR SCQs */ 717 skb_pool lbpool; /* Large buffers */
782 skb_pool sbpool; /* Small buffers */ 718 skb_pool hbpool; /* Pre-allocated huge buffers */
783 skb_pool lbpool; /* Large buffers */ 719 skb_pool iovpool; /* iovector buffers */
784 skb_pool hbpool; /* Pre-allocated huge buffers */ 720 volatile int efbie; /* Empty free buf. queue int. enabled */
785 skb_pool iovpool; /* iovector buffers */ 721 volatile u32 tst_addr; /* SRAM address of the TST in use */
786 volatile int efbie; /* Empty free buf. queue int. enabled */ 722 volatile int tst_free_entries;
787 volatile u32 tst_addr; /* SRAM address of the TST in use */ 723 vc_map vcmap[NS_MAX_RCTSIZE];
788 volatile int tst_free_entries; 724 vc_map *tste2vc[NS_TST_NUM_ENTRIES];
789 vc_map vcmap[NS_MAX_RCTSIZE]; 725 vc_map *scd2vc[NS_FRSCD_NUM];
790 vc_map *tste2vc[NS_TST_NUM_ENTRIES]; 726 buf_nr sbnr;
791 vc_map *scd2vc[NS_FRSCD_NUM]; 727 buf_nr lbnr;
792 buf_nr sbnr; 728 buf_nr hbnr;
793 buf_nr lbnr; 729 buf_nr iovnr;
794 buf_nr hbnr; 730 int sbfqc;
795 buf_nr iovnr; 731 int lbfqc;
796 int sbfqc; 732 u32 sm_handle;
797 int lbfqc; 733 u32 sm_addr;
798 u32 sm_handle; 734 u32 lg_handle;
799 u32 sm_addr; 735 u32 lg_addr;
800 u32 lg_handle; 736 struct sk_buff *rcbuf; /* Current raw cell buffer */
801 u32 lg_addr; 737 u32 rawch; /* Raw cell queue head */
802 struct sk_buff *rcbuf; /* Current raw cell buffer */ 738 unsigned intcnt; /* Interrupt counter */
803 u32 rawch; /* Raw cell queue head */ 739 spinlock_t int_lock; /* Interrupt lock */
804 unsigned intcnt; /* Interrupt counter */ 740 spinlock_t res_lock; /* Card resource lock */
805 spinlock_t int_lock; /* Interrupt lock */
806 spinlock_t res_lock; /* Card resource lock */
807} ns_dev; 741} ns_dev;
808 742
809
810 /* NOTE: Each tste2vc entry relates a given TST entry to the corresponding 743 /* NOTE: Each tste2vc entry relates a given TST entry to the corresponding
811 CBR vc. If the entry is not allocated, it must be NULL. 744 CBR vc. If the entry is not allocated, it must be NULL.
812 745
813 There are two TSTs so the driver can modify them on the fly 746 There are two TSTs so the driver can modify them on the fly
814 without stopping the transmission. 747 without stopping the transmission.
815
816 scd2vc allows us to find out unused fixed rate SCDs, because
817 they must have a NULL pointer here. */
818 748
749 scd2vc allows us to find out unused fixed rate SCDs, because
750 they must have a NULL pointer here. */
819 751
820#endif /* _LINUX_NICSTAR_H_ */ 752#endif /* _LINUX_NICSTAR_H_ */
diff --git a/drivers/atm/nicstarmac.c b/drivers/atm/nicstarmac.c
index 842e26c45557..f594526f8c6d 100644
--- a/drivers/atm/nicstarmac.c
+++ b/drivers/atm/nicstarmac.c
@@ -13,15 +13,15 @@ typedef void __iomem *virt_addr_t;
13 13
14#define CYCLE_DELAY 5 14#define CYCLE_DELAY 5
15 15
16/* This was the original definition 16/*
17 This was the original definition
17#define osp_MicroDelay(microsec) \ 18#define osp_MicroDelay(microsec) \
18 do { int _i = 4*microsec; while (--_i > 0) { __SLOW_DOWN_IO; }} while (0) 19 do { int _i = 4*microsec; while (--_i > 0) { __SLOW_DOWN_IO; }} while (0)
19*/ 20*/
20#define osp_MicroDelay(microsec) {unsigned long useconds = (microsec); \ 21#define osp_MicroDelay(microsec) {unsigned long useconds = (microsec); \
21 udelay((useconds));} 22 udelay((useconds));}
22 23/*
23 24 * The following tables represent the timing diagrams found in
24/* The following tables represent the timing diagrams found in
25 * the Data Sheet for the Xicor X25020 EEProm. The #defines below 25 * the Data Sheet for the Xicor X25020 EEProm. The #defines below
26 * represent the bits in the NICStAR's General Purpose register 26 * represent the bits in the NICStAR's General Purpose register
27 * that must be toggled for the corresponding actions on the EEProm 27 * that must be toggled for the corresponding actions on the EEProm
@@ -31,86 +31,80 @@ typedef void __iomem *virt_addr_t;
31/* Write Data To EEProm from SI line on rising edge of CLK */ 31/* Write Data To EEProm from SI line on rising edge of CLK */
32/* Read Data From EEProm on falling edge of CLK */ 32/* Read Data From EEProm on falling edge of CLK */
33 33
34#define CS_HIGH 0x0002 /* Chip select high */ 34#define CS_HIGH 0x0002 /* Chip select high */
35#define CS_LOW 0x0000 /* Chip select low (active low)*/ 35#define CS_LOW 0x0000 /* Chip select low (active low) */
36#define CLK_HIGH 0x0004 /* Clock high */ 36#define CLK_HIGH 0x0004 /* Clock high */
37#define CLK_LOW 0x0000 /* Clock low */ 37#define CLK_LOW 0x0000 /* Clock low */
38#define SI_HIGH 0x0001 /* Serial input data high */ 38#define SI_HIGH 0x0001 /* Serial input data high */
39#define SI_LOW 0x0000 /* Serial input data low */ 39#define SI_LOW 0x0000 /* Serial input data low */
40 40
41/* Read Status Register = 0000 0101b */ 41/* Read Status Register = 0000 0101b */
42#if 0 42#if 0
43static u_int32_t rdsrtab[] = 43static u_int32_t rdsrtab[] = {
44{ 44 CS_HIGH | CLK_HIGH,
45 CS_HIGH | CLK_HIGH, 45 CS_LOW | CLK_LOW,
46 CS_LOW | CLK_LOW, 46 CLK_HIGH, /* 0 */
47 CLK_HIGH, /* 0 */ 47 CLK_LOW,
48 CLK_LOW, 48 CLK_HIGH, /* 0 */
49 CLK_HIGH, /* 0 */ 49 CLK_LOW,
50 CLK_LOW, 50 CLK_HIGH, /* 0 */
51 CLK_HIGH, /* 0 */ 51 CLK_LOW,
52 CLK_LOW, 52 CLK_HIGH, /* 0 */
53 CLK_HIGH, /* 0 */ 53 CLK_LOW,
54 CLK_LOW, 54 CLK_HIGH, /* 0 */
55 CLK_HIGH, /* 0 */ 55 CLK_LOW | SI_HIGH,
56 CLK_LOW | SI_HIGH, 56 CLK_HIGH | SI_HIGH, /* 1 */
57 CLK_HIGH | SI_HIGH, /* 1 */ 57 CLK_LOW | SI_LOW,
58 CLK_LOW | SI_LOW, 58 CLK_HIGH, /* 0 */
59 CLK_HIGH, /* 0 */ 59 CLK_LOW | SI_HIGH,
60 CLK_LOW | SI_HIGH, 60 CLK_HIGH | SI_HIGH /* 1 */
61 CLK_HIGH | SI_HIGH /* 1 */
62}; 61};
63#endif /* 0 */ 62#endif /* 0 */
64
65 63
66/* Read from EEPROM = 0000 0011b */ 64/* Read from EEPROM = 0000 0011b */
67static u_int32_t readtab[] = 65static u_int32_t readtab[] = {
68{ 66 /*
69 /* 67 CS_HIGH | CLK_HIGH,
70 CS_HIGH | CLK_HIGH, 68 */
71 */ 69 CS_LOW | CLK_LOW,
72 CS_LOW | CLK_LOW, 70 CLK_HIGH, /* 0 */
73 CLK_HIGH, /* 0 */ 71 CLK_LOW,
74 CLK_LOW, 72 CLK_HIGH, /* 0 */
75 CLK_HIGH, /* 0 */ 73 CLK_LOW,
76 CLK_LOW, 74 CLK_HIGH, /* 0 */
77 CLK_HIGH, /* 0 */ 75 CLK_LOW,
78 CLK_LOW, 76 CLK_HIGH, /* 0 */
79 CLK_HIGH, /* 0 */ 77 CLK_LOW,
80 CLK_LOW, 78 CLK_HIGH, /* 0 */
81 CLK_HIGH, /* 0 */ 79 CLK_LOW,
82 CLK_LOW, 80 CLK_HIGH, /* 0 */
83 CLK_HIGH, /* 0 */ 81 CLK_LOW | SI_HIGH,
84 CLK_LOW | SI_HIGH, 82 CLK_HIGH | SI_HIGH, /* 1 */
85 CLK_HIGH | SI_HIGH, /* 1 */ 83 CLK_LOW | SI_HIGH,
86 CLK_LOW | SI_HIGH, 84 CLK_HIGH | SI_HIGH /* 1 */
87 CLK_HIGH | SI_HIGH /* 1 */
88}; 85};
89 86
90
91/* Clock to read from/write to the eeprom */ 87/* Clock to read from/write to the eeprom */
92static u_int32_t clocktab[] = 88static u_int32_t clocktab[] = {
93{ 89 CLK_LOW,
94 CLK_LOW, 90 CLK_HIGH,
95 CLK_HIGH, 91 CLK_LOW,
96 CLK_LOW, 92 CLK_HIGH,
97 CLK_HIGH, 93 CLK_LOW,
98 CLK_LOW, 94 CLK_HIGH,
99 CLK_HIGH, 95 CLK_LOW,
100 CLK_LOW, 96 CLK_HIGH,
101 CLK_HIGH, 97 CLK_LOW,
102 CLK_LOW, 98 CLK_HIGH,
103 CLK_HIGH, 99 CLK_LOW,
104 CLK_LOW, 100 CLK_HIGH,
105 CLK_HIGH, 101 CLK_LOW,
106 CLK_LOW, 102 CLK_HIGH,
107 CLK_HIGH, 103 CLK_LOW,
108 CLK_LOW, 104 CLK_HIGH,
109 CLK_HIGH, 105 CLK_LOW
110 CLK_LOW
111}; 106};
112 107
113
114#define NICSTAR_REG_WRITE(bs, reg, val) \ 108#define NICSTAR_REG_WRITE(bs, reg, val) \
115 while ( readl(bs + STAT) & 0x0200 ) ; \ 109 while ( readl(bs + STAT) & 0x0200 ) ; \
116 writel((val),(base)+(reg)) 110 writel((val),(base)+(reg))
@@ -124,153 +118,131 @@ static u_int32_t clocktab[] =
124 * register. 118 * register.
125 */ 119 */
126#if 0 120#if 0
127u_int32_t 121u_int32_t nicstar_read_eprom_status(virt_addr_t base)
128nicstar_read_eprom_status( virt_addr_t base )
129{ 122{
130 u_int32_t val; 123 u_int32_t val;
131 u_int32_t rbyte; 124 u_int32_t rbyte;
132 int32_t i, j; 125 int32_t i, j;
133 126
134 /* Send read instruction */ 127 /* Send read instruction */
135 val = NICSTAR_REG_READ( base, NICSTAR_REG_GENERAL_PURPOSE ) & 0xFFFFFFF0; 128 val = NICSTAR_REG_READ(base, NICSTAR_REG_GENERAL_PURPOSE) & 0xFFFFFFF0;
136 129
137 for (i=0; i<ARRAY_SIZE(rdsrtab); i++) 130 for (i = 0; i < ARRAY_SIZE(rdsrtab); i++) {
138 { 131 NICSTAR_REG_WRITE(base, NICSTAR_REG_GENERAL_PURPOSE,
139 NICSTAR_REG_WRITE( base, NICSTAR_REG_GENERAL_PURPOSE, 132 (val | rdsrtab[i]));
140 (val | rdsrtab[i]) ); 133 osp_MicroDelay(CYCLE_DELAY);
141 osp_MicroDelay( CYCLE_DELAY ); 134 }
142 } 135
143 136 /* Done sending instruction - now pull data off of bit 16, MSB first */
144 /* Done sending instruction - now pull data off of bit 16, MSB first */ 137 /* Data clocked out of eeprom on falling edge of clock */
145 /* Data clocked out of eeprom on falling edge of clock */ 138
146 139 rbyte = 0;
147 rbyte = 0; 140 for (i = 7, j = 0; i >= 0; i--) {
148 for (i=7, j=0; i>=0; i--) 141 NICSTAR_REG_WRITE(base, NICSTAR_REG_GENERAL_PURPOSE,
149 { 142 (val | clocktab[j++]));
150 NICSTAR_REG_WRITE( base, NICSTAR_REG_GENERAL_PURPOSE, 143 rbyte |= (((NICSTAR_REG_READ(base, NICSTAR_REG_GENERAL_PURPOSE)
151 (val | clocktab[j++]) ); 144 & 0x00010000) >> 16) << i);
152 rbyte |= (((NICSTAR_REG_READ( base, NICSTAR_REG_GENERAL_PURPOSE) 145 NICSTAR_REG_WRITE(base, NICSTAR_REG_GENERAL_PURPOSE,
153 & 0x00010000) >> 16) << i); 146 (val | clocktab[j++]));
154 NICSTAR_REG_WRITE( base, NICSTAR_REG_GENERAL_PURPOSE, 147 osp_MicroDelay(CYCLE_DELAY);
155 (val | clocktab[j++]) ); 148 }
156 osp_MicroDelay( CYCLE_DELAY ); 149 NICSTAR_REG_WRITE(base, NICSTAR_REG_GENERAL_PURPOSE, 2);
157 } 150 osp_MicroDelay(CYCLE_DELAY);
158 NICSTAR_REG_WRITE( base, NICSTAR_REG_GENERAL_PURPOSE, 2 ); 151 return rbyte;
159 osp_MicroDelay( CYCLE_DELAY );
160 return rbyte;
161} 152}
162#endif /* 0 */ 153#endif /* 0 */
163
164 154
165/* 155/*
166 * This routine will clock the Read_data function into the X2520 156 * This routine will clock the Read_data function into the X2520
167 * eeprom, followed by the address to read from, through the NicSTaR's General 157 * eeprom, followed by the address to read from, through the NicSTaR's General
168 * Purpose register. 158 * Purpose register.
169 */ 159 */
170 160
171static u_int8_t 161static u_int8_t read_eprom_byte(virt_addr_t base, u_int8_t offset)
172read_eprom_byte(virt_addr_t base, u_int8_t offset)
173{ 162{
174 u_int32_t val = 0; 163 u_int32_t val = 0;
175 int i,j=0; 164 int i, j = 0;
176 u_int8_t tempread = 0; 165 u_int8_t tempread = 0;
177 166
178 val = NICSTAR_REG_READ( base, NICSTAR_REG_GENERAL_PURPOSE ) & 0xFFFFFFF0; 167 val = NICSTAR_REG_READ(base, NICSTAR_REG_GENERAL_PURPOSE) & 0xFFFFFFF0;
179 168
180 /* Send READ instruction */ 169 /* Send READ instruction */
181 for (i=0; i<ARRAY_SIZE(readtab); i++) 170 for (i = 0; i < ARRAY_SIZE(readtab); i++) {
182 { 171 NICSTAR_REG_WRITE(base, NICSTAR_REG_GENERAL_PURPOSE,
183 NICSTAR_REG_WRITE( base, NICSTAR_REG_GENERAL_PURPOSE, 172 (val | readtab[i]));
184 (val | readtab[i]) ); 173 osp_MicroDelay(CYCLE_DELAY);
185 osp_MicroDelay( CYCLE_DELAY ); 174 }
186 } 175
187 176 /* Next, we need to send the byte address to read from */
188 /* Next, we need to send the byte address to read from */ 177 for (i = 7; i >= 0; i--) {
189 for (i=7; i>=0; i--) 178 NICSTAR_REG_WRITE(base, NICSTAR_REG_GENERAL_PURPOSE,
190 { 179 (val | clocktab[j++] | ((offset >> i) & 1)));
191 NICSTAR_REG_WRITE( base, NICSTAR_REG_GENERAL_PURPOSE, 180 osp_MicroDelay(CYCLE_DELAY);
192 (val | clocktab[j++] | ((offset >> i) & 1) ) ); 181 NICSTAR_REG_WRITE(base, NICSTAR_REG_GENERAL_PURPOSE,
193 osp_MicroDelay(CYCLE_DELAY); 182 (val | clocktab[j++] | ((offset >> i) & 1)));
194 NICSTAR_REG_WRITE( base, NICSTAR_REG_GENERAL_PURPOSE, 183 osp_MicroDelay(CYCLE_DELAY);
195 (val | clocktab[j++] | ((offset >> i) & 1) ) ); 184 }
196 osp_MicroDelay( CYCLE_DELAY ); 185
197 } 186 j = 0;
198 187
199 j = 0; 188 /* Now, we can read data from the eeprom by clocking it in */
200 189 for (i = 7; i >= 0; i--) {
201 /* Now, we can read data from the eeprom by clocking it in */ 190 NICSTAR_REG_WRITE(base, NICSTAR_REG_GENERAL_PURPOSE,
202 for (i=7; i>=0; i--) 191 (val | clocktab[j++]));
203 { 192 osp_MicroDelay(CYCLE_DELAY);
204 NICSTAR_REG_WRITE( base, NICSTAR_REG_GENERAL_PURPOSE, 193 tempread |=
205 (val | clocktab[j++]) ); 194 (((NICSTAR_REG_READ(base, NICSTAR_REG_GENERAL_PURPOSE)
206 osp_MicroDelay( CYCLE_DELAY ); 195 & 0x00010000) >> 16) << i);
207 tempread |= (((NICSTAR_REG_READ( base, NICSTAR_REG_GENERAL_PURPOSE ) 196 NICSTAR_REG_WRITE(base, NICSTAR_REG_GENERAL_PURPOSE,
208 & 0x00010000) >> 16) << i); 197 (val | clocktab[j++]));
209 NICSTAR_REG_WRITE( base, NICSTAR_REG_GENERAL_PURPOSE, 198 osp_MicroDelay(CYCLE_DELAY);
210 (val | clocktab[j++]) ); 199 }
211 osp_MicroDelay( CYCLE_DELAY ); 200
212 } 201 NICSTAR_REG_WRITE(base, NICSTAR_REG_GENERAL_PURPOSE, 2);
213 202 osp_MicroDelay(CYCLE_DELAY);
214 NICSTAR_REG_WRITE( base, NICSTAR_REG_GENERAL_PURPOSE, 2 ); 203 return tempread;
215 osp_MicroDelay( CYCLE_DELAY );
216 return tempread;
217} 204}
218 205
219 206static void nicstar_init_eprom(virt_addr_t base)
220static void
221nicstar_init_eprom( virt_addr_t base )
222{ 207{
223 u_int32_t val; 208 u_int32_t val;
224 209
225 /* 210 /*
226 * turn chip select off 211 * turn chip select off
227 */ 212 */
228 val = NICSTAR_REG_READ(base, NICSTAR_REG_GENERAL_PURPOSE) & 0xFFFFFFF0; 213 val = NICSTAR_REG_READ(base, NICSTAR_REG_GENERAL_PURPOSE) & 0xFFFFFFF0;
229 214
230 NICSTAR_REG_WRITE(base, NICSTAR_REG_GENERAL_PURPOSE, 215 NICSTAR_REG_WRITE(base, NICSTAR_REG_GENERAL_PURPOSE,
231 (val | CS_HIGH | CLK_HIGH)); 216 (val | CS_HIGH | CLK_HIGH));
232 osp_MicroDelay( CYCLE_DELAY ); 217 osp_MicroDelay(CYCLE_DELAY);
233 218
234 NICSTAR_REG_WRITE(base, NICSTAR_REG_GENERAL_PURPOSE, 219 NICSTAR_REG_WRITE(base, NICSTAR_REG_GENERAL_PURPOSE,
235 (val | CS_HIGH | CLK_LOW)); 220 (val | CS_HIGH | CLK_LOW));
236 osp_MicroDelay( CYCLE_DELAY ); 221 osp_MicroDelay(CYCLE_DELAY);
237 222
238 NICSTAR_REG_WRITE(base, NICSTAR_REG_GENERAL_PURPOSE, 223 NICSTAR_REG_WRITE(base, NICSTAR_REG_GENERAL_PURPOSE,
239 (val | CS_HIGH | CLK_HIGH)); 224 (val | CS_HIGH | CLK_HIGH));
240 osp_MicroDelay( CYCLE_DELAY ); 225 osp_MicroDelay(CYCLE_DELAY);
241 226
242 NICSTAR_REG_WRITE(base, NICSTAR_REG_GENERAL_PURPOSE, 227 NICSTAR_REG_WRITE(base, NICSTAR_REG_GENERAL_PURPOSE,
243 (val | CS_HIGH | CLK_LOW)); 228 (val | CS_HIGH | CLK_LOW));
244 osp_MicroDelay( CYCLE_DELAY ); 229 osp_MicroDelay(CYCLE_DELAY);
245} 230}
246 231
247
248/* 232/*
249 * This routine will be the interface to the ReadPromByte function 233 * This routine will be the interface to the ReadPromByte function
250 * above. 234 * above.
251 */ 235 */
252 236
253static void 237static void
254nicstar_read_eprom( 238nicstar_read_eprom(virt_addr_t base,
255 virt_addr_t base, 239 u_int8_t prom_offset, u_int8_t * buffer, u_int32_t nbytes)
256 u_int8_t prom_offset,
257 u_int8_t *buffer,
258 u_int32_t nbytes )
259{ 240{
260 u_int i; 241 u_int i;
261
262 for (i=0; i<nbytes; i++)
263 {
264 buffer[i] = read_eprom_byte( base, prom_offset );
265 ++prom_offset;
266 osp_MicroDelay( CYCLE_DELAY );
267 }
268}
269
270 242
271/* 243 for (i = 0; i < nbytes; i++) {
272void osp_MicroDelay(int x) { 244 buffer[i] = read_eprom_byte(base, prom_offset);
273 245 ++prom_offset;
246 osp_MicroDelay(CYCLE_DELAY);
247 }
274} 248}
275*/
276
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-10 01:53:39 -0500