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authorchas williams - CONTRACTOR <chas@cmf.nrl.navy.mil>2010-05-29 05:03:44 -0400
committerDavid S. Miller <davem@davemloft.net>2010-05-31 03:27:46 -0400
commit098fde114bf6655f4b75d71dbea208d039fc1de3 (patch)
treeea889dae935d8ca04508694929a0d17fde42ac1a /drivers/atm/nicstarmac.c
parent741a00be1f6bfa027225f44703ab72a741b757b7 (diff)
atm: [nicstar] reformatted with Lindent
Signed-off-by: Chas Williams - CONTRACTOR <chas@cmf.nrl.navy.mil> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/atm/nicstarmac.c')
-rw-r--r--drivers/atm/nicstarmac.c364
1 files changed, 168 insertions, 196 deletions
diff --git a/drivers/atm/nicstarmac.c b/drivers/atm/nicstarmac.c
index 842e26c45557..f594526f8c6d 100644
--- a/drivers/atm/nicstarmac.c
+++ b/drivers/atm/nicstarmac.c
@@ -13,15 +13,15 @@ typedef void __iomem *virt_addr_t;
13 13
14#define CYCLE_DELAY 5 14#define CYCLE_DELAY 5
15 15
16/* This was the original definition 16/*
17 This was the original definition
17#define osp_MicroDelay(microsec) \ 18#define osp_MicroDelay(microsec) \
18 do { int _i = 4*microsec; while (--_i > 0) { __SLOW_DOWN_IO; }} while (0) 19 do { int _i = 4*microsec; while (--_i > 0) { __SLOW_DOWN_IO; }} while (0)
19*/ 20*/
20#define osp_MicroDelay(microsec) {unsigned long useconds = (microsec); \ 21#define osp_MicroDelay(microsec) {unsigned long useconds = (microsec); \
21 udelay((useconds));} 22 udelay((useconds));}
22 23/*
23 24 * The following tables represent the timing diagrams found in
24/* The following tables represent the timing diagrams found in
25 * the Data Sheet for the Xicor X25020 EEProm. The #defines below 25 * the Data Sheet for the Xicor X25020 EEProm. The #defines below
26 * represent the bits in the NICStAR's General Purpose register 26 * represent the bits in the NICStAR's General Purpose register
27 * that must be toggled for the corresponding actions on the EEProm 27 * that must be toggled for the corresponding actions on the EEProm
@@ -31,86 +31,80 @@ typedef void __iomem *virt_addr_t;
31/* Write Data To EEProm from SI line on rising edge of CLK */ 31/* Write Data To EEProm from SI line on rising edge of CLK */
32/* Read Data From EEProm on falling edge of CLK */ 32/* Read Data From EEProm on falling edge of CLK */
33 33
34#define CS_HIGH 0x0002 /* Chip select high */ 34#define CS_HIGH 0x0002 /* Chip select high */
35#define CS_LOW 0x0000 /* Chip select low (active low)*/ 35#define CS_LOW 0x0000 /* Chip select low (active low) */
36#define CLK_HIGH 0x0004 /* Clock high */ 36#define CLK_HIGH 0x0004 /* Clock high */
37#define CLK_LOW 0x0000 /* Clock low */ 37#define CLK_LOW 0x0000 /* Clock low */
38#define SI_HIGH 0x0001 /* Serial input data high */ 38#define SI_HIGH 0x0001 /* Serial input data high */
39#define SI_LOW 0x0000 /* Serial input data low */ 39#define SI_LOW 0x0000 /* Serial input data low */
40 40
41/* Read Status Register = 0000 0101b */ 41/* Read Status Register = 0000 0101b */
42#if 0 42#if 0
43static u_int32_t rdsrtab[] = 43static u_int32_t rdsrtab[] = {
44{ 44 CS_HIGH | CLK_HIGH,
45 CS_HIGH | CLK_HIGH, 45 CS_LOW | CLK_LOW,
46 CS_LOW | CLK_LOW, 46 CLK_HIGH, /* 0 */
47 CLK_HIGH, /* 0 */ 47 CLK_LOW,
48 CLK_LOW, 48 CLK_HIGH, /* 0 */
49 CLK_HIGH, /* 0 */ 49 CLK_LOW,
50 CLK_LOW, 50 CLK_HIGH, /* 0 */
51 CLK_HIGH, /* 0 */ 51 CLK_LOW,
52 CLK_LOW, 52 CLK_HIGH, /* 0 */
53 CLK_HIGH, /* 0 */ 53 CLK_LOW,
54 CLK_LOW, 54 CLK_HIGH, /* 0 */
55 CLK_HIGH, /* 0 */ 55 CLK_LOW | SI_HIGH,
56 CLK_LOW | SI_HIGH, 56 CLK_HIGH | SI_HIGH, /* 1 */
57 CLK_HIGH | SI_HIGH, /* 1 */ 57 CLK_LOW | SI_LOW,
58 CLK_LOW | SI_LOW, 58 CLK_HIGH, /* 0 */
59 CLK_HIGH, /* 0 */ 59 CLK_LOW | SI_HIGH,
60 CLK_LOW | SI_HIGH, 60 CLK_HIGH | SI_HIGH /* 1 */
61 CLK_HIGH | SI_HIGH /* 1 */
62}; 61};
63#endif /* 0 */ 62#endif /* 0 */
64
65 63
66/* Read from EEPROM = 0000 0011b */ 64/* Read from EEPROM = 0000 0011b */
67static u_int32_t readtab[] = 65static u_int32_t readtab[] = {
68{ 66 /*
69 /* 67 CS_HIGH | CLK_HIGH,
70 CS_HIGH | CLK_HIGH, 68 */
71 */ 69 CS_LOW | CLK_LOW,
72 CS_LOW | CLK_LOW, 70 CLK_HIGH, /* 0 */
73 CLK_HIGH, /* 0 */ 71 CLK_LOW,
74 CLK_LOW, 72 CLK_HIGH, /* 0 */
75 CLK_HIGH, /* 0 */ 73 CLK_LOW,
76 CLK_LOW, 74 CLK_HIGH, /* 0 */
77 CLK_HIGH, /* 0 */ 75 CLK_LOW,
78 CLK_LOW, 76 CLK_HIGH, /* 0 */
79 CLK_HIGH, /* 0 */ 77 CLK_LOW,
80 CLK_LOW, 78 CLK_HIGH, /* 0 */
81 CLK_HIGH, /* 0 */ 79 CLK_LOW,
82 CLK_LOW, 80 CLK_HIGH, /* 0 */
83 CLK_HIGH, /* 0 */ 81 CLK_LOW | SI_HIGH,
84 CLK_LOW | SI_HIGH, 82 CLK_HIGH | SI_HIGH, /* 1 */
85 CLK_HIGH | SI_HIGH, /* 1 */ 83 CLK_LOW | SI_HIGH,
86 CLK_LOW | SI_HIGH, 84 CLK_HIGH | SI_HIGH /* 1 */
87 CLK_HIGH | SI_HIGH /* 1 */
88}; 85};
89 86
90
91/* Clock to read from/write to the eeprom */ 87/* Clock to read from/write to the eeprom */
92static u_int32_t clocktab[] = 88static u_int32_t clocktab[] = {
93{ 89 CLK_LOW,
94 CLK_LOW, 90 CLK_HIGH,
95 CLK_HIGH, 91 CLK_LOW,
96 CLK_LOW, 92 CLK_HIGH,
97 CLK_HIGH, 93 CLK_LOW,
98 CLK_LOW, 94 CLK_HIGH,
99 CLK_HIGH, 95 CLK_LOW,
100 CLK_LOW, 96 CLK_HIGH,
101 CLK_HIGH, 97 CLK_LOW,
102 CLK_LOW, 98 CLK_HIGH,
103 CLK_HIGH, 99 CLK_LOW,
104 CLK_LOW, 100 CLK_HIGH,
105 CLK_HIGH, 101 CLK_LOW,
106 CLK_LOW, 102 CLK_HIGH,
107 CLK_HIGH, 103 CLK_LOW,
108 CLK_LOW, 104 CLK_HIGH,
109 CLK_HIGH, 105 CLK_LOW
110 CLK_LOW
111}; 106};
112 107
113
114#define NICSTAR_REG_WRITE(bs, reg, val) \ 108#define NICSTAR_REG_WRITE(bs, reg, val) \
115 while ( readl(bs + STAT) & 0x0200 ) ; \ 109 while ( readl(bs + STAT) & 0x0200 ) ; \
116 writel((val),(base)+(reg)) 110 writel((val),(base)+(reg))
@@ -124,153 +118,131 @@ static u_int32_t clocktab[] =
124 * register. 118 * register.
125 */ 119 */
126#if 0 120#if 0
127u_int32_t 121u_int32_t nicstar_read_eprom_status(virt_addr_t base)
128nicstar_read_eprom_status( virt_addr_t base )
129{ 122{
130 u_int32_t val; 123 u_int32_t val;
131 u_int32_t rbyte; 124 u_int32_t rbyte;
132 int32_t i, j; 125 int32_t i, j;
133 126
134 /* Send read instruction */ 127 /* Send read instruction */
135 val = NICSTAR_REG_READ( base, NICSTAR_REG_GENERAL_PURPOSE ) & 0xFFFFFFF0; 128 val = NICSTAR_REG_READ(base, NICSTAR_REG_GENERAL_PURPOSE) & 0xFFFFFFF0;
136 129
137 for (i=0; i<ARRAY_SIZE(rdsrtab); i++) 130 for (i = 0; i < ARRAY_SIZE(rdsrtab); i++) {
138 { 131 NICSTAR_REG_WRITE(base, NICSTAR_REG_GENERAL_PURPOSE,
139 NICSTAR_REG_WRITE( base, NICSTAR_REG_GENERAL_PURPOSE, 132 (val | rdsrtab[i]));
140 (val | rdsrtab[i]) ); 133 osp_MicroDelay(CYCLE_DELAY);
141 osp_MicroDelay( CYCLE_DELAY ); 134 }
142 } 135
143 136 /* Done sending instruction - now pull data off of bit 16, MSB first */
144 /* Done sending instruction - now pull data off of bit 16, MSB first */ 137 /* Data clocked out of eeprom on falling edge of clock */
145 /* Data clocked out of eeprom on falling edge of clock */ 138
146 139 rbyte = 0;
147 rbyte = 0; 140 for (i = 7, j = 0; i >= 0; i--) {
148 for (i=7, j=0; i>=0; i--) 141 NICSTAR_REG_WRITE(base, NICSTAR_REG_GENERAL_PURPOSE,
149 { 142 (val | clocktab[j++]));
150 NICSTAR_REG_WRITE( base, NICSTAR_REG_GENERAL_PURPOSE, 143 rbyte |= (((NICSTAR_REG_READ(base, NICSTAR_REG_GENERAL_PURPOSE)
151 (val | clocktab[j++]) ); 144 & 0x00010000) >> 16) << i);
152 rbyte |= (((NICSTAR_REG_READ( base, NICSTAR_REG_GENERAL_PURPOSE) 145 NICSTAR_REG_WRITE(base, NICSTAR_REG_GENERAL_PURPOSE,
153 & 0x00010000) >> 16) << i); 146 (val | clocktab[j++]));
154 NICSTAR_REG_WRITE( base, NICSTAR_REG_GENERAL_PURPOSE, 147 osp_MicroDelay(CYCLE_DELAY);
155 (val | clocktab[j++]) ); 148 }
156 osp_MicroDelay( CYCLE_DELAY ); 149 NICSTAR_REG_WRITE(base, NICSTAR_REG_GENERAL_PURPOSE, 2);
157 } 150 osp_MicroDelay(CYCLE_DELAY);
158 NICSTAR_REG_WRITE( base, NICSTAR_REG_GENERAL_PURPOSE, 2 ); 151 return rbyte;
159 osp_MicroDelay( CYCLE_DELAY );
160 return rbyte;
161} 152}
162#endif /* 0 */ 153#endif /* 0 */
163
164 154
165/* 155/*
166 * This routine will clock the Read_data function into the X2520 156 * This routine will clock the Read_data function into the X2520
167 * eeprom, followed by the address to read from, through the NicSTaR's General 157 * eeprom, followed by the address to read from, through the NicSTaR's General
168 * Purpose register. 158 * Purpose register.
169 */ 159 */
170 160
171static u_int8_t 161static u_int8_t read_eprom_byte(virt_addr_t base, u_int8_t offset)
172read_eprom_byte(virt_addr_t base, u_int8_t offset)
173{ 162{
174 u_int32_t val = 0; 163 u_int32_t val = 0;
175 int i,j=0; 164 int i, j = 0;
176 u_int8_t tempread = 0; 165 u_int8_t tempread = 0;
177 166
178 val = NICSTAR_REG_READ( base, NICSTAR_REG_GENERAL_PURPOSE ) & 0xFFFFFFF0; 167 val = NICSTAR_REG_READ(base, NICSTAR_REG_GENERAL_PURPOSE) & 0xFFFFFFF0;
179 168
180 /* Send READ instruction */ 169 /* Send READ instruction */
181 for (i=0; i<ARRAY_SIZE(readtab); i++) 170 for (i = 0; i < ARRAY_SIZE(readtab); i++) {
182 { 171 NICSTAR_REG_WRITE(base, NICSTAR_REG_GENERAL_PURPOSE,
183 NICSTAR_REG_WRITE( base, NICSTAR_REG_GENERAL_PURPOSE, 172 (val | readtab[i]));
184 (val | readtab[i]) ); 173 osp_MicroDelay(CYCLE_DELAY);
185 osp_MicroDelay( CYCLE_DELAY ); 174 }
186 } 175
187 176 /* Next, we need to send the byte address to read from */
188 /* Next, we need to send the byte address to read from */ 177 for (i = 7; i >= 0; i--) {
189 for (i=7; i>=0; i--) 178 NICSTAR_REG_WRITE(base, NICSTAR_REG_GENERAL_PURPOSE,
190 { 179 (val | clocktab[j++] | ((offset >> i) & 1)));
191 NICSTAR_REG_WRITE( base, NICSTAR_REG_GENERAL_PURPOSE, 180 osp_MicroDelay(CYCLE_DELAY);
192 (val | clocktab[j++] | ((offset >> i) & 1) ) ); 181 NICSTAR_REG_WRITE(base, NICSTAR_REG_GENERAL_PURPOSE,
193 osp_MicroDelay(CYCLE_DELAY); 182 (val | clocktab[j++] | ((offset >> i) & 1)));
194 NICSTAR_REG_WRITE( base, NICSTAR_REG_GENERAL_PURPOSE, 183 osp_MicroDelay(CYCLE_DELAY);
195 (val | clocktab[j++] | ((offset >> i) & 1) ) ); 184 }
196 osp_MicroDelay( CYCLE_DELAY ); 185
197 } 186 j = 0;
198 187
199 j = 0; 188 /* Now, we can read data from the eeprom by clocking it in */
200 189 for (i = 7; i >= 0; i--) {
201 /* Now, we can read data from the eeprom by clocking it in */ 190 NICSTAR_REG_WRITE(base, NICSTAR_REG_GENERAL_PURPOSE,
202 for (i=7; i>=0; i--) 191 (val | clocktab[j++]));
203 { 192 osp_MicroDelay(CYCLE_DELAY);
204 NICSTAR_REG_WRITE( base, NICSTAR_REG_GENERAL_PURPOSE, 193 tempread |=
205 (val | clocktab[j++]) ); 194 (((NICSTAR_REG_READ(base, NICSTAR_REG_GENERAL_PURPOSE)
206 osp_MicroDelay( CYCLE_DELAY ); 195 & 0x00010000) >> 16) << i);
207 tempread |= (((NICSTAR_REG_READ( base, NICSTAR_REG_GENERAL_PURPOSE ) 196 NICSTAR_REG_WRITE(base, NICSTAR_REG_GENERAL_PURPOSE,
208 & 0x00010000) >> 16) << i); 197 (val | clocktab[j++]));
209 NICSTAR_REG_WRITE( base, NICSTAR_REG_GENERAL_PURPOSE, 198 osp_MicroDelay(CYCLE_DELAY);
210 (val | clocktab[j++]) ); 199 }
211 osp_MicroDelay( CYCLE_DELAY ); 200
212 } 201 NICSTAR_REG_WRITE(base, NICSTAR_REG_GENERAL_PURPOSE, 2);
213 202 osp_MicroDelay(CYCLE_DELAY);
214 NICSTAR_REG_WRITE( base, NICSTAR_REG_GENERAL_PURPOSE, 2 ); 203 return tempread;
215 osp_MicroDelay( CYCLE_DELAY );
216 return tempread;
217} 204}
218 205
219 206static void nicstar_init_eprom(virt_addr_t base)
220static void
221nicstar_init_eprom( virt_addr_t base )
222{ 207{
223 u_int32_t val; 208 u_int32_t val;
224 209
225 /* 210 /*
226 * turn chip select off 211 * turn chip select off
227 */ 212 */
228 val = NICSTAR_REG_READ(base, NICSTAR_REG_GENERAL_PURPOSE) & 0xFFFFFFF0; 213 val = NICSTAR_REG_READ(base, NICSTAR_REG_GENERAL_PURPOSE) & 0xFFFFFFF0;
229 214
230 NICSTAR_REG_WRITE(base, NICSTAR_REG_GENERAL_PURPOSE, 215 NICSTAR_REG_WRITE(base, NICSTAR_REG_GENERAL_PURPOSE,
231 (val | CS_HIGH | CLK_HIGH)); 216 (val | CS_HIGH | CLK_HIGH));
232 osp_MicroDelay( CYCLE_DELAY ); 217 osp_MicroDelay(CYCLE_DELAY);
233 218
234 NICSTAR_REG_WRITE(base, NICSTAR_REG_GENERAL_PURPOSE, 219 NICSTAR_REG_WRITE(base, NICSTAR_REG_GENERAL_PURPOSE,
235 (val | CS_HIGH | CLK_LOW)); 220 (val | CS_HIGH | CLK_LOW));
236 osp_MicroDelay( CYCLE_DELAY ); 221 osp_MicroDelay(CYCLE_DELAY);
237 222
238 NICSTAR_REG_WRITE(base, NICSTAR_REG_GENERAL_PURPOSE, 223 NICSTAR_REG_WRITE(base, NICSTAR_REG_GENERAL_PURPOSE,
239 (val | CS_HIGH | CLK_HIGH)); 224 (val | CS_HIGH | CLK_HIGH));
240 osp_MicroDelay( CYCLE_DELAY ); 225 osp_MicroDelay(CYCLE_DELAY);
241 226
242 NICSTAR_REG_WRITE(base, NICSTAR_REG_GENERAL_PURPOSE, 227 NICSTAR_REG_WRITE(base, NICSTAR_REG_GENERAL_PURPOSE,
243 (val | CS_HIGH | CLK_LOW)); 228 (val | CS_HIGH | CLK_LOW));
244 osp_MicroDelay( CYCLE_DELAY ); 229 osp_MicroDelay(CYCLE_DELAY);
245} 230}
246 231
247
248/* 232/*
249 * This routine will be the interface to the ReadPromByte function 233 * This routine will be the interface to the ReadPromByte function
250 * above. 234 * above.
251 */ 235 */
252 236
253static void 237static void
254nicstar_read_eprom( 238nicstar_read_eprom(virt_addr_t base,
255 virt_addr_t base, 239 u_int8_t prom_offset, u_int8_t * buffer, u_int32_t nbytes)
256 u_int8_t prom_offset,
257 u_int8_t *buffer,
258 u_int32_t nbytes )
259{ 240{
260 u_int i; 241 u_int i;
261
262 for (i=0; i<nbytes; i++)
263 {
264 buffer[i] = read_eprom_byte( base, prom_offset );
265 ++prom_offset;
266 osp_MicroDelay( CYCLE_DELAY );
267 }
268}
269
270 242
271/* 243 for (i = 0; i < nbytes; i++) {
272void osp_MicroDelay(int x) { 244 buffer[i] = read_eprom_byte(base, prom_offset);
273 245 ++prom_offset;
246 osp_MicroDelay(CYCLE_DELAY);
247 }
274} 248}
275*/
276
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