diff options
author | françois romieu <romieu@fr.zoreil.com> | 2011-09-29 20:37:43 -0400 |
---|---|---|
committer | David S. Miller <davem@davemloft.net> | 2011-10-03 14:09:10 -0400 |
commit | 26c5c44d63824f7c397d27b10c2c43a3bab4a2f0 (patch) | |
tree | 30035842663845637d481a7008f137442a3ad411 /drivers/atm/iphase.c | |
parent | 7880b72e94fd3cf3283de6752175191583bce9f0 (diff) |
atm/iphase : removal of PCI space dereferences.
Mostly PHY access and a few (ugly) debug statements for DMA control.
Signed-off-by: Francois Romieu <romieu@fr.zoreil.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/atm/iphase.c')
-rw-r--r-- | drivers/atm/iphase.c | 265 |
1 files changed, 145 insertions, 120 deletions
diff --git a/drivers/atm/iphase.c b/drivers/atm/iphase.c index cb90f7a3e074..3d0c2b0fed9c 100644 --- a/drivers/atm/iphase.c +++ b/drivers/atm/iphase.c | |||
@@ -818,127 +818,152 @@ static void ia_hw_type(IADEV *iadev) { | |||
818 | 818 | ||
819 | } | 819 | } |
820 | 820 | ||
821 | static void IaFrontEndIntr(IADEV *iadev) { | 821 | static u32 ia_phy_read32(struct iadev_priv *ia, unsigned int reg) |
822 | volatile IA_SUNI *suni; | 822 | { |
823 | volatile ia_mb25_t *mb25; | 823 | return readl(ia->phy + (reg >> 2)); |
824 | volatile suni_pm7345_t *suni_pm7345; | 824 | } |
825 | 825 | ||
826 | if(iadev->phy_type & FE_25MBIT_PHY) { | 826 | static void ia_phy_write32(struct iadev_priv *ia, unsigned int reg, u32 val) |
827 | mb25 = (ia_mb25_t*)iadev->phy; | 827 | { |
828 | iadev->carrier_detect = Boolean(mb25->mb25_intr_status & MB25_IS_GSB); | 828 | writel(val, ia->phy + (reg >> 2)); |
829 | } else if (iadev->phy_type & FE_DS3_PHY) { | 829 | } |
830 | suni_pm7345 = (suni_pm7345_t *)iadev->phy; | 830 | |
831 | /* clear FRMR interrupts */ | 831 | static void ia_frontend_intr(struct iadev_priv *iadev) |
832 | (void) suni_pm7345->suni_ds3_frm_intr_stat; | 832 | { |
833 | iadev->carrier_detect = | 833 | u32 status; |
834 | Boolean(!(suni_pm7345->suni_ds3_frm_stat & SUNI_DS3_LOSV)); | 834 | |
835 | } else if (iadev->phy_type & FE_E3_PHY ) { | 835 | if (iadev->phy_type & FE_25MBIT_PHY) { |
836 | suni_pm7345 = (suni_pm7345_t *)iadev->phy; | 836 | status = ia_phy_read32(iadev, MB25_INTR_STATUS); |
837 | (void) suni_pm7345->suni_e3_frm_maint_intr_ind; | 837 | iadev->carrier_detect = (status & MB25_IS_GSB) ? 1 : 0; |
838 | iadev->carrier_detect = | 838 | } else if (iadev->phy_type & FE_DS3_PHY) { |
839 | Boolean(!(suni_pm7345->suni_e3_frm_fram_intr_ind_stat&SUNI_E3_LOS)); | 839 | ia_phy_read32(iadev, SUNI_DS3_FRM_INTR_STAT); |
840 | } | 840 | status = ia_phy_read32(iadev, SUNI_DS3_FRM_STAT); |
841 | else { | 841 | iadev->carrier_detect = (status & SUNI_DS3_LOSV) ? 0 : 1; |
842 | suni = (IA_SUNI *)iadev->phy; | 842 | } else if (iadev->phy_type & FE_E3_PHY) { |
843 | (void) suni->suni_rsop_status; | 843 | ia_phy_read32(iadev, SUNI_E3_FRM_MAINT_INTR_IND); |
844 | iadev->carrier_detect = Boolean(!(suni->suni_rsop_status & SUNI_LOSV)); | 844 | status = ia_phy_read32(iadev, SUNI_E3_FRM_FRAM_INTR_IND_STAT); |
845 | } | 845 | iadev->carrier_detect = (status & SUNI_E3_LOS) ? 0 : 1; |
846 | if (iadev->carrier_detect) | 846 | } else { |
847 | printk("IA: SUNI carrier detected\n"); | 847 | status = ia_phy_read32(iadev, SUNI_RSOP_STATUS); |
848 | else | 848 | iadev->carrier_detect = (status & SUNI_LOSV) ? 0 : 1; |
849 | printk("IA: SUNI carrier lost signal\n"); | 849 | } |
850 | return; | 850 | |
851 | printk(KERN_INFO "IA: SUNI carrier %s\n", | ||
852 | iadev->carrier_detect ? "detected" : "lost signal"); | ||
851 | } | 853 | } |
852 | 854 | ||
853 | static void ia_mb25_init (IADEV *iadev) | 855 | static void ia_mb25_init(struct iadev_priv *iadev) |
854 | { | 856 | { |
855 | volatile ia_mb25_t *mb25 = (ia_mb25_t*)iadev->phy; | ||
856 | #if 0 | 857 | #if 0 |
857 | mb25->mb25_master_ctrl = MB25_MC_DRIC | MB25_MC_DREC | MB25_MC_ENABLED; | 858 | mb25->mb25_master_ctrl = MB25_MC_DRIC | MB25_MC_DREC | MB25_MC_ENABLED; |
858 | #endif | 859 | #endif |
859 | mb25->mb25_master_ctrl = MB25_MC_DRIC | MB25_MC_DREC; | 860 | ia_phy_write32(iadev, MB25_MASTER_CTRL, MB25_MC_DRIC | MB25_MC_DREC); |
860 | mb25->mb25_diag_control = 0; | 861 | ia_phy_write32(iadev, MB25_DIAG_CONTROL, 0); |
861 | /* | 862 | |
862 | * Initialize carrier detect state | 863 | iadev->carrier_detect = |
863 | */ | 864 | (ia_phy_read32(iadev, MB25_INTR_STATUS) & MB25_IS_GSB) ? 1 : 0; |
864 | iadev->carrier_detect = Boolean(mb25->mb25_intr_status & MB25_IS_GSB); | 865 | } |
865 | return; | ||
866 | } | ||
867 | 866 | ||
868 | static void ia_suni_pm7345_init (IADEV *iadev) | 867 | struct ia_reg { |
868 | u16 reg; | ||
869 | u16 val; | ||
870 | }; | ||
871 | |||
872 | static void ia_phy_write(struct iadev_priv *iadev, | ||
873 | const struct ia_reg *regs, int len) | ||
869 | { | 874 | { |
870 | volatile suni_pm7345_t *suni_pm7345 = (suni_pm7345_t *)iadev->phy; | 875 | while (len--) { |
871 | if (iadev->phy_type & FE_DS3_PHY) | 876 | ia_phy_write32(iadev, regs->reg, regs->val); |
872 | { | 877 | regs++; |
873 | iadev->carrier_detect = | 878 | } |
874 | Boolean(!(suni_pm7345->suni_ds3_frm_stat & SUNI_DS3_LOSV)); | 879 | } |
875 | suni_pm7345->suni_ds3_frm_intr_enbl = 0x17; | 880 | |
876 | suni_pm7345->suni_ds3_frm_cfg = 1; | 881 | static void ia_suni_pm7345_init_ds3(struct iadev_priv *iadev) |
877 | suni_pm7345->suni_ds3_tran_cfg = 1; | 882 | { |
878 | suni_pm7345->suni_config = 0; | 883 | static const struct ia_reg suni_ds3_init [] = { |
879 | suni_pm7345->suni_splr_cfg = 0; | 884 | { SUNI_DS3_FRM_INTR_ENBL, 0x17 }, |
880 | suni_pm7345->suni_splt_cfg = 0; | 885 | { SUNI_DS3_FRM_CFG, 0x01 }, |
881 | } | 886 | { SUNI_DS3_TRAN_CFG, 0x01 }, |
882 | else | 887 | { SUNI_CONFIG, 0 }, |
883 | { | 888 | { SUNI_SPLR_CFG, 0 }, |
884 | iadev->carrier_detect = | 889 | { SUNI_SPLT_CFG, 0 } |
885 | Boolean(!(suni_pm7345->suni_e3_frm_fram_intr_ind_stat & SUNI_E3_LOS)); | 890 | }; |
886 | suni_pm7345->suni_e3_frm_fram_options = 0x4; | 891 | u32 status; |
887 | suni_pm7345->suni_e3_frm_maint_options = 0x20; | 892 | |
888 | suni_pm7345->suni_e3_frm_fram_intr_enbl = 0x1d; | 893 | status = ia_phy_read32(iadev, SUNI_DS3_FRM_STAT); |
889 | suni_pm7345->suni_e3_frm_maint_intr_enbl = 0x30; | 894 | iadev->carrier_detect = (status & SUNI_DS3_LOSV) ? 0 : 1; |
890 | suni_pm7345->suni_e3_tran_stat_diag_options = 0x0; | 895 | |
891 | suni_pm7345->suni_e3_tran_fram_options = 0x1; | 896 | ia_phy_write(iadev, suni_ds3_init, ARRAY_SIZE(suni_ds3_init)); |
892 | suni_pm7345->suni_config = SUNI_PM7345_E3ENBL; | 897 | } |
893 | suni_pm7345->suni_splr_cfg = 0x41; | 898 | |
894 | suni_pm7345->suni_splt_cfg = 0x41; | 899 | static void ia_suni_pm7345_init_e3(struct iadev_priv *iadev) |
895 | } | 900 | { |
896 | /* | 901 | static const struct ia_reg suni_e3_init [] = { |
897 | * Enable RSOP loss of signal interrupt. | 902 | { SUNI_E3_FRM_FRAM_OPTIONS, 0x04 }, |
898 | */ | 903 | { SUNI_E3_FRM_MAINT_OPTIONS, 0x20 }, |
899 | suni_pm7345->suni_intr_enbl = 0x28; | 904 | { SUNI_E3_FRM_FRAM_INTR_ENBL, 0x1d }, |
900 | 905 | { SUNI_E3_FRM_MAINT_INTR_ENBL, 0x30 }, | |
901 | /* | 906 | { SUNI_E3_TRAN_STAT_DIAG_OPTIONS, 0 }, |
902 | * Clear error counters | 907 | { SUNI_E3_TRAN_FRAM_OPTIONS, 0x01 }, |
903 | */ | 908 | { SUNI_CONFIG, SUNI_PM7345_E3ENBL }, |
904 | suni_pm7345->suni_id_reset = 0; | 909 | { SUNI_SPLR_CFG, 0x41 }, |
905 | 910 | { SUNI_SPLT_CFG, 0x41 } | |
906 | /* | 911 | }; |
907 | * Clear "PMCTST" in master test register. | 912 | u32 status; |
908 | */ | 913 | |
909 | suni_pm7345->suni_master_test = 0; | 914 | status = ia_phy_read32(iadev, SUNI_E3_FRM_FRAM_INTR_IND_STAT); |
910 | 915 | iadev->carrier_detect = (status & SUNI_E3_LOS) ? 0 : 1; | |
911 | suni_pm7345->suni_rxcp_ctrl = 0x2c; | 916 | ia_phy_write(iadev, suni_e3_init, ARRAY_SIZE(suni_e3_init)); |
912 | suni_pm7345->suni_rxcp_fctrl = 0x81; | 917 | } |
913 | 918 | ||
914 | suni_pm7345->suni_rxcp_idle_pat_h1 = | 919 | static void ia_suni_pm7345_init(struct iadev_priv *iadev) |
915 | suni_pm7345->suni_rxcp_idle_pat_h2 = | 920 | { |
916 | suni_pm7345->suni_rxcp_idle_pat_h3 = 0; | 921 | static const struct ia_reg suni_init [] = { |
917 | suni_pm7345->suni_rxcp_idle_pat_h4 = 1; | 922 | /* Enable RSOP loss of signal interrupt. */ |
918 | 923 | { SUNI_INTR_ENBL, 0x28 }, | |
919 | suni_pm7345->suni_rxcp_idle_mask_h1 = 0xff; | 924 | /* Clear error counters. */ |
920 | suni_pm7345->suni_rxcp_idle_mask_h2 = 0xff; | 925 | { SUNI_ID_RESET, 0 }, |
921 | suni_pm7345->suni_rxcp_idle_mask_h3 = 0xff; | 926 | /* Clear "PMCTST" in master test register. */ |
922 | suni_pm7345->suni_rxcp_idle_mask_h4 = 0xfe; | 927 | { SUNI_MASTER_TEST, 0 }, |
923 | 928 | ||
924 | suni_pm7345->suni_rxcp_cell_pat_h1 = | 929 | { SUNI_RXCP_CTRL, 0x2c }, |
925 | suni_pm7345->suni_rxcp_cell_pat_h2 = | 930 | { SUNI_RXCP_FCTRL, 0x81 }, |
926 | suni_pm7345->suni_rxcp_cell_pat_h3 = 0; | 931 | |
927 | suni_pm7345->suni_rxcp_cell_pat_h4 = 1; | 932 | { SUNI_RXCP_IDLE_PAT_H1, 0 }, |
928 | 933 | { SUNI_RXCP_IDLE_PAT_H2, 0 }, | |
929 | suni_pm7345->suni_rxcp_cell_mask_h1 = | 934 | { SUNI_RXCP_IDLE_PAT_H3, 0 }, |
930 | suni_pm7345->suni_rxcp_cell_mask_h2 = | 935 | { SUNI_RXCP_IDLE_PAT_H4, 0x01 }, |
931 | suni_pm7345->suni_rxcp_cell_mask_h3 = | 936 | |
932 | suni_pm7345->suni_rxcp_cell_mask_h4 = 0xff; | 937 | { SUNI_RXCP_IDLE_MASK_H1, 0xff }, |
933 | 938 | { SUNI_RXCP_IDLE_MASK_H2, 0xff }, | |
934 | suni_pm7345->suni_txcp_ctrl = 0xa4; | 939 | { SUNI_RXCP_IDLE_MASK_H3, 0xff }, |
935 | suni_pm7345->suni_txcp_intr_en_sts = 0x10; | 940 | { SUNI_RXCP_IDLE_MASK_H4, 0xfe }, |
936 | suni_pm7345->suni_txcp_idle_pat_h5 = 0x55; | 941 | |
937 | 942 | { SUNI_RXCP_CELL_PAT_H1, 0 }, | |
938 | suni_pm7345->suni_config &= ~(SUNI_PM7345_LLB | | 943 | { SUNI_RXCP_CELL_PAT_H2, 0 }, |
939 | SUNI_PM7345_CLB | | 944 | { SUNI_RXCP_CELL_PAT_H3, 0 }, |
940 | SUNI_PM7345_DLB | | 945 | { SUNI_RXCP_CELL_PAT_H4, 0x01 }, |
941 | SUNI_PM7345_PLB); | 946 | |
947 | { SUNI_RXCP_CELL_MASK_H1, 0xff }, | ||
948 | { SUNI_RXCP_CELL_MASK_H2, 0xff }, | ||
949 | { SUNI_RXCP_CELL_MASK_H3, 0xff }, | ||
950 | { SUNI_RXCP_CELL_MASK_H4, 0xff }, | ||
951 | |||
952 | { SUNI_TXCP_CTRL, 0xa4 }, | ||
953 | { SUNI_TXCP_INTR_EN_STS, 0x10 }, | ||
954 | { SUNI_TXCP_IDLE_PAT_H5, 0x55 } | ||
955 | }; | ||
956 | |||
957 | if (iadev->phy_type & FE_DS3_PHY) | ||
958 | ia_suni_pm7345_init_ds3(iadev); | ||
959 | else | ||
960 | ia_suni_pm7345_init_e3(iadev); | ||
961 | |||
962 | ia_phy_write(iadev, suni_init, ARRAY_SIZE(suni_init)); | ||
963 | |||
964 | ia_phy_write32(iadev, SUNI_CONFIG, ia_phy_read32(iadev, SUNI_CONFIG) & | ||
965 | ~(SUNI_PM7345_LLB | SUNI_PM7345_CLB | | ||
966 | SUNI_PM7345_DLB | SUNI_PM7345_PLB)); | ||
942 | #ifdef __SNMP__ | 967 | #ifdef __SNMP__ |
943 | suni_pm7345->suni_rxcp_intr_en_sts |= SUNI_OOCDE; | 968 | suni_pm7345->suni_rxcp_intr_en_sts |= SUNI_OOCDE; |
944 | #endif /* __SNMP__ */ | 969 | #endif /* __SNMP__ */ |
@@ -1425,10 +1450,10 @@ static int rx_init(struct atm_dev *dev) | |||
1425 | iadev->dma + IPHASE5575_RX_LIST_ADDR); | 1450 | iadev->dma + IPHASE5575_RX_LIST_ADDR); |
1426 | IF_INIT(printk("Tx Dle list addr: 0x%p value: 0x%0x\n", | 1451 | IF_INIT(printk("Tx Dle list addr: 0x%p value: 0x%0x\n", |
1427 | iadev->dma+IPHASE5575_TX_LIST_ADDR, | 1452 | iadev->dma+IPHASE5575_TX_LIST_ADDR, |
1428 | *(u32*)(iadev->dma+IPHASE5575_TX_LIST_ADDR)); | 1453 | readl(iadev->dma + IPHASE5575_TX_LIST_ADDR)); |
1429 | printk("Rx Dle list addr: 0x%p value: 0x%0x\n", | 1454 | printk("Rx Dle list addr: 0x%p value: 0x%0x\n", |
1430 | iadev->dma+IPHASE5575_RX_LIST_ADDR, | 1455 | iadev->dma+IPHASE5575_RX_LIST_ADDR, |
1431 | *(u32*)(iadev->dma+IPHASE5575_RX_LIST_ADDR));) | 1456 | readl(iadev->dma + IPHASE5575_RX_LIST_ADDR));) |
1432 | 1457 | ||
1433 | writew(0xffff, iadev->reass_reg+REASS_MASK_REG); | 1458 | writew(0xffff, iadev->reass_reg+REASS_MASK_REG); |
1434 | writew(0, iadev->reass_reg+MODE_REG); | 1459 | writew(0, iadev->reass_reg+MODE_REG); |
@@ -2208,7 +2233,7 @@ static irqreturn_t ia_int(int irq, void *dev_id) | |||
2208 | if (status & STAT_DLERINT) | 2233 | if (status & STAT_DLERINT) |
2209 | { | 2234 | { |
2210 | /* Clear this bit by writing a 1 to it. */ | 2235 | /* Clear this bit by writing a 1 to it. */ |
2211 | *(u_int *)(iadev->reg+IPHASE5575_BUS_STATUS_REG) = STAT_DLERINT; | 2236 | writel(STAT_DLERINT, iadev->reg + IPHASE5575_BUS_STATUS_REG); |
2212 | rx_dle_intr(dev); | 2237 | rx_dle_intr(dev); |
2213 | } | 2238 | } |
2214 | if (status & STAT_SEGINT) | 2239 | if (status & STAT_SEGINT) |
@@ -2219,13 +2244,13 @@ static irqreturn_t ia_int(int irq, void *dev_id) | |||
2219 | } | 2244 | } |
2220 | if (status & STAT_DLETINT) | 2245 | if (status & STAT_DLETINT) |
2221 | { | 2246 | { |
2222 | *(u_int *)(iadev->reg+IPHASE5575_BUS_STATUS_REG) = STAT_DLETINT; | 2247 | writel(STAT_DLETINT, iadev->reg + IPHASE5575_BUS_STATUS_REG); |
2223 | tx_dle_intr(dev); | 2248 | tx_dle_intr(dev); |
2224 | } | 2249 | } |
2225 | if (status & (STAT_FEINT | STAT_ERRINT | STAT_MARKINT)) | 2250 | if (status & (STAT_FEINT | STAT_ERRINT | STAT_MARKINT)) |
2226 | { | 2251 | { |
2227 | if (status & STAT_FEINT) | 2252 | if (status & STAT_FEINT) |
2228 | IaFrontEndIntr(iadev); | 2253 | ia_frontend_intr(iadev); |
2229 | } | 2254 | } |
2230 | } | 2255 | } |
2231 | return IRQ_RETVAL(handled); | 2256 | return IRQ_RETVAL(handled); |
@@ -2556,7 +2581,7 @@ static int __devinit ia_start(struct atm_dev *dev) | |||
2556 | goto err_free_rx; | 2581 | goto err_free_rx; |
2557 | } | 2582 | } |
2558 | /* Get iadev->carrier_detect status */ | 2583 | /* Get iadev->carrier_detect status */ |
2559 | IaFrontEndIntr(iadev); | 2584 | ia_frontend_intr(iadev); |
2560 | } | 2585 | } |
2561 | return 0; | 2586 | return 0; |
2562 | 2587 | ||
@@ -2827,7 +2852,7 @@ static int ia_ioctl(struct atm_dev *dev, unsigned int cmd, void __user *arg) | |||
2827 | 2852 | ||
2828 | case 0xb: | 2853 | case 0xb: |
2829 | if (!capable(CAP_NET_ADMIN)) return -EPERM; | 2854 | if (!capable(CAP_NET_ADMIN)) return -EPERM; |
2830 | IaFrontEndIntr(iadev); | 2855 | ia_frontend_intr(iadev); |
2831 | break; | 2856 | break; |
2832 | case 0xa: | 2857 | case 0xa: |
2833 | if (!capable(CAP_NET_ADMIN)) return -EPERM; | 2858 | if (!capable(CAP_NET_ADMIN)) return -EPERM; |