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authorLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
committerLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
commit1da177e4c3f41524e886b7f1b8a0c1fc7321cac2 (patch)
tree0bba044c4ce775e45a88a51686b5d9f90697ea9d /drivers/atm/horizon.c
Linux-2.6.12-rc2v2.6.12-rc2
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
Diffstat (limited to 'drivers/atm/horizon.c')
-rw-r--r--drivers/atm/horizon.c2953
1 files changed, 2953 insertions, 0 deletions
diff --git a/drivers/atm/horizon.c b/drivers/atm/horizon.c
new file mode 100644
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+++ b/drivers/atm/horizon.c
@@ -0,0 +1,2953 @@
1/*
2 Madge Horizon ATM Adapter driver.
3 Copyright (C) 1995-1999 Madge Networks Ltd.
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the Free Software
17 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18
19 The GNU GPL is contained in /usr/doc/copyright/GPL on a Debian
20 system and in the file COPYING in the Linux kernel source.
21*/
22
23/*
24 IMPORTANT NOTE: Madge Networks no longer makes the adapters
25 supported by this driver and makes no commitment to maintain it.
26*/
27
28#include <linux/module.h>
29#include <linux/kernel.h>
30#include <linux/mm.h>
31#include <linux/pci.h>
32#include <linux/errno.h>
33#include <linux/atm.h>
34#include <linux/atmdev.h>
35#include <linux/sonet.h>
36#include <linux/skbuff.h>
37#include <linux/time.h>
38#include <linux/delay.h>
39#include <linux/uio.h>
40#include <linux/init.h>
41#include <linux/ioport.h>
42#include <linux/wait.h>
43
44#include <asm/system.h>
45#include <asm/io.h>
46#include <asm/atomic.h>
47#include <asm/uaccess.h>
48#include <asm/string.h>
49#include <asm/byteorder.h>
50
51#include "horizon.h"
52
53#define maintainer_string "Giuliano Procida at Madge Networks <gprocida@madge.com>"
54#define description_string "Madge ATM Horizon [Ultra] driver"
55#define version_string "1.2.1"
56
57static inline void __init show_version (void) {
58 printk ("%s version %s\n", description_string, version_string);
59}
60
61/*
62
63 CREDITS
64
65 Driver and documentation by:
66
67 Chris Aston Madge Networks
68 Giuliano Procida Madge Networks
69 Simon Benham Madge Networks
70 Simon Johnson Madge Networks
71 Various Others Madge Networks
72
73 Some inspiration taken from other drivers by:
74
75 Alexandru Cucos UTBv
76 Kari Mettinen University of Helsinki
77 Werner Almesberger EPFL LRC
78
79 Theory of Operation
80
81 I Hardware, detection, initialisation and shutdown.
82
83 1. Supported Hardware
84
85 This driver should handle all variants of the PCI Madge ATM adapters
86 with the Horizon chipset. These are all PCI cards supporting PIO, BM
87 DMA and a form of MMIO (registers only, not internal RAM).
88
89 The driver is only known to work with SONET and UTP Horizon Ultra
90 cards at 155Mb/s. However, code is in place to deal with both the
91 original Horizon and 25Mb/s operation.
92
93 There are two revisions of the Horizon ASIC: the original and the
94 Ultra. Details of hardware bugs are in section III.
95
96 The ASIC version can be distinguished by chip markings but is NOT
97 indicated by the PCI revision (all adapters seem to have PCI rev 1).
98
99 I believe that:
100
101 Horizon => Collage 25 PCI Adapter (UTP and STP)
102 Horizon Ultra => Collage 155 PCI Client (UTP or SONET)
103 Ambassador x => Collage 155 PCI Server (completely different)
104
105 Horizon (25Mb/s) is fitted with UTP and STP connectors. It seems to
106 have a Madge B154 plus glue logic serializer. I have also found a
107 really ancient version of this with slightly different glue. It
108 comes with the revision 0 (140-025-01) ASIC.
109
110 Horizon Ultra (155Mb/s) is fitted with either a Pulse Medialink
111 output (UTP) or an HP HFBR 5205 output (SONET). It has either
112 Madge's SAMBA framer or a SUNI-lite device (early versions). It
113 comes with the revision 1 (140-027-01) ASIC.
114
115 2. Detection
116
117 All Horizon-based cards present with the same PCI Vendor and Device
118 IDs. The standard Linux 2.2 PCI API is used to locate any cards and
119 to enable bus-mastering (with appropriate latency).
120
121 ATM_LAYER_STATUS in the control register distinguishes between the
122 two possible physical layers (25 and 155). It is not clear whether
123 the 155 cards can also operate at 25Mbps. We rely on the fact that a
124 card operates at 155 if and only if it has the newer Horizon Ultra
125 ASIC.
126
127 For 155 cards the two possible framers are probed for and then set
128 up for loop-timing.
129
130 3. Initialisation
131
132 The card is reset and then put into a known state. The physical
133 layer is configured for normal operation at the appropriate speed;
134 in the case of the 155 cards, the framer is initialised with
135 line-based timing; the internal RAM is zeroed and the allocation of
136 buffers for RX and TX is made; the Burnt In Address is read and
137 copied to the ATM ESI; various policy settings for RX (VPI bits,
138 unknown VCs, oam cells) are made. Ideally all policy items should be
139 configurable at module load (if not actually on-demand), however,
140 only the vpi vs vci bit allocation can be specified at insmod.
141
142 4. Shutdown
143
144 This is in response to module_cleaup. No VCs are in use and the card
145 should be idle; it is reset.
146
147 II Driver software (as it should be)
148
149 0. Traffic Parameters
150
151 The traffic classes (not an enumeration) are currently: ATM_NONE (no
152 traffic), ATM_UBR, ATM_CBR, ATM_VBR and ATM_ABR, ATM_ANYCLASS
153 (compatible with everything). Together with (perhaps only some of)
154 the following items they make up the traffic specification.
155
156 struct atm_trafprm {
157 unsigned char traffic_class; traffic class (ATM_UBR, ...)
158 int max_pcr; maximum PCR in cells per second
159 int pcr; desired PCR in cells per second
160 int min_pcr; minimum PCR in cells per second
161 int max_cdv; maximum CDV in microseconds
162 int max_sdu; maximum SDU in bytes
163 };
164
165 Note that these denote bandwidth available not bandwidth used; the
166 possibilities according to ATMF are:
167
168 Real Time (cdv and max CDT given)
169
170 CBR(pcr) pcr bandwidth always available
171 rtVBR(pcr,scr,mbs) scr bandwidth always available, upto pcr at mbs too
172
173 Non Real Time
174
175 nrtVBR(pcr,scr,mbs) scr bandwidth always available, upto pcr at mbs too
176 UBR()
177 ABR(mcr,pcr) mcr bandwidth always available, upto pcr (depending) too
178
179 mbs is max burst size (bucket)
180 pcr and scr have associated cdvt values
181 mcr is like scr but has no cdtv
182 cdtv may differ at each hop
183
184 Some of the above items are qos items (as opposed to traffic
185 parameters). We have nothing to do with qos. All except ABR can have
186 their traffic parameters converted to GCRA parameters. The GCRA may
187 be implemented as a (real-number) leaky bucket. The GCRA can be used
188 in complicated ways by switches and in simpler ways by end-stations.
189 It can be used both to filter incoming cells and shape out-going
190 cells.
191
192 ATM Linux actually supports:
193
194 ATM_NONE() (no traffic in this direction)
195 ATM_UBR(max_frame_size)
196 ATM_CBR(max/min_pcr, max_cdv, max_frame_size)
197
198 0 or ATM_MAX_PCR are used to indicate maximum available PCR
199
200 A traffic specification consists of the AAL type and separate
201 traffic specifications for either direction. In ATM Linux it is:
202
203 struct atm_qos {
204 struct atm_trafprm txtp;
205 struct atm_trafprm rxtp;
206 unsigned char aal;
207 };
208
209 AAL types are:
210
211 ATM_NO_AAL AAL not specified
212 ATM_AAL0 "raw" ATM cells
213 ATM_AAL1 AAL1 (CBR)
214 ATM_AAL2 AAL2 (VBR)
215 ATM_AAL34 AAL3/4 (data)
216 ATM_AAL5 AAL5 (data)
217 ATM_SAAL signaling AAL
218
219 The Horizon has support for AAL frame types: 0, 3/4 and 5. However,
220 it does not implement AAL 3/4 SAR and it has a different notion of
221 "raw cell" to ATM Linux's (48 bytes vs. 52 bytes) so neither are
222 supported by this driver.
223
224 The Horizon has limited support for ABR (including UBR), VBR and
225 CBR. Each TX channel has a bucket (containing up to 31 cell units)
226 and two timers (PCR and SCR) associated with it that can be used to
227 govern cell emissions and host notification (in the case of ABR this
228 is presumably so that RM cells may be emitted at appropriate times).
229 The timers may either be disabled or may be set to any of 240 values
230 (determined by the clock crystal, a fixed (?) per-device divider, a
231 configurable divider and a configurable timer preload value).
232
233 At the moment only UBR and CBR are supported by the driver. VBR will
234 be supported as soon as ATM for Linux supports it. ABR support is
235 very unlikely as RM cell handling is completely up to the driver.
236
237 1. TX (TX channel setup and TX transfer)
238
239 The TX half of the driver owns the TX Horizon registers. The TX
240 component in the IRQ handler is the BM completion handler. This can
241 only be entered when tx_busy is true (enforced by hardware). The
242 other TX component can only be entered when tx_busy is false
243 (enforced by driver). So TX is single-threaded.
244
245 Apart from a minor optimisation to not re-select the last channel,
246 the TX send component works as follows:
247
248 Atomic test and set tx_busy until we succeed; we should implement
249 some sort of timeout so that tx_busy will never be stuck at true.
250
251 If no TX channel is set up for this VC we wait for an idle one (if
252 necessary) and set it up.
253
254 At this point we have a TX channel ready for use. We wait for enough
255 buffers to become available then start a TX transmit (set the TX
256 descriptor, schedule transfer, exit).
257
258 The IRQ component handles TX completion (stats, free buffer, tx_busy
259 unset, exit). We also re-schedule further transfers for the same
260 frame if needed.
261
262 TX setup in more detail:
263
264 TX open is a nop, the relevant information is held in the hrz_vcc
265 (vcc->dev_data) structure and is "cached" on the card.
266
267 TX close gets the TX lock and clears the channel from the "cache".
268
269 2. RX (Data Available and RX transfer)
270
271 The RX half of the driver owns the RX registers. There are two RX
272 components in the IRQ handler: the data available handler deals with
273 fresh data that has arrived on the card, the BM completion handler
274 is very similar to the TX completion handler. The data available
275 handler grabs the rx_lock and it is only released once the data has
276 been discarded or completely transferred to the host. The BM
277 completion handler only runs when the lock is held; the data
278 available handler is locked out over the same period.
279
280 Data available on the card triggers an interrupt. If the data is not
281 suitable for our existing RX channels or we cannot allocate a buffer
282 it is flushed. Otherwise an RX receive is scheduled. Multiple RX
283 transfers may be scheduled for the same frame.
284
285 RX setup in more detail:
286
287 RX open...
288 RX close...
289
290 III Hardware Bugs
291
292 0. Byte vs Word addressing of adapter RAM.
293
294 A design feature; see the .h file (especially the memory map).
295
296 1. Bus Master Data Transfers (original Horizon only, fixed in Ultra)
297
298 The host must not start a transmit direction transfer at a
299 non-four-byte boundary in host memory. Instead the host should
300 perform a byte, or a two byte, or one byte followed by two byte
301 transfer in order to start the rest of the transfer on a four byte
302 boundary. RX is OK.
303
304 Simultaneous transmit and receive direction bus master transfers are
305 not allowed.
306
307 The simplest solution to these two is to always do PIO (never DMA)
308 in the TX direction on the original Horizon. More complicated
309 solutions are likely to hurt my brain.
310
311 2. Loss of buffer on close VC
312
313 When a VC is being closed, the buffer associated with it is not
314 returned to the pool. The host must store the reference to this
315 buffer and when opening a new VC then give it to that new VC.
316
317 The host intervention currently consists of stacking such a buffer
318 pointer at VC close and checking the stack at VC open.
319
320 3. Failure to close a VC
321
322 If a VC is currently receiving a frame then closing the VC may fail
323 and the frame continues to be received.
324
325 The solution is to make sure any received frames are flushed when
326 ready. This is currently done just before the solution to 2.
327
328 4. PCI bus (original Horizon only, fixed in Ultra)
329
330 Reading from the data port prior to initialisation will hang the PCI
331 bus. Just don't do that then! We don't.
332
333 IV To Do List
334
335 . Timer code may be broken.
336
337 . Allow users to specify buffer allocation split for TX and RX.
338
339 . Deal once and for all with buggy VC close.
340
341 . Handle interrupted and/or non-blocking operations.
342
343 . Change some macros to functions and move from .h to .c.
344
345 . Try to limit the number of TX frames each VC may have queued, in
346 order to reduce the chances of TX buffer exhaustion.
347
348 . Implement VBR (bucket and timers not understood) and ABR (need to
349 do RM cells manually); also no Linux support for either.
350
351 . Implement QoS changes on open VCs (involves extracting parts of VC open
352 and close into separate functions and using them to make changes).
353
354*/
355
356/********** globals **********/
357
358static void do_housekeeping (unsigned long arg);
359
360static unsigned short debug = 0;
361static unsigned short vpi_bits = 0;
362static int max_tx_size = 9000;
363static int max_rx_size = 9000;
364static unsigned char pci_lat = 0;
365
366/********** access functions **********/
367
368/* Read / Write Horizon registers */
369static inline void wr_regl (const hrz_dev * dev, unsigned char reg, u32 data) {
370 outl (cpu_to_le32 (data), dev->iobase + reg);
371}
372
373static inline u32 rd_regl (const hrz_dev * dev, unsigned char reg) {
374 return le32_to_cpu (inl (dev->iobase + reg));
375}
376
377static inline void wr_regw (const hrz_dev * dev, unsigned char reg, u16 data) {
378 outw (cpu_to_le16 (data), dev->iobase + reg);
379}
380
381static inline u16 rd_regw (const hrz_dev * dev, unsigned char reg) {
382 return le16_to_cpu (inw (dev->iobase + reg));
383}
384
385static inline void wrs_regb (const hrz_dev * dev, unsigned char reg, void * addr, u32 len) {
386 outsb (dev->iobase + reg, addr, len);
387}
388
389static inline void rds_regb (const hrz_dev * dev, unsigned char reg, void * addr, u32 len) {
390 insb (dev->iobase + reg, addr, len);
391}
392
393/* Read / Write to a given address in Horizon buffer memory.
394 Interrupts must be disabled between the address register and data
395 port accesses as these must form an atomic operation. */
396static inline void wr_mem (const hrz_dev * dev, HDW * addr, u32 data) {
397 // wr_regl (dev, MEM_WR_ADDR_REG_OFF, (u32) addr);
398 wr_regl (dev, MEM_WR_ADDR_REG_OFF, (addr - (HDW *) 0) * sizeof(HDW));
399 wr_regl (dev, MEMORY_PORT_OFF, data);
400}
401
402static inline u32 rd_mem (const hrz_dev * dev, HDW * addr) {
403 // wr_regl (dev, MEM_RD_ADDR_REG_OFF, (u32) addr);
404 wr_regl (dev, MEM_RD_ADDR_REG_OFF, (addr - (HDW *) 0) * sizeof(HDW));
405 return rd_regl (dev, MEMORY_PORT_OFF);
406}
407
408static inline void wr_framer (const hrz_dev * dev, u32 addr, u32 data) {
409 wr_regl (dev, MEM_WR_ADDR_REG_OFF, (u32) addr | 0x80000000);
410 wr_regl (dev, MEMORY_PORT_OFF, data);
411}
412
413static inline u32 rd_framer (const hrz_dev * dev, u32 addr) {
414 wr_regl (dev, MEM_RD_ADDR_REG_OFF, (u32) addr | 0x80000000);
415 return rd_regl (dev, MEMORY_PORT_OFF);
416}
417
418/********** specialised access functions **********/
419
420/* RX */
421
422static inline void FLUSH_RX_CHANNEL (hrz_dev * dev, u16 channel) {
423 wr_regw (dev, RX_CHANNEL_PORT_OFF, FLUSH_CHANNEL | channel);
424 return;
425}
426
427static inline void WAIT_FLUSH_RX_COMPLETE (hrz_dev * dev) {
428 while (rd_regw (dev, RX_CHANNEL_PORT_OFF) & FLUSH_CHANNEL)
429 ;
430 return;
431}
432
433static inline void SELECT_RX_CHANNEL (hrz_dev * dev, u16 channel) {
434 wr_regw (dev, RX_CHANNEL_PORT_OFF, channel);
435 return;
436}
437
438static inline void WAIT_UPDATE_COMPLETE (hrz_dev * dev) {
439 while (rd_regw (dev, RX_CHANNEL_PORT_OFF) & RX_CHANNEL_UPDATE_IN_PROGRESS)
440 ;
441 return;
442}
443
444/* TX */
445
446static inline void SELECT_TX_CHANNEL (hrz_dev * dev, u16 tx_channel) {
447 wr_regl (dev, TX_CHANNEL_PORT_OFF, tx_channel);
448 return;
449}
450
451/* Update or query one configuration parameter of a particular channel. */
452
453static inline void update_tx_channel_config (hrz_dev * dev, short chan, u8 mode, u16 value) {
454 wr_regw (dev, TX_CHANNEL_CONFIG_COMMAND_OFF,
455 chan * TX_CHANNEL_CONFIG_MULT | mode);
456 wr_regw (dev, TX_CHANNEL_CONFIG_DATA_OFF, value);
457 return;
458}
459
460static inline u16 query_tx_channel_config (hrz_dev * dev, short chan, u8 mode) {
461 wr_regw (dev, TX_CHANNEL_CONFIG_COMMAND_OFF,
462 chan * TX_CHANNEL_CONFIG_MULT | mode);
463 return rd_regw (dev, TX_CHANNEL_CONFIG_DATA_OFF);
464}
465
466/********** dump functions **********/
467
468static inline void dump_skb (char * prefix, unsigned int vc, struct sk_buff * skb) {
469#ifdef DEBUG_HORIZON
470 unsigned int i;
471 unsigned char * data = skb->data;
472 PRINTDB (DBG_DATA, "%s(%u) ", prefix, vc);
473 for (i=0; i<skb->len && i < 256;i++)
474 PRINTDM (DBG_DATA, "%02x ", data[i]);
475 PRINTDE (DBG_DATA,"");
476#else
477 (void) prefix;
478 (void) vc;
479 (void) skb;
480#endif
481 return;
482}
483
484static inline void dump_regs (hrz_dev * dev) {
485#ifdef DEBUG_HORIZON
486 PRINTD (DBG_REGS, "CONTROL 0: %#x", rd_regl (dev, CONTROL_0_REG));
487 PRINTD (DBG_REGS, "RX CONFIG: %#x", rd_regw (dev, RX_CONFIG_OFF));
488 PRINTD (DBG_REGS, "TX CONFIG: %#x", rd_regw (dev, TX_CONFIG_OFF));
489 PRINTD (DBG_REGS, "TX STATUS: %#x", rd_regw (dev, TX_STATUS_OFF));
490 PRINTD (DBG_REGS, "IRQ ENBLE: %#x", rd_regl (dev, INT_ENABLE_REG_OFF));
491 PRINTD (DBG_REGS, "IRQ SORCE: %#x", rd_regl (dev, INT_SOURCE_REG_OFF));
492#else
493 (void) dev;
494#endif
495 return;
496}
497
498static inline void dump_framer (hrz_dev * dev) {
499#ifdef DEBUG_HORIZON
500 unsigned int i;
501 PRINTDB (DBG_REGS, "framer registers:");
502 for (i = 0; i < 0x10; ++i)
503 PRINTDM (DBG_REGS, " %02x", rd_framer (dev, i));
504 PRINTDE (DBG_REGS,"");
505#else
506 (void) dev;
507#endif
508 return;
509}
510
511/********** VPI/VCI <-> (RX) channel conversions **********/
512
513/* RX channels are 10 bit integers, these fns are quite paranoid */
514
515static inline int channel_to_vpivci (const u16 channel, short * vpi, int * vci) {
516 unsigned short vci_bits = 10 - vpi_bits;
517 if ((channel & RX_CHANNEL_MASK) == channel) {
518 *vci = channel & ((~0)<<vci_bits);
519 *vpi = channel >> vci_bits;
520 return channel ? 0 : -EINVAL;
521 }
522 return -EINVAL;
523}
524
525static inline int vpivci_to_channel (u16 * channel, const short vpi, const int vci) {
526 unsigned short vci_bits = 10 - vpi_bits;
527 if (0 <= vpi && vpi < 1<<vpi_bits && 0 <= vci && vci < 1<<vci_bits) {
528 *channel = vpi<<vci_bits | vci;
529 return *channel ? 0 : -EINVAL;
530 }
531 return -EINVAL;
532}
533
534/********** decode RX queue entries **********/
535
536static inline u16 rx_q_entry_to_length (u32 x) {
537 return x & RX_Q_ENTRY_LENGTH_MASK;
538}
539
540static inline u16 rx_q_entry_to_rx_channel (u32 x) {
541 return (x>>RX_Q_ENTRY_CHANNEL_SHIFT) & RX_CHANNEL_MASK;
542}
543
544/* Cell Transmit Rate Values
545 *
546 * the cell transmit rate (cells per sec) can be set to a variety of
547 * different values by specifying two parameters: a timer preload from
548 * 1 to 16 (stored as 0 to 15) and a clock divider (2 to the power of
549 * an exponent from 0 to 14; the special value 15 disables the timer).
550 *
551 * cellrate = baserate / (preload * 2^divider)
552 *
553 * The maximum cell rate that can be specified is therefore just the
554 * base rate. Halving the preload is equivalent to adding 1 to the
555 * divider and so values 1 to 8 of the preload are redundant except
556 * in the case of a maximal divider (14).
557 *
558 * Given a desired cell rate, an algorithm to determine the preload
559 * and divider is:
560 *
561 * a) x = baserate / cellrate, want p * 2^d = x (as far as possible)
562 * b) if x > 16 * 2^14 then set p = 16, d = 14 (min rate), done
563 * if x <= 16 then set p = x, d = 0 (high rates), done
564 * c) now have 16 < x <= 2^18, or 1 < x/16 <= 2^14 and we want to
565 * know n such that 2^(n-1) < x/16 <= 2^n, so slide a bit until
566 * we find the range (n will be between 1 and 14), set d = n
567 * d) Also have 8 < x/2^n <= 16, so set p nearest x/2^n
568 *
569 * The algorithm used below is a minor variant of the above.
570 *
571 * The base rate is derived from the oscillator frequency (Hz) using a
572 * fixed divider:
573 *
574 * baserate = freq / 32 in the case of some Unknown Card
575 * baserate = freq / 8 in the case of the Horizon 25
576 * baserate = freq / 8 in the case of the Horizon Ultra 155
577 *
578 * The Horizon cards have oscillators and base rates as follows:
579 *
580 * Card Oscillator Base Rate
581 * Unknown Card 33 MHz 1.03125 MHz (33 MHz = PCI freq)
582 * Horizon 25 32 MHz 4 MHz
583 * Horizon Ultra 155 40 MHz 5 MHz
584 *
585 * The following defines give the base rates in Hz. These were
586 * previously a factor of 100 larger, no doubt someone was using
587 * cps*100.
588 */
589
590#define BR_UKN 1031250l
591#define BR_HRZ 4000000l
592#define BR_ULT 5000000l
593
594// d is an exponent
595#define CR_MIND 0
596#define CR_MAXD 14
597
598// p ranges from 1 to a power of 2
599#define CR_MAXPEXP 4
600
601static int make_rate (const hrz_dev * dev, u32 c, rounding r,
602 u16 * bits, unsigned int * actual)
603{
604 // note: rounding the rate down means rounding 'p' up
605 const unsigned long br = test_bit(ultra, &dev->flags) ? BR_ULT : BR_HRZ;
606
607 u32 div = CR_MIND;
608 u32 pre;
609
610 // br_exp and br_man are used to avoid overflowing (c*maxp*2^d) in
611 // the tests below. We could think harder about exact possibilities
612 // of failure...
613
614 unsigned long br_man = br;
615 unsigned int br_exp = 0;
616
617 PRINTD (DBG_QOS|DBG_FLOW, "make_rate b=%lu, c=%u, %s", br, c,
618 r == round_up ? "up" : r == round_down ? "down" : "nearest");
619
620 // avoid div by zero
621 if (!c) {
622 PRINTD (DBG_QOS|DBG_ERR, "zero rate is not allowed!");
623 return -EINVAL;
624 }
625
626 while (br_exp < CR_MAXPEXP + CR_MIND && (br_man % 2 == 0)) {
627 br_man = br_man >> 1;
628 ++br_exp;
629 }
630 // (br >>br_exp) <<br_exp == br and
631 // br_exp <= CR_MAXPEXP+CR_MIND
632
633 if (br_man <= (c << (CR_MAXPEXP+CR_MIND-br_exp))) {
634 // Equivalent to: B <= (c << (MAXPEXP+MIND))
635 // take care of rounding
636 switch (r) {
637 case round_down:
638 pre = (br+(c<<div)-1)/(c<<div);
639 // but p must be non-zero
640 if (!pre)
641 pre = 1;
642 break;
643 case round_nearest:
644 pre = (br+(c<<div)/2)/(c<<div);
645 // but p must be non-zero
646 if (!pre)
647 pre = 1;
648 break;
649 default: /* round_up */
650 pre = br/(c<<div);
651 // but p must be non-zero
652 if (!pre)
653 return -EINVAL;
654 }
655 PRINTD (DBG_QOS, "A: p=%u, d=%u", pre, div);
656 goto got_it;
657 }
658
659 // at this point we have
660 // d == MIND and (c << (MAXPEXP+MIND)) < B
661 while (div < CR_MAXD) {
662 div++;
663 if (br_man <= (c << (CR_MAXPEXP+div-br_exp))) {
664 // Equivalent to: B <= (c << (MAXPEXP+d))
665 // c << (MAXPEXP+d-1) < B <= c << (MAXPEXP+d)
666 // 1 << (MAXPEXP-1) < B/2^d/c <= 1 << MAXPEXP
667 // MAXP/2 < B/c2^d <= MAXP
668 // take care of rounding
669 switch (r) {
670 case round_down:
671 pre = (br+(c<<div)-1)/(c<<div);
672 break;
673 case round_nearest:
674 pre = (br+(c<<div)/2)/(c<<div);
675 break;
676 default: /* round_up */
677 pre = br/(c<<div);
678 }
679 PRINTD (DBG_QOS, "B: p=%u, d=%u", pre, div);
680 goto got_it;
681 }
682 }
683 // at this point we have
684 // d == MAXD and (c << (MAXPEXP+MAXD)) < B
685 // but we cannot go any higher
686 // take care of rounding
687 if (r == round_down)
688 return -EINVAL;
689 pre = 1 << CR_MAXPEXP;
690 PRINTD (DBG_QOS, "C: p=%u, d=%u", pre, div);
691got_it:
692 // paranoia
693 if (div > CR_MAXD || (!pre) || pre > 1<<CR_MAXPEXP) {
694 PRINTD (DBG_QOS, "set_cr internal failure: d=%u p=%u",
695 div, pre);
696 return -EINVAL;
697 } else {
698 if (bits)
699 *bits = (div<<CLOCK_SELECT_SHIFT) | (pre-1);
700 if (actual) {
701 *actual = (br + (pre<<div) - 1) / (pre<<div);
702 PRINTD (DBG_QOS, "actual rate: %u", *actual);
703 }
704 return 0;
705 }
706}
707
708static int make_rate_with_tolerance (const hrz_dev * dev, u32 c, rounding r, unsigned int tol,
709 u16 * bit_pattern, unsigned int * actual) {
710 unsigned int my_actual;
711
712 PRINTD (DBG_QOS|DBG_FLOW, "make_rate_with_tolerance c=%u, %s, tol=%u",
713 c, (r == round_up) ? "up" : (r == round_down) ? "down" : "nearest", tol);
714
715 if (!actual)
716 // actual rate is not returned
717 actual = &my_actual;
718
719 if (make_rate (dev, c, round_nearest, bit_pattern, actual))
720 // should never happen as round_nearest always succeeds
721 return -1;
722
723 if (c - tol <= *actual && *actual <= c + tol)
724 // within tolerance
725 return 0;
726 else
727 // intolerant, try rounding instead
728 return make_rate (dev, c, r, bit_pattern, actual);
729}
730
731/********** Listen on a VC **********/
732
733static int hrz_open_rx (hrz_dev * dev, u16 channel) {
734 // is there any guarantee that we don't get two simulataneous
735 // identical calls of this function from different processes? yes
736 // rate_lock
737 unsigned long flags;
738 u32 channel_type; // u16?
739
740 u16 buf_ptr = RX_CHANNEL_IDLE;
741
742 rx_ch_desc * rx_desc = &memmap->rx_descs[channel];
743
744 PRINTD (DBG_FLOW, "hrz_open_rx %x", channel);
745
746 spin_lock_irqsave (&dev->mem_lock, flags);
747 channel_type = rd_mem (dev, &rx_desc->wr_buf_type) & BUFFER_PTR_MASK;
748 spin_unlock_irqrestore (&dev->mem_lock, flags);
749
750 // very serious error, should never occur
751 if (channel_type != RX_CHANNEL_DISABLED) {
752 PRINTD (DBG_ERR|DBG_VCC, "RX channel for VC already open");
753 return -EBUSY; // clean up?
754 }
755
756 // Give back spare buffer
757 if (dev->noof_spare_buffers) {
758 buf_ptr = dev->spare_buffers[--dev->noof_spare_buffers];
759 PRINTD (DBG_VCC, "using a spare buffer: %u", buf_ptr);
760 // should never occur
761 if (buf_ptr == RX_CHANNEL_DISABLED || buf_ptr == RX_CHANNEL_IDLE) {
762 // but easy to recover from
763 PRINTD (DBG_ERR|DBG_VCC, "bad spare buffer pointer, using IDLE");
764 buf_ptr = RX_CHANNEL_IDLE;
765 }
766 } else {
767 PRINTD (DBG_VCC, "using IDLE buffer pointer");
768 }
769
770 // Channel is currently disabled so change its status to idle
771
772 // do we really need to save the flags again?
773 spin_lock_irqsave (&dev->mem_lock, flags);
774
775 wr_mem (dev, &rx_desc->wr_buf_type,
776 buf_ptr | CHANNEL_TYPE_AAL5 | FIRST_CELL_OF_AAL5_FRAME);
777 if (buf_ptr != RX_CHANNEL_IDLE)
778 wr_mem (dev, &rx_desc->rd_buf_type, buf_ptr);
779
780 spin_unlock_irqrestore (&dev->mem_lock, flags);
781
782 // rxer->rate = make_rate (qos->peak_cells);
783
784 PRINTD (DBG_FLOW, "hrz_open_rx ok");
785
786 return 0;
787}
788
789#if 0
790/********** change vc rate for a given vc **********/
791
792static void hrz_change_vc_qos (ATM_RXER * rxer, MAAL_QOS * qos) {
793 rxer->rate = make_rate (qos->peak_cells);
794}
795#endif
796
797/********** free an skb (as per ATM device driver documentation) **********/
798
799static inline void hrz_kfree_skb (struct sk_buff * skb) {
800 if (ATM_SKB(skb)->vcc->pop) {
801 ATM_SKB(skb)->vcc->pop (ATM_SKB(skb)->vcc, skb);
802 } else {
803 dev_kfree_skb_any (skb);
804 }
805}
806
807/********** cancel listen on a VC **********/
808
809static void hrz_close_rx (hrz_dev * dev, u16 vc) {
810 unsigned long flags;
811
812 u32 value;
813
814 u32 r1, r2;
815
816 rx_ch_desc * rx_desc = &memmap->rx_descs[vc];
817
818 int was_idle = 0;
819
820 spin_lock_irqsave (&dev->mem_lock, flags);
821 value = rd_mem (dev, &rx_desc->wr_buf_type) & BUFFER_PTR_MASK;
822 spin_unlock_irqrestore (&dev->mem_lock, flags);
823
824 if (value == RX_CHANNEL_DISABLED) {
825 // I suppose this could happen once we deal with _NONE traffic properly
826 PRINTD (DBG_VCC, "closing VC: RX channel %u already disabled", vc);
827 return;
828 }
829 if (value == RX_CHANNEL_IDLE)
830 was_idle = 1;
831
832 spin_lock_irqsave (&dev->mem_lock, flags);
833
834 for (;;) {
835 wr_mem (dev, &rx_desc->wr_buf_type, RX_CHANNEL_DISABLED);
836
837 if ((rd_mem (dev, &rx_desc->wr_buf_type) & BUFFER_PTR_MASK) == RX_CHANNEL_DISABLED)
838 break;
839
840 was_idle = 0;
841 }
842
843 if (was_idle) {
844 spin_unlock_irqrestore (&dev->mem_lock, flags);
845 return;
846 }
847
848 WAIT_FLUSH_RX_COMPLETE(dev);
849
850 // XXX Is this all really necessary? We can rely on the rx_data_av
851 // handler to discard frames that remain queued for delivery. If the
852 // worry is that immediately reopening the channel (perhaps by a
853 // different process) may cause some data to be mis-delivered then
854 // there may still be a simpler solution (such as busy-waiting on
855 // rx_busy once the channel is disabled or before a new one is
856 // opened - does this leave any holes?). Arguably setting up and
857 // tearing down the TX and RX halves of each virtual circuit could
858 // most safely be done within ?x_busy protected regions.
859
860 // OK, current changes are that Simon's marker is disabled and we DO
861 // look for NULL rxer elsewhere. The code here seems flush frames
862 // and then remember the last dead cell belonging to the channel
863 // just disabled - the cell gets relinked at the next vc_open.
864 // However, when all VCs are closed or only a few opened there are a
865 // handful of buffers that are unusable.
866
867 // Does anyone feel like documenting spare_buffers properly?
868 // Does anyone feel like fixing this in a nicer way?
869
870 // Flush any data which is left in the channel
871 for (;;) {
872 // Change the rx channel port to something different to the RX
873 // channel we are trying to close to force Horizon to flush the rx
874 // channel read and write pointers.
875
876 u16 other = vc^(RX_CHANS/2);
877
878 SELECT_RX_CHANNEL (dev, other);
879 WAIT_UPDATE_COMPLETE (dev);
880
881 r1 = rd_mem (dev, &rx_desc->rd_buf_type);
882
883 // Select this RX channel. Flush doesn't seem to work unless we
884 // select an RX channel before hand
885
886 SELECT_RX_CHANNEL (dev, vc);
887 WAIT_UPDATE_COMPLETE (dev);
888
889 // Attempt to flush a frame on this RX channel
890
891 FLUSH_RX_CHANNEL (dev, vc);
892 WAIT_FLUSH_RX_COMPLETE (dev);
893
894 // Force Horizon to flush rx channel read and write pointers as before
895
896 SELECT_RX_CHANNEL (dev, other);
897 WAIT_UPDATE_COMPLETE (dev);
898
899 r2 = rd_mem (dev, &rx_desc->rd_buf_type);
900
901 PRINTD (DBG_VCC|DBG_RX, "r1 = %u, r2 = %u", r1, r2);
902
903 if (r1 == r2) {
904 dev->spare_buffers[dev->noof_spare_buffers++] = (u16)r1;
905 break;
906 }
907 }
908
909#if 0
910 {
911 rx_q_entry * wr_ptr = &memmap->rx_q_entries[rd_regw (dev, RX_QUEUE_WR_PTR_OFF)];
912 rx_q_entry * rd_ptr = dev->rx_q_entry;
913
914 PRINTD (DBG_VCC|DBG_RX, "rd_ptr = %u, wr_ptr = %u", rd_ptr, wr_ptr);
915
916 while (rd_ptr != wr_ptr) {
917 u32 x = rd_mem (dev, (HDW *) rd_ptr);
918
919 if (vc == rx_q_entry_to_rx_channel (x)) {
920 x |= SIMONS_DODGEY_MARKER;
921
922 PRINTD (DBG_RX|DBG_VCC|DBG_WARN, "marking a frame as dodgey");
923
924 wr_mem (dev, (HDW *) rd_ptr, x);
925 }
926
927 if (rd_ptr == dev->rx_q_wrap)
928 rd_ptr = dev->rx_q_reset;
929 else
930 rd_ptr++;
931 }
932 }
933#endif
934
935 spin_unlock_irqrestore (&dev->mem_lock, flags);
936
937 return;
938}
939
940/********** schedule RX transfers **********/
941
942// Note on tail recursion: a GCC developer said that it is not likely
943// to be fixed soon, so do not define TAILRECUSRIONWORKS unless you
944// are sure it does as you may otherwise overflow the kernel stack.
945
946// giving this fn a return value would help GCC, alledgedly
947
948static void rx_schedule (hrz_dev * dev, int irq) {
949 unsigned int rx_bytes;
950
951 int pio_instead = 0;
952#ifndef TAILRECURSIONWORKS
953 pio_instead = 1;
954 while (pio_instead) {
955#endif
956 // bytes waiting for RX transfer
957 rx_bytes = dev->rx_bytes;
958
959#if 0
960 spin_count = 0;
961 while (rd_regl (dev, MASTER_RX_COUNT_REG_OFF)) {
962 PRINTD (DBG_RX|DBG_WARN, "RX error: other PCI Bus Master RX still in progress!");
963 if (++spin_count > 10) {
964 PRINTD (DBG_RX|DBG_ERR, "spun out waiting PCI Bus Master RX completion");
965 wr_regl (dev, MASTER_RX_COUNT_REG_OFF, 0);
966 clear_bit (rx_busy, &dev->flags);
967 hrz_kfree_skb (dev->rx_skb);
968 return;
969 }
970 }
971#endif
972
973 // this code follows the TX code but (at the moment) there is only
974 // one region - the skb itself. I don't know if this will change,
975 // but it doesn't hurt to have the code here, disabled.
976
977 if (rx_bytes) {
978 // start next transfer within same region
979 if (rx_bytes <= MAX_PIO_COUNT) {
980 PRINTD (DBG_RX|DBG_BUS, "(pio)");
981 pio_instead = 1;
982 }
983 if (rx_bytes <= MAX_TRANSFER_COUNT) {
984 PRINTD (DBG_RX|DBG_BUS, "(simple or last multi)");
985 dev->rx_bytes = 0;
986 } else {
987 PRINTD (DBG_RX|DBG_BUS, "(continuing multi)");
988 dev->rx_bytes = rx_bytes - MAX_TRANSFER_COUNT;
989 rx_bytes = MAX_TRANSFER_COUNT;
990 }
991 } else {
992 // rx_bytes == 0 -- we're between regions
993 // regions remaining to transfer
994#if 0
995 unsigned int rx_regions = dev->rx_regions;
996#else
997 unsigned int rx_regions = 0;
998#endif
999
1000 if (rx_regions) {
1001#if 0
1002 // start a new region
1003 dev->rx_addr = dev->rx_iovec->iov_base;
1004 rx_bytes = dev->rx_iovec->iov_len;
1005 ++dev->rx_iovec;
1006 dev->rx_regions = rx_regions - 1;
1007
1008 if (rx_bytes <= MAX_PIO_COUNT) {
1009 PRINTD (DBG_RX|DBG_BUS, "(pio)");
1010 pio_instead = 1;
1011 }
1012 if (rx_bytes <= MAX_TRANSFER_COUNT) {
1013 PRINTD (DBG_RX|DBG_BUS, "(full region)");
1014 dev->rx_bytes = 0;
1015 } else {
1016 PRINTD (DBG_RX|DBG_BUS, "(start multi region)");
1017 dev->rx_bytes = rx_bytes - MAX_TRANSFER_COUNT;
1018 rx_bytes = MAX_TRANSFER_COUNT;
1019 }
1020#endif
1021 } else {
1022 // rx_regions == 0
1023 // that's all folks - end of frame
1024 struct sk_buff * skb = dev->rx_skb;
1025 // dev->rx_iovec = 0;
1026
1027 FLUSH_RX_CHANNEL (dev, dev->rx_channel);
1028
1029 dump_skb ("<<<", dev->rx_channel, skb);
1030
1031 PRINTD (DBG_RX|DBG_SKB, "push %p %u", skb->data, skb->len);
1032
1033 {
1034 struct atm_vcc * vcc = ATM_SKB(skb)->vcc;
1035 // VC layer stats
1036 atomic_inc(&vcc->stats->rx);
1037 do_gettimeofday(&skb->stamp);
1038 // end of our responsability
1039 vcc->push (vcc, skb);
1040 }
1041 }
1042 }
1043
1044 // note: writing RX_COUNT clears any interrupt condition
1045 if (rx_bytes) {
1046 if (pio_instead) {
1047 if (irq)
1048 wr_regl (dev, MASTER_RX_COUNT_REG_OFF, 0);
1049 rds_regb (dev, DATA_PORT_OFF, dev->rx_addr, rx_bytes);
1050 } else {
1051 wr_regl (dev, MASTER_RX_ADDR_REG_OFF, virt_to_bus (dev->rx_addr));
1052 wr_regl (dev, MASTER_RX_COUNT_REG_OFF, rx_bytes);
1053 }
1054 dev->rx_addr += rx_bytes;
1055 } else {
1056 if (irq)
1057 wr_regl (dev, MASTER_RX_COUNT_REG_OFF, 0);
1058 // allow another RX thread to start
1059 YELLOW_LED_ON(dev);
1060 clear_bit (rx_busy, &dev->flags);
1061 PRINTD (DBG_RX, "cleared rx_busy for dev %p", dev);
1062 }
1063
1064#ifdef TAILRECURSIONWORKS
1065 // and we all bless optimised tail calls
1066 if (pio_instead)
1067 return rx_schedule (dev, 0);
1068 return;
1069#else
1070 // grrrrrrr!
1071 irq = 0;
1072 }
1073 return;
1074#endif
1075}
1076
1077/********** handle RX bus master complete events **********/
1078
1079static inline void rx_bus_master_complete_handler (hrz_dev * dev) {
1080 if (test_bit (rx_busy, &dev->flags)) {
1081 rx_schedule (dev, 1);
1082 } else {
1083 PRINTD (DBG_RX|DBG_ERR, "unexpected RX bus master completion");
1084 // clear interrupt condition on adapter
1085 wr_regl (dev, MASTER_RX_COUNT_REG_OFF, 0);
1086 }
1087 return;
1088}
1089
1090/********** (queue to) become the next TX thread **********/
1091
1092static inline int tx_hold (hrz_dev * dev) {
1093 PRINTD (DBG_TX, "sleeping at tx lock %p %lu", dev, dev->flags);
1094 wait_event_interruptible(dev->tx_queue, (!test_and_set_bit(tx_busy, &dev->flags)));
1095 PRINTD (DBG_TX, "woken at tx lock %p %lu", dev, dev->flags);
1096 if (signal_pending (current))
1097 return -1;
1098 PRINTD (DBG_TX, "set tx_busy for dev %p", dev);
1099 return 0;
1100}
1101
1102/********** allow another TX thread to start **********/
1103
1104static inline void tx_release (hrz_dev * dev) {
1105 clear_bit (tx_busy, &dev->flags);
1106 PRINTD (DBG_TX, "cleared tx_busy for dev %p", dev);
1107 wake_up_interruptible (&dev->tx_queue);
1108}
1109
1110/********** schedule TX transfers **********/
1111
1112static void tx_schedule (hrz_dev * const dev, int irq) {
1113 unsigned int tx_bytes;
1114
1115 int append_desc = 0;
1116
1117 int pio_instead = 0;
1118#ifndef TAILRECURSIONWORKS
1119 pio_instead = 1;
1120 while (pio_instead) {
1121#endif
1122 // bytes in current region waiting for TX transfer
1123 tx_bytes = dev->tx_bytes;
1124
1125#if 0
1126 spin_count = 0;
1127 while (rd_regl (dev, MASTER_TX_COUNT_REG_OFF)) {
1128 PRINTD (DBG_TX|DBG_WARN, "TX error: other PCI Bus Master TX still in progress!");
1129 if (++spin_count > 10) {
1130 PRINTD (DBG_TX|DBG_ERR, "spun out waiting PCI Bus Master TX completion");
1131 wr_regl (dev, MASTER_TX_COUNT_REG_OFF, 0);
1132 tx_release (dev);
1133 hrz_kfree_skb (dev->tx_skb);
1134 return;
1135 }
1136 }
1137#endif
1138
1139 if (tx_bytes) {
1140 // start next transfer within same region
1141 if (!test_bit (ultra, &dev->flags) || tx_bytes <= MAX_PIO_COUNT) {
1142 PRINTD (DBG_TX|DBG_BUS, "(pio)");
1143 pio_instead = 1;
1144 }
1145 if (tx_bytes <= MAX_TRANSFER_COUNT) {
1146 PRINTD (DBG_TX|DBG_BUS, "(simple or last multi)");
1147 if (!dev->tx_iovec) {
1148 // end of last region
1149 append_desc = 1;
1150 }
1151 dev->tx_bytes = 0;
1152 } else {
1153 PRINTD (DBG_TX|DBG_BUS, "(continuing multi)");
1154 dev->tx_bytes = tx_bytes - MAX_TRANSFER_COUNT;
1155 tx_bytes = MAX_TRANSFER_COUNT;
1156 }
1157 } else {
1158 // tx_bytes == 0 -- we're between regions
1159 // regions remaining to transfer
1160 unsigned int tx_regions = dev->tx_regions;
1161
1162 if (tx_regions) {
1163 // start a new region
1164 dev->tx_addr = dev->tx_iovec->iov_base;
1165 tx_bytes = dev->tx_iovec->iov_len;
1166 ++dev->tx_iovec;
1167 dev->tx_regions = tx_regions - 1;
1168
1169 if (!test_bit (ultra, &dev->flags) || tx_bytes <= MAX_PIO_COUNT) {
1170 PRINTD (DBG_TX|DBG_BUS, "(pio)");
1171 pio_instead = 1;
1172 }
1173 if (tx_bytes <= MAX_TRANSFER_COUNT) {
1174 PRINTD (DBG_TX|DBG_BUS, "(full region)");
1175 dev->tx_bytes = 0;
1176 } else {
1177 PRINTD (DBG_TX|DBG_BUS, "(start multi region)");
1178 dev->tx_bytes = tx_bytes - MAX_TRANSFER_COUNT;
1179 tx_bytes = MAX_TRANSFER_COUNT;
1180 }
1181 } else {
1182 // tx_regions == 0
1183 // that's all folks - end of frame
1184 struct sk_buff * skb = dev->tx_skb;
1185 dev->tx_iovec = NULL;
1186
1187 // VC layer stats
1188 atomic_inc(&ATM_SKB(skb)->vcc->stats->tx);
1189
1190 // free the skb
1191 hrz_kfree_skb (skb);
1192 }
1193 }
1194
1195 // note: writing TX_COUNT clears any interrupt condition
1196 if (tx_bytes) {
1197 if (pio_instead) {
1198 if (irq)
1199 wr_regl (dev, MASTER_TX_COUNT_REG_OFF, 0);
1200 wrs_regb (dev, DATA_PORT_OFF, dev->tx_addr, tx_bytes);
1201 if (append_desc)
1202 wr_regl (dev, TX_DESCRIPTOR_PORT_OFF, cpu_to_be32 (dev->tx_skb->len));
1203 } else {
1204 wr_regl (dev, MASTER_TX_ADDR_REG_OFF, virt_to_bus (dev->tx_addr));
1205 if (append_desc)
1206 wr_regl (dev, TX_DESCRIPTOR_REG_OFF, cpu_to_be32 (dev->tx_skb->len));
1207 wr_regl (dev, MASTER_TX_COUNT_REG_OFF,
1208 append_desc
1209 ? tx_bytes | MASTER_TX_AUTO_APPEND_DESC
1210 : tx_bytes);
1211 }
1212 dev->tx_addr += tx_bytes;
1213 } else {
1214 if (irq)
1215 wr_regl (dev, MASTER_TX_COUNT_REG_OFF, 0);
1216 YELLOW_LED_ON(dev);
1217 tx_release (dev);
1218 }
1219
1220#ifdef TAILRECURSIONWORKS
1221 // and we all bless optimised tail calls
1222 if (pio_instead)
1223 return tx_schedule (dev, 0);
1224 return;
1225#else
1226 // grrrrrrr!
1227 irq = 0;
1228 }
1229 return;
1230#endif
1231}
1232
1233/********** handle TX bus master complete events **********/
1234
1235static inline void tx_bus_master_complete_handler (hrz_dev * dev) {
1236 if (test_bit (tx_busy, &dev->flags)) {
1237 tx_schedule (dev, 1);
1238 } else {
1239 PRINTD (DBG_TX|DBG_ERR, "unexpected TX bus master completion");
1240 // clear interrupt condition on adapter
1241 wr_regl (dev, MASTER_TX_COUNT_REG_OFF, 0);
1242 }
1243 return;
1244}
1245
1246/********** move RX Q pointer to next item in circular buffer **********/
1247
1248// called only from IRQ sub-handler
1249static inline u32 rx_queue_entry_next (hrz_dev * dev) {
1250 u32 rx_queue_entry;
1251 spin_lock (&dev->mem_lock);
1252 rx_queue_entry = rd_mem (dev, &dev->rx_q_entry->entry);
1253 if (dev->rx_q_entry == dev->rx_q_wrap)
1254 dev->rx_q_entry = dev->rx_q_reset;
1255 else
1256 dev->rx_q_entry++;
1257 wr_regw (dev, RX_QUEUE_RD_PTR_OFF, dev->rx_q_entry - dev->rx_q_reset);
1258 spin_unlock (&dev->mem_lock);
1259 return rx_queue_entry;
1260}
1261
1262/********** handle RX disabled by device **********/
1263
1264static inline void rx_disabled_handler (hrz_dev * dev) {
1265 wr_regw (dev, RX_CONFIG_OFF, rd_regw (dev, RX_CONFIG_OFF) | RX_ENABLE);
1266 // count me please
1267 PRINTK (KERN_WARNING, "RX was disabled!");
1268}
1269
1270/********** handle RX data received by device **********/
1271
1272// called from IRQ handler
1273static inline void rx_data_av_handler (hrz_dev * dev) {
1274 u32 rx_queue_entry;
1275 u32 rx_queue_entry_flags;
1276 u16 rx_len;
1277 u16 rx_channel;
1278
1279 PRINTD (DBG_FLOW, "hrz_data_av_handler");
1280
1281 // try to grab rx lock (not possible during RX bus mastering)
1282 if (test_and_set_bit (rx_busy, &dev->flags)) {
1283 PRINTD (DBG_RX, "locked out of rx lock");
1284 return;
1285 }
1286 PRINTD (DBG_RX, "set rx_busy for dev %p", dev);
1287 // lock is cleared if we fail now, o/w after bus master completion
1288
1289 YELLOW_LED_OFF(dev);
1290
1291 rx_queue_entry = rx_queue_entry_next (dev);
1292
1293 rx_len = rx_q_entry_to_length (rx_queue_entry);
1294 rx_channel = rx_q_entry_to_rx_channel (rx_queue_entry);
1295
1296 WAIT_FLUSH_RX_COMPLETE (dev);
1297
1298 SELECT_RX_CHANNEL (dev, rx_channel);
1299
1300 PRINTD (DBG_RX, "rx_queue_entry is: %#x", rx_queue_entry);
1301 rx_queue_entry_flags = rx_queue_entry & (RX_CRC_32_OK|RX_COMPLETE_FRAME|SIMONS_DODGEY_MARKER);
1302
1303 if (!rx_len) {
1304 // (at least) bus-mastering breaks if we try to handle a
1305 // zero-length frame, besides AAL5 does not support them
1306 PRINTK (KERN_ERR, "zero-length frame!");
1307 rx_queue_entry_flags &= ~RX_COMPLETE_FRAME;
1308 }
1309
1310 if (rx_queue_entry_flags & SIMONS_DODGEY_MARKER) {
1311 PRINTD (DBG_RX|DBG_ERR, "Simon's marker detected!");
1312 }
1313 if (rx_queue_entry_flags == (RX_CRC_32_OK | RX_COMPLETE_FRAME)) {
1314 struct atm_vcc * atm_vcc;
1315
1316 PRINTD (DBG_RX, "got a frame on rx_channel %x len %u", rx_channel, rx_len);
1317
1318 atm_vcc = dev->rxer[rx_channel];
1319 // if no vcc is assigned to this channel, we should drop the frame
1320 // (is this what SIMONS etc. was trying to achieve?)
1321
1322 if (atm_vcc) {
1323
1324 if (atm_vcc->qos.rxtp.traffic_class != ATM_NONE) {
1325
1326 if (rx_len <= atm_vcc->qos.rxtp.max_sdu) {
1327
1328 struct sk_buff * skb = atm_alloc_charge (atm_vcc, rx_len, GFP_ATOMIC);
1329 if (skb) {
1330 // remember this so we can push it later
1331 dev->rx_skb = skb;
1332 // remember this so we can flush it later
1333 dev->rx_channel = rx_channel;
1334
1335 // prepare socket buffer
1336 skb_put (skb, rx_len);
1337 ATM_SKB(skb)->vcc = atm_vcc;
1338
1339 // simple transfer
1340 // dev->rx_regions = 0;
1341 // dev->rx_iovec = 0;
1342 dev->rx_bytes = rx_len;
1343 dev->rx_addr = skb->data;
1344 PRINTD (DBG_RX, "RX start simple transfer (addr %p, len %d)",
1345 skb->data, rx_len);
1346
1347 // do the business
1348 rx_schedule (dev, 0);
1349 return;
1350
1351 } else {
1352 PRINTD (DBG_SKB|DBG_WARN, "failed to get skb");
1353 }
1354
1355 } else {
1356 PRINTK (KERN_INFO, "frame received on TX-only VC %x", rx_channel);
1357 // do we count this?
1358 }
1359
1360 } else {
1361 PRINTK (KERN_WARNING, "dropped over-size frame");
1362 // do we count this?
1363 }
1364
1365 } else {
1366 PRINTD (DBG_WARN|DBG_VCC|DBG_RX, "no VCC for this frame (VC closed)");
1367 // do we count this?
1368 }
1369
1370 } else {
1371 // Wait update complete ? SPONG
1372 }
1373
1374 // RX was aborted
1375 YELLOW_LED_ON(dev);
1376
1377 FLUSH_RX_CHANNEL (dev,rx_channel);
1378 clear_bit (rx_busy, &dev->flags);
1379
1380 return;
1381}
1382
1383/********** interrupt handler **********/
1384
1385static irqreturn_t interrupt_handler(int irq, void *dev_id,
1386 struct pt_regs *pt_regs) {
1387 hrz_dev * dev = (hrz_dev *) dev_id;
1388 u32 int_source;
1389 unsigned int irq_ok;
1390 (void) pt_regs;
1391
1392 PRINTD (DBG_FLOW, "interrupt_handler: %p", dev_id);
1393
1394 if (!dev_id) {
1395 PRINTD (DBG_IRQ|DBG_ERR, "irq with NULL dev_id: %d", irq);
1396 return IRQ_NONE;
1397 }
1398 if (irq != dev->irq) {
1399 PRINTD (DBG_IRQ|DBG_ERR, "irq mismatch: %d", irq);
1400 return IRQ_NONE;
1401 }
1402
1403 // definitely for us
1404 irq_ok = 0;
1405 while ((int_source = rd_regl (dev, INT_SOURCE_REG_OFF)
1406 & INTERESTING_INTERRUPTS)) {
1407 // In the interests of fairness, the (inline) handlers below are
1408 // called in sequence and without immediate return to the head of
1409 // the while loop. This is only of issue for slow hosts (or when
1410 // debugging messages are on). Really slow hosts may find a fast
1411 // sender keeps them permanently in the IRQ handler. :(
1412
1413 // (only an issue for slow hosts) RX completion goes before
1414 // rx_data_av as the former implies rx_busy and so the latter
1415 // would just abort. If it reschedules another transfer
1416 // (continuing the same frame) then it will not clear rx_busy.
1417
1418 // (only an issue for slow hosts) TX completion goes before RX
1419 // data available as it is a much shorter routine - there is the
1420 // chance that any further transfers it schedules will be complete
1421 // by the time of the return to the head of the while loop
1422
1423 if (int_source & RX_BUS_MASTER_COMPLETE) {
1424 ++irq_ok;
1425 PRINTD (DBG_IRQ|DBG_BUS|DBG_RX, "rx_bus_master_complete asserted");
1426 rx_bus_master_complete_handler (dev);
1427 }
1428 if (int_source & TX_BUS_MASTER_COMPLETE) {
1429 ++irq_ok;
1430 PRINTD (DBG_IRQ|DBG_BUS|DBG_TX, "tx_bus_master_complete asserted");
1431 tx_bus_master_complete_handler (dev);
1432 }
1433 if (int_source & RX_DATA_AV) {
1434 ++irq_ok;
1435 PRINTD (DBG_IRQ|DBG_RX, "rx_data_av asserted");
1436 rx_data_av_handler (dev);
1437 }
1438 }
1439 if (irq_ok) {
1440 PRINTD (DBG_IRQ, "work done: %u", irq_ok);
1441 } else {
1442 PRINTD (DBG_IRQ|DBG_WARN, "spurious interrupt source: %#x", int_source);
1443 }
1444
1445 PRINTD (DBG_IRQ|DBG_FLOW, "interrupt_handler done: %p", dev_id);
1446 if (irq_ok)
1447 return IRQ_HANDLED;
1448 return IRQ_NONE;
1449}
1450
1451/********** housekeeping **********/
1452
1453static void do_housekeeping (unsigned long arg) {
1454 // just stats at the moment
1455 hrz_dev * dev = (hrz_dev *) arg;
1456
1457 // collect device-specific (not driver/atm-linux) stats here
1458 dev->tx_cell_count += rd_regw (dev, TX_CELL_COUNT_OFF);
1459 dev->rx_cell_count += rd_regw (dev, RX_CELL_COUNT_OFF);
1460 dev->hec_error_count += rd_regw (dev, HEC_ERROR_COUNT_OFF);
1461 dev->unassigned_cell_count += rd_regw (dev, UNASSIGNED_CELL_COUNT_OFF);
1462
1463 mod_timer (&dev->housekeeping, jiffies + HZ/10);
1464
1465 return;
1466}
1467
1468/********** find an idle channel for TX and set it up **********/
1469
1470// called with tx_busy set
1471static inline short setup_idle_tx_channel (hrz_dev * dev, hrz_vcc * vcc) {
1472 unsigned short idle_channels;
1473 short tx_channel = -1;
1474 unsigned int spin_count;
1475 PRINTD (DBG_FLOW|DBG_TX, "setup_idle_tx_channel %p", dev);
1476
1477 // better would be to fail immediately, the caller can then decide whether
1478 // to wait or drop (depending on whether this is UBR etc.)
1479 spin_count = 0;
1480 while (!(idle_channels = rd_regw (dev, TX_STATUS_OFF) & IDLE_CHANNELS_MASK)) {
1481 PRINTD (DBG_TX|DBG_WARN, "waiting for idle TX channel");
1482 // delay a bit here
1483 if (++spin_count > 100) {
1484 PRINTD (DBG_TX|DBG_ERR, "spun out waiting for idle TX channel");
1485 return -EBUSY;
1486 }
1487 }
1488
1489 // got an idle channel
1490 {
1491 // tx_idle ensures we look for idle channels in RR order
1492 int chan = dev->tx_idle;
1493
1494 int keep_going = 1;
1495 while (keep_going) {
1496 if (idle_channels & (1<<chan)) {
1497 tx_channel = chan;
1498 keep_going = 0;
1499 }
1500 ++chan;
1501 if (chan == TX_CHANS)
1502 chan = 0;
1503 }
1504
1505 dev->tx_idle = chan;
1506 }
1507
1508 // set up the channel we found
1509 {
1510 // Initialise the cell header in the transmit channel descriptor
1511 // a.k.a. prepare the channel and remember that we have done so.
1512
1513 tx_ch_desc * tx_desc = &memmap->tx_descs[tx_channel];
1514 u16 rd_ptr;
1515 u16 wr_ptr;
1516 u16 channel = vcc->channel;
1517
1518 unsigned long flags;
1519 spin_lock_irqsave (&dev->mem_lock, flags);
1520
1521 // Update the transmit channel record.
1522 dev->tx_channel_record[tx_channel] = channel;
1523
1524 // xBR channel
1525 update_tx_channel_config (dev, tx_channel, RATE_TYPE_ACCESS,
1526 vcc->tx_xbr_bits);
1527
1528 // Update the PCR counter preload value etc.
1529 update_tx_channel_config (dev, tx_channel, PCR_TIMER_ACCESS,
1530 vcc->tx_pcr_bits);
1531
1532#if 0
1533 if (vcc->tx_xbr_bits == VBR_RATE_TYPE) {
1534 // SCR timer
1535 update_tx_channel_config (dev, tx_channel, SCR_TIMER_ACCESS,
1536 vcc->tx_scr_bits);
1537
1538 // Bucket size...
1539 update_tx_channel_config (dev, tx_channel, BUCKET_CAPACITY_ACCESS,
1540 vcc->tx_bucket_bits);
1541
1542 // ... and fullness
1543 update_tx_channel_config (dev, tx_channel, BUCKET_FULLNESS_ACCESS,
1544 vcc->tx_bucket_bits);
1545 }
1546#endif
1547
1548 // Initialise the read and write buffer pointers
1549 rd_ptr = rd_mem (dev, &tx_desc->rd_buf_type) & BUFFER_PTR_MASK;
1550 wr_ptr = rd_mem (dev, &tx_desc->wr_buf_type) & BUFFER_PTR_MASK;
1551
1552 // idle TX channels should have identical pointers
1553 if (rd_ptr != wr_ptr) {
1554 PRINTD (DBG_TX|DBG_ERR, "TX buffer pointers are broken!");
1555 // spin_unlock... return -E...
1556 // I wonder if gcc would get rid of one of the pointer aliases
1557 }
1558 PRINTD (DBG_TX, "TX buffer pointers are: rd %x, wr %x.",
1559 rd_ptr, wr_ptr);
1560
1561 switch (vcc->aal) {
1562 case aal0:
1563 PRINTD (DBG_QOS|DBG_TX, "tx_channel: aal0");
1564 rd_ptr |= CHANNEL_TYPE_RAW_CELLS;
1565 wr_ptr |= CHANNEL_TYPE_RAW_CELLS;
1566 break;
1567 case aal34:
1568 PRINTD (DBG_QOS|DBG_TX, "tx_channel: aal34");
1569 rd_ptr |= CHANNEL_TYPE_AAL3_4;
1570 wr_ptr |= CHANNEL_TYPE_AAL3_4;
1571 break;
1572 case aal5:
1573 rd_ptr |= CHANNEL_TYPE_AAL5;
1574 wr_ptr |= CHANNEL_TYPE_AAL5;
1575 // Initialise the CRC
1576 wr_mem (dev, &tx_desc->partial_crc, INITIAL_CRC);
1577 break;
1578 }
1579
1580 wr_mem (dev, &tx_desc->rd_buf_type, rd_ptr);
1581 wr_mem (dev, &tx_desc->wr_buf_type, wr_ptr);
1582
1583 // Write the Cell Header
1584 // Payload Type, CLP and GFC would go here if non-zero
1585 wr_mem (dev, &tx_desc->cell_header, channel);
1586
1587 spin_unlock_irqrestore (&dev->mem_lock, flags);
1588 }
1589
1590 return tx_channel;
1591}
1592
1593/********** send a frame **********/
1594
1595static int hrz_send (struct atm_vcc * atm_vcc, struct sk_buff * skb) {
1596 unsigned int spin_count;
1597 int free_buffers;
1598 hrz_dev * dev = HRZ_DEV(atm_vcc->dev);
1599 hrz_vcc * vcc = HRZ_VCC(atm_vcc);
1600 u16 channel = vcc->channel;
1601
1602 u32 buffers_required;
1603
1604 /* signed for error return */
1605 short tx_channel;
1606
1607 PRINTD (DBG_FLOW|DBG_TX, "hrz_send vc %x data %p len %u",
1608 channel, skb->data, skb->len);
1609
1610 dump_skb (">>>", channel, skb);
1611
1612 if (atm_vcc->qos.txtp.traffic_class == ATM_NONE) {
1613 PRINTK (KERN_ERR, "attempt to send on RX-only VC %x", channel);
1614 hrz_kfree_skb (skb);
1615 return -EIO;
1616 }
1617
1618 // don't understand this
1619 ATM_SKB(skb)->vcc = atm_vcc;
1620
1621 if (skb->len > atm_vcc->qos.txtp.max_sdu) {
1622 PRINTK (KERN_ERR, "sk_buff length greater than agreed max_sdu, dropping...");
1623 hrz_kfree_skb (skb);
1624 return -EIO;
1625 }
1626
1627 if (!channel) {
1628 PRINTD (DBG_ERR|DBG_TX, "attempt to transmit on zero (rx_)channel");
1629 hrz_kfree_skb (skb);
1630 return -EIO;
1631 }
1632
1633#if 0
1634 {
1635 // where would be a better place for this? housekeeping?
1636 u16 status;
1637 pci_read_config_word (dev->pci_dev, PCI_STATUS, &status);
1638 if (status & PCI_STATUS_REC_MASTER_ABORT) {
1639 PRINTD (DBG_BUS|DBG_ERR, "Clearing PCI Master Abort (and cleaning up)");
1640 status &= ~PCI_STATUS_REC_MASTER_ABORT;
1641 pci_write_config_word (dev->pci_dev, PCI_STATUS, status);
1642 if (test_bit (tx_busy, &dev->flags)) {
1643 hrz_kfree_skb (dev->tx_skb);
1644 tx_release (dev);
1645 }
1646 }
1647 }
1648#endif
1649
1650#ifdef DEBUG_HORIZON
1651 /* wey-hey! */
1652 if (channel == 1023) {
1653 unsigned int i;
1654 unsigned short d = 0;
1655 char * s = skb->data;
1656 if (*s++ == 'D') {
1657 for (i = 0; i < 4; ++i) {
1658 d = (d<<4) | ((*s <= '9') ? (*s - '0') : (*s - 'a' + 10));
1659 ++s;
1660 }
1661 PRINTK (KERN_INFO, "debug bitmap is now %hx", debug = d);
1662 }
1663 }
1664#endif
1665
1666 // wait until TX is free and grab lock
1667 if (tx_hold (dev)) {
1668 hrz_kfree_skb (skb);
1669 return -ERESTARTSYS;
1670 }
1671
1672 // Wait for enough space to be available in transmit buffer memory.
1673
1674 // should be number of cells needed + 2 (according to hardware docs)
1675 // = ((framelen+8)+47) / 48 + 2
1676 // = (framelen+7) / 48 + 3, hmm... faster to put addition inside XXX
1677 buffers_required = (skb->len+(ATM_AAL5_TRAILER-1)) / ATM_CELL_PAYLOAD + 3;
1678
1679 // replace with timer and sleep, add dev->tx_buffers_queue (max 1 entry)
1680 spin_count = 0;
1681 while ((free_buffers = rd_regw (dev, TX_FREE_BUFFER_COUNT_OFF)) < buffers_required) {
1682 PRINTD (DBG_TX, "waiting for free TX buffers, got %d of %d",
1683 free_buffers, buffers_required);
1684 // what is the appropriate delay? implement a timeout? (depending on line speed?)
1685 // mdelay (1);
1686 // what happens if we kill (current_pid, SIGKILL) ?
1687 schedule();
1688 if (++spin_count > 1000) {
1689 PRINTD (DBG_TX|DBG_ERR, "spun out waiting for tx buffers, got %d of %d",
1690 free_buffers, buffers_required);
1691 tx_release (dev);
1692 hrz_kfree_skb (skb);
1693 return -ERESTARTSYS;
1694 }
1695 }
1696
1697 // Select a channel to transmit the frame on.
1698 if (channel == dev->last_vc) {
1699 PRINTD (DBG_TX, "last vc hack: hit");
1700 tx_channel = dev->tx_last;
1701 } else {
1702 PRINTD (DBG_TX, "last vc hack: miss");
1703 // Are we currently transmitting this VC on one of the channels?
1704 for (tx_channel = 0; tx_channel < TX_CHANS; ++tx_channel)
1705 if (dev->tx_channel_record[tx_channel] == channel) {
1706 PRINTD (DBG_TX, "vc already on channel: hit");
1707 break;
1708 }
1709 if (tx_channel == TX_CHANS) {
1710 PRINTD (DBG_TX, "vc already on channel: miss");
1711 // Find and set up an idle channel.
1712 tx_channel = setup_idle_tx_channel (dev, vcc);
1713 if (tx_channel < 0) {
1714 PRINTD (DBG_TX|DBG_ERR, "failed to get channel");
1715 tx_release (dev);
1716 return tx_channel;
1717 }
1718 }
1719
1720 PRINTD (DBG_TX, "got channel");
1721 SELECT_TX_CHANNEL(dev, tx_channel);
1722
1723 dev->last_vc = channel;
1724 dev->tx_last = tx_channel;
1725 }
1726
1727 PRINTD (DBG_TX, "using channel %u", tx_channel);
1728
1729 YELLOW_LED_OFF(dev);
1730
1731 // TX start transfer
1732
1733 {
1734 unsigned int tx_len = skb->len;
1735 unsigned int tx_iovcnt = skb_shinfo(skb)->nr_frags;
1736 // remember this so we can free it later
1737 dev->tx_skb = skb;
1738
1739 if (tx_iovcnt) {
1740 // scatter gather transfer
1741 dev->tx_regions = tx_iovcnt;
1742 dev->tx_iovec = NULL; /* @@@ needs rewritten */
1743 dev->tx_bytes = 0;
1744 PRINTD (DBG_TX|DBG_BUS, "TX start scatter-gather transfer (iovec %p, len %d)",
1745 skb->data, tx_len);
1746 tx_release (dev);
1747 hrz_kfree_skb (skb);
1748 return -EIO;
1749 } else {
1750 // simple transfer
1751 dev->tx_regions = 0;
1752 dev->tx_iovec = NULL;
1753 dev->tx_bytes = tx_len;
1754 dev->tx_addr = skb->data;
1755 PRINTD (DBG_TX|DBG_BUS, "TX start simple transfer (addr %p, len %d)",
1756 skb->data, tx_len);
1757 }
1758
1759 // and do the business
1760 tx_schedule (dev, 0);
1761
1762 }
1763
1764 return 0;
1765}
1766
1767/********** reset a card **********/
1768
1769static void hrz_reset (const hrz_dev * dev) {
1770 u32 control_0_reg = rd_regl (dev, CONTROL_0_REG);
1771
1772 // why not set RESET_HORIZON to one and wait for the card to
1773 // reassert that bit as zero? Like so:
1774 control_0_reg = control_0_reg & RESET_HORIZON;
1775 wr_regl (dev, CONTROL_0_REG, control_0_reg);
1776 while (control_0_reg & RESET_HORIZON)
1777 control_0_reg = rd_regl (dev, CONTROL_0_REG);
1778
1779 // old reset code retained:
1780 wr_regl (dev, CONTROL_0_REG, control_0_reg |
1781 RESET_ATM | RESET_RX | RESET_TX | RESET_HOST);
1782 // just guessing here
1783 udelay (1000);
1784
1785 wr_regl (dev, CONTROL_0_REG, control_0_reg);
1786}
1787
1788/********** read the burnt in address **********/
1789
1790static inline void WRITE_IT_WAIT (const hrz_dev *dev, u32 ctrl)
1791{
1792 wr_regl (dev, CONTROL_0_REG, ctrl);
1793 udelay (5);
1794}
1795
1796static inline void CLOCK_IT (const hrz_dev *dev, u32 ctrl)
1797{
1798 // DI must be valid around rising SK edge
1799 WRITE_IT_WAIT(dev, ctrl & ~SEEPROM_SK);
1800 WRITE_IT_WAIT(dev, ctrl | SEEPROM_SK);
1801}
1802
1803static u16 __init read_bia (const hrz_dev * dev, u16 addr)
1804{
1805 u32 ctrl = rd_regl (dev, CONTROL_0_REG);
1806
1807 const unsigned int addr_bits = 6;
1808 const unsigned int data_bits = 16;
1809
1810 unsigned int i;
1811
1812 u16 res;
1813
1814 ctrl &= ~(SEEPROM_CS | SEEPROM_SK | SEEPROM_DI);
1815 WRITE_IT_WAIT(dev, ctrl);
1816
1817 // wake Serial EEPROM and send 110 (READ) command
1818 ctrl |= (SEEPROM_CS | SEEPROM_DI);
1819 CLOCK_IT(dev, ctrl);
1820
1821 ctrl |= SEEPROM_DI;
1822 CLOCK_IT(dev, ctrl);
1823
1824 ctrl &= ~SEEPROM_DI;
1825 CLOCK_IT(dev, ctrl);
1826
1827 for (i=0; i<addr_bits; i++) {
1828 if (addr & (1 << (addr_bits-1)))
1829 ctrl |= SEEPROM_DI;
1830 else
1831 ctrl &= ~SEEPROM_DI;
1832
1833 CLOCK_IT(dev, ctrl);
1834
1835 addr = addr << 1;
1836 }
1837
1838 // we could check that we have DO = 0 here
1839 ctrl &= ~SEEPROM_DI;
1840
1841 res = 0;
1842 for (i=0;i<data_bits;i++) {
1843 res = res >> 1;
1844
1845 CLOCK_IT(dev, ctrl);
1846
1847 if (rd_regl (dev, CONTROL_0_REG) & SEEPROM_DO)
1848 res |= (1 << (data_bits-1));
1849 }
1850
1851 ctrl &= ~(SEEPROM_SK | SEEPROM_CS);
1852 WRITE_IT_WAIT(dev, ctrl);
1853
1854 return res;
1855}
1856
1857/********** initialise a card **********/
1858
1859static int __init hrz_init (hrz_dev * dev) {
1860 int onefivefive;
1861
1862 u16 chan;
1863
1864 int buff_count;
1865
1866 HDW * mem;
1867
1868 cell_buf * tx_desc;
1869 cell_buf * rx_desc;
1870
1871 u32 ctrl;
1872
1873 ctrl = rd_regl (dev, CONTROL_0_REG);
1874 PRINTD (DBG_INFO, "ctrl0reg is %#x", ctrl);
1875 onefivefive = ctrl & ATM_LAYER_STATUS;
1876
1877 if (onefivefive)
1878 printk (DEV_LABEL ": Horizon Ultra (at 155.52 MBps)");
1879 else
1880 printk (DEV_LABEL ": Horizon (at 25 MBps)");
1881
1882 printk (":");
1883 // Reset the card to get everything in a known state
1884
1885 printk (" reset");
1886 hrz_reset (dev);
1887
1888 // Clear all the buffer memory
1889
1890 printk (" clearing memory");
1891
1892 for (mem = (HDW *) memmap; mem < (HDW *) (memmap + 1); ++mem)
1893 wr_mem (dev, mem, 0);
1894
1895 printk (" tx channels");
1896
1897 // All transmit eight channels are set up as AAL5 ABR channels with
1898 // a 16us cell spacing. Why?
1899
1900 // Channel 0 gets the free buffer at 100h, channel 1 gets the free
1901 // buffer at 110h etc.
1902
1903 for (chan = 0; chan < TX_CHANS; ++chan) {
1904 tx_ch_desc * tx_desc = &memmap->tx_descs[chan];
1905 cell_buf * buf = &memmap->inittxbufs[chan];
1906
1907 // initialise the read and write buffer pointers
1908 wr_mem (dev, &tx_desc->rd_buf_type, BUF_PTR(buf));
1909 wr_mem (dev, &tx_desc->wr_buf_type, BUF_PTR(buf));
1910
1911 // set the status of the initial buffers to empty
1912 wr_mem (dev, &buf->next, BUFF_STATUS_EMPTY);
1913 }
1914
1915 // Use space bufn3 at the moment for tx buffers
1916
1917 printk (" tx buffers");
1918
1919 tx_desc = memmap->bufn3;
1920
1921 wr_mem (dev, &memmap->txfreebufstart.next, BUF_PTR(tx_desc) | BUFF_STATUS_EMPTY);
1922
1923 for (buff_count = 0; buff_count < BUFN3_SIZE-1; buff_count++) {
1924 wr_mem (dev, &tx_desc->next, BUF_PTR(tx_desc+1) | BUFF_STATUS_EMPTY);
1925 tx_desc++;
1926 }
1927
1928 wr_mem (dev, &tx_desc->next, BUF_PTR(&memmap->txfreebufend) | BUFF_STATUS_EMPTY);
1929
1930 // Initialise the transmit free buffer count
1931 wr_regw (dev, TX_FREE_BUFFER_COUNT_OFF, BUFN3_SIZE);
1932
1933 printk (" rx channels");
1934
1935 // Initialise all of the receive channels to be AAL5 disabled with
1936 // an interrupt threshold of 0
1937
1938 for (chan = 0; chan < RX_CHANS; ++chan) {
1939 rx_ch_desc * rx_desc = &memmap->rx_descs[chan];
1940
1941 wr_mem (dev, &rx_desc->wr_buf_type, CHANNEL_TYPE_AAL5 | RX_CHANNEL_DISABLED);
1942 }
1943
1944 printk (" rx buffers");
1945
1946 // Use space bufn4 at the moment for rx buffers
1947
1948 rx_desc = memmap->bufn4;
1949
1950 wr_mem (dev, &memmap->rxfreebufstart.next, BUF_PTR(rx_desc) | BUFF_STATUS_EMPTY);
1951
1952 for (buff_count = 0; buff_count < BUFN4_SIZE-1; buff_count++) {
1953 wr_mem (dev, &rx_desc->next, BUF_PTR(rx_desc+1) | BUFF_STATUS_EMPTY);
1954
1955 rx_desc++;
1956 }
1957
1958 wr_mem (dev, &rx_desc->next, BUF_PTR(&memmap->rxfreebufend) | BUFF_STATUS_EMPTY);
1959
1960 // Initialise the receive free buffer count
1961 wr_regw (dev, RX_FREE_BUFFER_COUNT_OFF, BUFN4_SIZE);
1962
1963 // Initialize Horizons registers
1964
1965 // TX config
1966 wr_regw (dev, TX_CONFIG_OFF,
1967 ABR_ROUND_ROBIN | TX_NORMAL_OPERATION | DRVR_DRVRBAR_ENABLE);
1968
1969 // RX config. Use 10-x VC bits, x VP bits, non user cells in channel 0.
1970 wr_regw (dev, RX_CONFIG_OFF,
1971 DISCARD_UNUSED_VPI_VCI_BITS_SET | NON_USER_CELLS_IN_ONE_CHANNEL | vpi_bits);
1972
1973 // RX line config
1974 wr_regw (dev, RX_LINE_CONFIG_OFF,
1975 LOCK_DETECT_ENABLE | FREQUENCY_DETECT_ENABLE | GXTALOUT_SELECT_DIV4);
1976
1977 // Set the max AAL5 cell count to be just enough to contain the
1978 // largest AAL5 frame that the user wants to receive
1979 wr_regw (dev, MAX_AAL5_CELL_COUNT_OFF,
1980 (max_rx_size + ATM_AAL5_TRAILER + ATM_CELL_PAYLOAD - 1) / ATM_CELL_PAYLOAD);
1981
1982 // Enable receive
1983 wr_regw (dev, RX_CONFIG_OFF, rd_regw (dev, RX_CONFIG_OFF) | RX_ENABLE);
1984
1985 printk (" control");
1986
1987 // Drive the OE of the LEDs then turn the green LED on
1988 ctrl |= GREEN_LED_OE | YELLOW_LED_OE | GREEN_LED | YELLOW_LED;
1989 wr_regl (dev, CONTROL_0_REG, ctrl);
1990
1991 // Test for a 155-capable card
1992
1993 if (onefivefive) {
1994 // Select 155 mode... make this a choice (or: how do we detect
1995 // external line speed and switch?)
1996 ctrl |= ATM_LAYER_SELECT;
1997 wr_regl (dev, CONTROL_0_REG, ctrl);
1998
1999 // test SUNI-lite vs SAMBA
2000
2001 // Register 0x00 in the SUNI will have some of bits 3-7 set, and
2002 // they will always be zero for the SAMBA. Ha! Bloody hardware
2003 // engineers. It'll never work.
2004
2005 if (rd_framer (dev, 0) & 0x00f0) {
2006 // SUNI
2007 printk (" SUNI");
2008
2009 // Reset, just in case
2010 wr_framer (dev, 0x00, 0x0080);
2011 wr_framer (dev, 0x00, 0x0000);
2012
2013 // Configure transmit FIFO
2014 wr_framer (dev, 0x63, rd_framer (dev, 0x63) | 0x0002);
2015
2016 // Set line timed mode
2017 wr_framer (dev, 0x05, rd_framer (dev, 0x05) | 0x0001);
2018 } else {
2019 // SAMBA
2020 printk (" SAMBA");
2021
2022 // Reset, just in case
2023 wr_framer (dev, 0, rd_framer (dev, 0) | 0x0001);
2024 wr_framer (dev, 0, rd_framer (dev, 0) &~ 0x0001);
2025
2026 // Turn off diagnostic loopback and enable line-timed mode
2027 wr_framer (dev, 0, 0x0002);
2028
2029 // Turn on transmit outputs
2030 wr_framer (dev, 2, 0x0B80);
2031 }
2032 } else {
2033 // Select 25 mode
2034 ctrl &= ~ATM_LAYER_SELECT;
2035
2036 // Madge B154 setup
2037 // none required?
2038 }
2039
2040 printk (" LEDs");
2041
2042 GREEN_LED_ON(dev);
2043 YELLOW_LED_ON(dev);
2044
2045 printk (" ESI=");
2046
2047 {
2048 u16 b = 0;
2049 int i;
2050 u8 * esi = dev->atm_dev->esi;
2051
2052 // in the card I have, EEPROM
2053 // addresses 0, 1, 2 contain 0
2054 // addresess 5, 6 etc. contain ffff
2055 // NB: Madge prefix is 00 00 f6 (which is 00 00 6f in Ethernet bit order)
2056 // the read_bia routine gets the BIA in Ethernet bit order
2057
2058 for (i=0; i < ESI_LEN; ++i) {
2059 if (i % 2 == 0)
2060 b = read_bia (dev, i/2 + 2);
2061 else
2062 b = b >> 8;
2063 esi[i] = b & 0xFF;
2064 printk ("%02x", esi[i]);
2065 }
2066 }
2067
2068 // Enable RX_Q and ?X_COMPLETE interrupts only
2069 wr_regl (dev, INT_ENABLE_REG_OFF, INTERESTING_INTERRUPTS);
2070 printk (" IRQ on");
2071
2072 printk (".\n");
2073
2074 return onefivefive;
2075}
2076
2077/********** check max_sdu **********/
2078
2079static int check_max_sdu (hrz_aal aal, struct atm_trafprm * tp, unsigned int max_frame_size) {
2080 PRINTD (DBG_FLOW|DBG_QOS, "check_max_sdu");
2081
2082 switch (aal) {
2083 case aal0:
2084 if (!(tp->max_sdu)) {
2085 PRINTD (DBG_QOS, "defaulting max_sdu");
2086 tp->max_sdu = ATM_AAL0_SDU;
2087 } else if (tp->max_sdu != ATM_AAL0_SDU) {
2088 PRINTD (DBG_QOS|DBG_ERR, "rejecting max_sdu");
2089 return -EINVAL;
2090 }
2091 break;
2092 case aal34:
2093 if (tp->max_sdu == 0 || tp->max_sdu > ATM_MAX_AAL34_PDU) {
2094 PRINTD (DBG_QOS, "%sing max_sdu", tp->max_sdu ? "capp" : "default");
2095 tp->max_sdu = ATM_MAX_AAL34_PDU;
2096 }
2097 break;
2098 case aal5:
2099 if (tp->max_sdu == 0 || tp->max_sdu > max_frame_size) {
2100 PRINTD (DBG_QOS, "%sing max_sdu", tp->max_sdu ? "capp" : "default");
2101 tp->max_sdu = max_frame_size;
2102 }
2103 break;
2104 }
2105 return 0;
2106}
2107
2108/********** check pcr **********/
2109
2110// something like this should be part of ATM Linux
2111static int atm_pcr_check (struct atm_trafprm * tp, unsigned int pcr) {
2112 // we are assuming non-UBR, and non-special values of pcr
2113 if (tp->min_pcr == ATM_MAX_PCR)
2114 PRINTD (DBG_QOS, "luser gave min_pcr = ATM_MAX_PCR");
2115 else if (tp->min_pcr < 0)
2116 PRINTD (DBG_QOS, "luser gave negative min_pcr");
2117 else if (tp->min_pcr && tp->min_pcr > pcr)
2118 PRINTD (DBG_QOS, "pcr less than min_pcr");
2119 else
2120 // !! max_pcr = UNSPEC (0) is equivalent to max_pcr = MAX (-1)
2121 // easier to #define ATM_MAX_PCR 0 and have all rates unsigned?
2122 // [this would get rid of next two conditionals]
2123 if ((0) && tp->max_pcr == ATM_MAX_PCR)
2124 PRINTD (DBG_QOS, "luser gave max_pcr = ATM_MAX_PCR");
2125 else if ((tp->max_pcr != ATM_MAX_PCR) && tp->max_pcr < 0)
2126 PRINTD (DBG_QOS, "luser gave negative max_pcr");
2127 else if (tp->max_pcr && tp->max_pcr != ATM_MAX_PCR && tp->max_pcr < pcr)
2128 PRINTD (DBG_QOS, "pcr greater than max_pcr");
2129 else {
2130 // each limit unspecified or not violated
2131 PRINTD (DBG_QOS, "xBR(pcr) OK");
2132 return 0;
2133 }
2134 PRINTD (DBG_QOS, "pcr=%u, tp: min_pcr=%d, pcr=%d, max_pcr=%d",
2135 pcr, tp->min_pcr, tp->pcr, tp->max_pcr);
2136 return -EINVAL;
2137}
2138
2139/********** open VC **********/
2140
2141static int hrz_open (struct atm_vcc *atm_vcc)
2142{
2143 int error;
2144 u16 channel;
2145
2146 struct atm_qos * qos;
2147 struct atm_trafprm * txtp;
2148 struct atm_trafprm * rxtp;
2149
2150 hrz_dev * dev = HRZ_DEV(atm_vcc->dev);
2151 hrz_vcc vcc;
2152 hrz_vcc * vccp; // allocated late
2153 short vpi = atm_vcc->vpi;
2154 int vci = atm_vcc->vci;
2155 PRINTD (DBG_FLOW|DBG_VCC, "hrz_open %x %x", vpi, vci);
2156
2157#ifdef ATM_VPI_UNSPEC
2158 // UNSPEC is deprecated, remove this code eventually
2159 if (vpi == ATM_VPI_UNSPEC || vci == ATM_VCI_UNSPEC) {
2160 PRINTK (KERN_WARNING, "rejecting open with unspecified VPI/VCI (deprecated)");
2161 return -EINVAL;
2162 }
2163#endif
2164
2165 error = vpivci_to_channel (&channel, vpi, vci);
2166 if (error) {
2167 PRINTD (DBG_WARN|DBG_VCC, "VPI/VCI out of range: %hd/%d", vpi, vci);
2168 return error;
2169 }
2170
2171 vcc.channel = channel;
2172 // max speed for the moment
2173 vcc.tx_rate = 0x0;
2174
2175 qos = &atm_vcc->qos;
2176
2177 // check AAL and remember it
2178 switch (qos->aal) {
2179 case ATM_AAL0:
2180 // we would if it were 48 bytes and not 52!
2181 PRINTD (DBG_QOS|DBG_VCC, "AAL0");
2182 vcc.aal = aal0;
2183 break;
2184 case ATM_AAL34:
2185 // we would if I knew how do the SAR!
2186 PRINTD (DBG_QOS|DBG_VCC, "AAL3/4");
2187 vcc.aal = aal34;
2188 break;
2189 case ATM_AAL5:
2190 PRINTD (DBG_QOS|DBG_VCC, "AAL5");
2191 vcc.aal = aal5;
2192 break;
2193 default:
2194 PRINTD (DBG_QOS|DBG_VCC, "Bad AAL!");
2195 return -EINVAL;
2196 break;
2197 }
2198
2199 // TX traffic parameters
2200
2201 // there are two, interrelated problems here: 1. the reservation of
2202 // PCR is not a binary choice, we are given bounds and/or a
2203 // desirable value; 2. the device is only capable of certain values,
2204 // most of which are not integers. It is almost certainly acceptable
2205 // to be off by a maximum of 1 to 10 cps.
2206
2207 // Pragmatic choice: always store an integral PCR as that which has
2208 // been allocated, even if we allocate a little (or a lot) less,
2209 // after rounding. The actual allocation depends on what we can
2210 // manage with our rate selection algorithm. The rate selection
2211 // algorithm is given an integral PCR and a tolerance and told
2212 // whether it should round the value up or down if the tolerance is
2213 // exceeded; it returns: a) the actual rate selected (rounded up to
2214 // the nearest integer), b) a bit pattern to feed to the timer
2215 // register, and c) a failure value if no applicable rate exists.
2216
2217 // Part of the job is done by atm_pcr_goal which gives us a PCR
2218 // specification which says: EITHER grab the maximum available PCR
2219 // (and perhaps a lower bound which we musn't pass), OR grab this
2220 // amount, rounding down if you have to (and perhaps a lower bound
2221 // which we musn't pass) OR grab this amount, rounding up if you
2222 // have to (and perhaps an upper bound which we musn't pass). If any
2223 // bounds ARE passed we fail. Note that rounding is only rounding to
2224 // match device limitations, we do not round down to satisfy
2225 // bandwidth availability even if this would not violate any given
2226 // lower bound.
2227
2228 // Note: telephony = 64kb/s = 48 byte cell payload @ 500/3 cells/s
2229 // (say) so this is not even a binary fixpoint cell rate (but this
2230 // device can do it). To avoid this sort of hassle we use a
2231 // tolerance parameter (currently fixed at 10 cps).
2232
2233 PRINTD (DBG_QOS, "TX:");
2234
2235 txtp = &qos->txtp;
2236
2237 // set up defaults for no traffic
2238 vcc.tx_rate = 0;
2239 // who knows what would actually happen if you try and send on this?
2240 vcc.tx_xbr_bits = IDLE_RATE_TYPE;
2241 vcc.tx_pcr_bits = CLOCK_DISABLE;
2242#if 0
2243 vcc.tx_scr_bits = CLOCK_DISABLE;
2244 vcc.tx_bucket_bits = 0;
2245#endif
2246
2247 if (txtp->traffic_class != ATM_NONE) {
2248 error = check_max_sdu (vcc.aal, txtp, max_tx_size);
2249 if (error) {
2250 PRINTD (DBG_QOS, "TX max_sdu check failed");
2251 return error;
2252 }
2253
2254 switch (txtp->traffic_class) {
2255 case ATM_UBR: {
2256 // we take "the PCR" as a rate-cap
2257 // not reserved
2258 vcc.tx_rate = 0;
2259 make_rate (dev, 1<<30, round_nearest, &vcc.tx_pcr_bits, NULL);
2260 vcc.tx_xbr_bits = ABR_RATE_TYPE;
2261 break;
2262 }
2263#if 0
2264 case ATM_ABR: {
2265 // reserve min, allow up to max
2266 vcc.tx_rate = 0; // ?
2267 make_rate (dev, 1<<30, round_nearest, &vcc.tx_pcr_bits, 0);
2268 vcc.tx_xbr_bits = ABR_RATE_TYPE;
2269 break;
2270 }
2271#endif
2272 case ATM_CBR: {
2273 int pcr = atm_pcr_goal (txtp);
2274 rounding r;
2275 if (!pcr) {
2276 // down vs. up, remaining bandwidth vs. unlimited bandwidth!!
2277 // should really have: once someone gets unlimited bandwidth
2278 // that no more non-UBR channels can be opened until the
2279 // unlimited one closes?? For the moment, round_down means
2280 // greedy people actually get something and not nothing
2281 r = round_down;
2282 // slight race (no locking) here so we may get -EAGAIN
2283 // later; the greedy bastards would deserve it :)
2284 PRINTD (DBG_QOS, "snatching all remaining TX bandwidth");
2285 pcr = dev->tx_avail;
2286 } else if (pcr < 0) {
2287 r = round_down;
2288 pcr = -pcr;
2289 } else {
2290 r = round_up;
2291 }
2292 error = make_rate_with_tolerance (dev, pcr, r, 10,
2293 &vcc.tx_pcr_bits, &vcc.tx_rate);
2294 if (error) {
2295 PRINTD (DBG_QOS, "could not make rate from TX PCR");
2296 return error;
2297 }
2298 // not really clear what further checking is needed
2299 error = atm_pcr_check (txtp, vcc.tx_rate);
2300 if (error) {
2301 PRINTD (DBG_QOS, "TX PCR failed consistency check");
2302 return error;
2303 }
2304 vcc.tx_xbr_bits = CBR_RATE_TYPE;
2305 break;
2306 }
2307#if 0
2308 case ATM_VBR: {
2309 int pcr = atm_pcr_goal (txtp);
2310 // int scr = atm_scr_goal (txtp);
2311 int scr = pcr/2; // just for fun
2312 unsigned int mbs = 60; // just for fun
2313 rounding pr;
2314 rounding sr;
2315 unsigned int bucket;
2316 if (!pcr) {
2317 pr = round_nearest;
2318 pcr = 1<<30;
2319 } else if (pcr < 0) {
2320 pr = round_down;
2321 pcr = -pcr;
2322 } else {
2323 pr = round_up;
2324 }
2325 error = make_rate_with_tolerance (dev, pcr, pr, 10,
2326 &vcc.tx_pcr_bits, 0);
2327 if (!scr) {
2328 // see comments for PCR with CBR above
2329 sr = round_down;
2330 // slight race (no locking) here so we may get -EAGAIN
2331 // later; the greedy bastards would deserve it :)
2332 PRINTD (DBG_QOS, "snatching all remaining TX bandwidth");
2333 scr = dev->tx_avail;
2334 } else if (scr < 0) {
2335 sr = round_down;
2336 scr = -scr;
2337 } else {
2338 sr = round_up;
2339 }
2340 error = make_rate_with_tolerance (dev, scr, sr, 10,
2341 &vcc.tx_scr_bits, &vcc.tx_rate);
2342 if (error) {
2343 PRINTD (DBG_QOS, "could not make rate from TX SCR");
2344 return error;
2345 }
2346 // not really clear what further checking is needed
2347 // error = atm_scr_check (txtp, vcc.tx_rate);
2348 if (error) {
2349 PRINTD (DBG_QOS, "TX SCR failed consistency check");
2350 return error;
2351 }
2352 // bucket calculations (from a piece of paper...) cell bucket
2353 // capacity must be largest integer smaller than m(p-s)/p + 1
2354 // where m = max burst size, p = pcr, s = scr
2355 bucket = mbs*(pcr-scr)/pcr;
2356 if (bucket*pcr != mbs*(pcr-scr))
2357 bucket += 1;
2358 if (bucket > BUCKET_MAX_SIZE) {
2359 PRINTD (DBG_QOS, "shrinking bucket from %u to %u",
2360 bucket, BUCKET_MAX_SIZE);
2361 bucket = BUCKET_MAX_SIZE;
2362 }
2363 vcc.tx_xbr_bits = VBR_RATE_TYPE;
2364 vcc.tx_bucket_bits = bucket;
2365 break;
2366 }
2367#endif
2368 default: {
2369 PRINTD (DBG_QOS, "unsupported TX traffic class");
2370 return -EINVAL;
2371 break;
2372 }
2373 }
2374 }
2375
2376 // RX traffic parameters
2377
2378 PRINTD (DBG_QOS, "RX:");
2379
2380 rxtp = &qos->rxtp;
2381
2382 // set up defaults for no traffic
2383 vcc.rx_rate = 0;
2384
2385 if (rxtp->traffic_class != ATM_NONE) {
2386 error = check_max_sdu (vcc.aal, rxtp, max_rx_size);
2387 if (error) {
2388 PRINTD (DBG_QOS, "RX max_sdu check failed");
2389 return error;
2390 }
2391 switch (rxtp->traffic_class) {
2392 case ATM_UBR: {
2393 // not reserved
2394 break;
2395 }
2396#if 0
2397 case ATM_ABR: {
2398 // reserve min
2399 vcc.rx_rate = 0; // ?
2400 break;
2401 }
2402#endif
2403 case ATM_CBR: {
2404 int pcr = atm_pcr_goal (rxtp);
2405 if (!pcr) {
2406 // slight race (no locking) here so we may get -EAGAIN
2407 // later; the greedy bastards would deserve it :)
2408 PRINTD (DBG_QOS, "snatching all remaining RX bandwidth");
2409 pcr = dev->rx_avail;
2410 } else if (pcr < 0) {
2411 pcr = -pcr;
2412 }
2413 vcc.rx_rate = pcr;
2414 // not really clear what further checking is needed
2415 error = atm_pcr_check (rxtp, vcc.rx_rate);
2416 if (error) {
2417 PRINTD (DBG_QOS, "RX PCR failed consistency check");
2418 return error;
2419 }
2420 break;
2421 }
2422#if 0
2423 case ATM_VBR: {
2424 // int scr = atm_scr_goal (rxtp);
2425 int scr = 1<<16; // just for fun
2426 if (!scr) {
2427 // slight race (no locking) here so we may get -EAGAIN
2428 // later; the greedy bastards would deserve it :)
2429 PRINTD (DBG_QOS, "snatching all remaining RX bandwidth");
2430 scr = dev->rx_avail;
2431 } else if (scr < 0) {
2432 scr = -scr;
2433 }
2434 vcc.rx_rate = scr;
2435 // not really clear what further checking is needed
2436 // error = atm_scr_check (rxtp, vcc.rx_rate);
2437 if (error) {
2438 PRINTD (DBG_QOS, "RX SCR failed consistency check");
2439 return error;
2440 }
2441 break;
2442 }
2443#endif
2444 default: {
2445 PRINTD (DBG_QOS, "unsupported RX traffic class");
2446 return -EINVAL;
2447 break;
2448 }
2449 }
2450 }
2451
2452
2453 // late abort useful for diagnostics
2454 if (vcc.aal != aal5) {
2455 PRINTD (DBG_QOS, "AAL not supported");
2456 return -EINVAL;
2457 }
2458
2459 // get space for our vcc stuff and copy parameters into it
2460 vccp = kmalloc (sizeof(hrz_vcc), GFP_KERNEL);
2461 if (!vccp) {
2462 PRINTK (KERN_ERR, "out of memory!");
2463 return -ENOMEM;
2464 }
2465 *vccp = vcc;
2466
2467 // clear error and grab cell rate resource lock
2468 error = 0;
2469 spin_lock (&dev->rate_lock);
2470
2471 if (vcc.tx_rate > dev->tx_avail) {
2472 PRINTD (DBG_QOS, "not enough TX PCR left");
2473 error = -EAGAIN;
2474 }
2475
2476 if (vcc.rx_rate > dev->rx_avail) {
2477 PRINTD (DBG_QOS, "not enough RX PCR left");
2478 error = -EAGAIN;
2479 }
2480
2481 if (!error) {
2482 // really consume cell rates
2483 dev->tx_avail -= vcc.tx_rate;
2484 dev->rx_avail -= vcc.rx_rate;
2485 PRINTD (DBG_QOS|DBG_VCC, "reserving %u TX PCR and %u RX PCR",
2486 vcc.tx_rate, vcc.rx_rate);
2487 }
2488
2489 // release lock and exit on error
2490 spin_unlock (&dev->rate_lock);
2491 if (error) {
2492 PRINTD (DBG_QOS|DBG_VCC, "insufficient cell rate resources");
2493 kfree (vccp);
2494 return error;
2495 }
2496
2497 // this is "immediately before allocating the connection identifier
2498 // in hardware" - so long as the next call does not fail :)
2499 set_bit(ATM_VF_ADDR,&atm_vcc->flags);
2500
2501 // any errors here are very serious and should never occur
2502
2503 if (rxtp->traffic_class != ATM_NONE) {
2504 if (dev->rxer[channel]) {
2505 PRINTD (DBG_ERR|DBG_VCC, "VC already open for RX");
2506 error = -EBUSY;
2507 }
2508 if (!error)
2509 error = hrz_open_rx (dev, channel);
2510 if (error) {
2511 kfree (vccp);
2512 return error;
2513 }
2514 // this link allows RX frames through
2515 dev->rxer[channel] = atm_vcc;
2516 }
2517
2518 // success, set elements of atm_vcc
2519 atm_vcc->dev_data = (void *) vccp;
2520
2521 // indicate readiness
2522 set_bit(ATM_VF_READY,&atm_vcc->flags);
2523
2524 return 0;
2525}
2526
2527/********** close VC **********/
2528
2529static void hrz_close (struct atm_vcc * atm_vcc) {
2530 hrz_dev * dev = HRZ_DEV(atm_vcc->dev);
2531 hrz_vcc * vcc = HRZ_VCC(atm_vcc);
2532 u16 channel = vcc->channel;
2533 PRINTD (DBG_VCC|DBG_FLOW, "hrz_close");
2534
2535 // indicate unreadiness
2536 clear_bit(ATM_VF_READY,&atm_vcc->flags);
2537
2538 if (atm_vcc->qos.txtp.traffic_class != ATM_NONE) {
2539 unsigned int i;
2540
2541 // let any TX on this channel that has started complete
2542 // no restart, just keep trying
2543 while (tx_hold (dev))
2544 ;
2545 // remove record of any tx_channel having been setup for this channel
2546 for (i = 0; i < TX_CHANS; ++i)
2547 if (dev->tx_channel_record[i] == channel) {
2548 dev->tx_channel_record[i] = -1;
2549 break;
2550 }
2551 if (dev->last_vc == channel)
2552 dev->tx_last = -1;
2553 tx_release (dev);
2554 }
2555
2556 if (atm_vcc->qos.rxtp.traffic_class != ATM_NONE) {
2557 // disable RXing - it tries quite hard
2558 hrz_close_rx (dev, channel);
2559 // forget the vcc - no more skbs will be pushed
2560 if (atm_vcc != dev->rxer[channel])
2561 PRINTK (KERN_ERR, "%s atm_vcc=%p rxer[channel]=%p",
2562 "arghhh! we're going to die!",
2563 atm_vcc, dev->rxer[channel]);
2564 dev->rxer[channel] = NULL;
2565 }
2566
2567 // atomically release our rate reservation
2568 spin_lock (&dev->rate_lock);
2569 PRINTD (DBG_QOS|DBG_VCC, "releasing %u TX PCR and %u RX PCR",
2570 vcc->tx_rate, vcc->rx_rate);
2571 dev->tx_avail += vcc->tx_rate;
2572 dev->rx_avail += vcc->rx_rate;
2573 spin_unlock (&dev->rate_lock);
2574
2575 // free our structure
2576 kfree (vcc);
2577 // say the VPI/VCI is free again
2578 clear_bit(ATM_VF_ADDR,&atm_vcc->flags);
2579}
2580
2581#if 0
2582static int hrz_getsockopt (struct atm_vcc * atm_vcc, int level, int optname,
2583 void *optval, int optlen) {
2584 hrz_dev * dev = HRZ_DEV(atm_vcc->dev);
2585 PRINTD (DBG_FLOW|DBG_VCC, "hrz_getsockopt");
2586 switch (level) {
2587 case SOL_SOCKET:
2588 switch (optname) {
2589// case SO_BCTXOPT:
2590// break;
2591// case SO_BCRXOPT:
2592// break;
2593 default:
2594 return -ENOPROTOOPT;
2595 break;
2596 };
2597 break;
2598 }
2599 return -EINVAL;
2600}
2601
2602static int hrz_setsockopt (struct atm_vcc * atm_vcc, int level, int optname,
2603 void *optval, int optlen) {
2604 hrz_dev * dev = HRZ_DEV(atm_vcc->dev);
2605 PRINTD (DBG_FLOW|DBG_VCC, "hrz_setsockopt");
2606 switch (level) {
2607 case SOL_SOCKET:
2608 switch (optname) {
2609// case SO_BCTXOPT:
2610// break;
2611// case SO_BCRXOPT:
2612// break;
2613 default:
2614 return -ENOPROTOOPT;
2615 break;
2616 };
2617 break;
2618 }
2619 return -EINVAL;
2620}
2621#endif
2622
2623#if 0
2624static int hrz_ioctl (struct atm_dev * atm_dev, unsigned int cmd, void *arg) {
2625 hrz_dev * dev = HRZ_DEV(atm_dev);
2626 PRINTD (DBG_FLOW, "hrz_ioctl");
2627 return -1;
2628}
2629
2630unsigned char hrz_phy_get (struct atm_dev * atm_dev, unsigned long addr) {
2631 hrz_dev * dev = HRZ_DEV(atm_dev);
2632 PRINTD (DBG_FLOW, "hrz_phy_get");
2633 return 0;
2634}
2635
2636static void hrz_phy_put (struct atm_dev * atm_dev, unsigned char value,
2637 unsigned long addr) {
2638 hrz_dev * dev = HRZ_DEV(atm_dev);
2639 PRINTD (DBG_FLOW, "hrz_phy_put");
2640}
2641
2642static int hrz_change_qos (struct atm_vcc * atm_vcc, struct atm_qos *qos, int flgs) {
2643 hrz_dev * dev = HRZ_DEV(vcc->dev);
2644 PRINTD (DBG_FLOW, "hrz_change_qos");
2645 return -1;
2646}
2647#endif
2648
2649/********** proc file contents **********/
2650
2651static int hrz_proc_read (struct atm_dev * atm_dev, loff_t * pos, char * page) {
2652 hrz_dev * dev = HRZ_DEV(atm_dev);
2653 int left = *pos;
2654 PRINTD (DBG_FLOW, "hrz_proc_read");
2655
2656 /* more diagnostics here? */
2657
2658#if 0
2659 if (!left--) {
2660 unsigned int count = sprintf (page, "vbr buckets:");
2661 unsigned int i;
2662 for (i = 0; i < TX_CHANS; ++i)
2663 count += sprintf (page, " %u/%u",
2664 query_tx_channel_config (dev, i, BUCKET_FULLNESS_ACCESS),
2665 query_tx_channel_config (dev, i, BUCKET_CAPACITY_ACCESS));
2666 count += sprintf (page+count, ".\n");
2667 return count;
2668 }
2669#endif
2670
2671 if (!left--)
2672 return sprintf (page,
2673 "cells: TX %lu, RX %lu, HEC errors %lu, unassigned %lu.\n",
2674 dev->tx_cell_count, dev->rx_cell_count,
2675 dev->hec_error_count, dev->unassigned_cell_count);
2676
2677 if (!left--)
2678 return sprintf (page,
2679 "free cell buffers: TX %hu, RX %hu+%hu.\n",
2680 rd_regw (dev, TX_FREE_BUFFER_COUNT_OFF),
2681 rd_regw (dev, RX_FREE_BUFFER_COUNT_OFF),
2682 dev->noof_spare_buffers);
2683
2684 if (!left--)
2685 return sprintf (page,
2686 "cps remaining: TX %u, RX %u\n",
2687 dev->tx_avail, dev->rx_avail);
2688
2689 return 0;
2690}
2691
2692static const struct atmdev_ops hrz_ops = {
2693 .open = hrz_open,
2694 .close = hrz_close,
2695 .send = hrz_send,
2696 .proc_read = hrz_proc_read,
2697 .owner = THIS_MODULE,
2698};
2699
2700static int __devinit hrz_probe(struct pci_dev *pci_dev, const struct pci_device_id *pci_ent)
2701{
2702 hrz_dev * dev;
2703 int err = 0;
2704
2705 // adapter slot free, read resources from PCI configuration space
2706 u32 iobase = pci_resource_start (pci_dev, 0);
2707 u32 * membase = bus_to_virt (pci_resource_start (pci_dev, 1));
2708 unsigned int irq;
2709 unsigned char lat;
2710
2711 PRINTD (DBG_FLOW, "hrz_probe");
2712
2713 if (pci_enable_device(pci_dev))
2714 return -EINVAL;
2715
2716 /* XXX DEV_LABEL is a guess */
2717 if (!request_region(iobase, HRZ_IO_EXTENT, DEV_LABEL)) {
2718 return -EINVAL;
2719 goto out_disable;
2720 }
2721
2722 dev = kmalloc(sizeof(hrz_dev), GFP_KERNEL);
2723 if (!dev) {
2724 // perhaps we should be nice: deregister all adapters and abort?
2725 PRINTD(DBG_ERR, "out of memory");
2726 err = -ENOMEM;
2727 goto out_release;
2728 }
2729
2730 memset(dev, 0, sizeof(hrz_dev));
2731
2732 pci_set_drvdata(pci_dev, dev);
2733
2734 // grab IRQ and install handler - move this someplace more sensible
2735 irq = pci_dev->irq;
2736 if (request_irq(irq,
2737 interrupt_handler,
2738 SA_SHIRQ, /* irqflags guess */
2739 DEV_LABEL, /* name guess */
2740 dev)) {
2741 PRINTD(DBG_WARN, "request IRQ failed!");
2742 err = -EINVAL;
2743 goto out_free;
2744 }
2745
2746 PRINTD(DBG_INFO, "found Madge ATM adapter (hrz) at: IO %x, IRQ %u, MEM %p",
2747 iobase, irq, membase);
2748
2749 dev->atm_dev = atm_dev_register(DEV_LABEL, &hrz_ops, -1, NULL);
2750 if (!(dev->atm_dev)) {
2751 PRINTD(DBG_ERR, "failed to register Madge ATM adapter");
2752 err = -EINVAL;
2753 goto out_free_irq;
2754 }
2755
2756 PRINTD(DBG_INFO, "registered Madge ATM adapter (no. %d) (%p) at %p",
2757 dev->atm_dev->number, dev, dev->atm_dev);
2758 dev->atm_dev->dev_data = (void *) dev;
2759 dev->pci_dev = pci_dev;
2760
2761 // enable bus master accesses
2762 pci_set_master(pci_dev);
2763
2764 // frobnicate latency (upwards, usually)
2765 pci_read_config_byte(pci_dev, PCI_LATENCY_TIMER, &lat);
2766 if (pci_lat) {
2767 PRINTD(DBG_INFO, "%s PCI latency timer from %hu to %hu",
2768 "changing", lat, pci_lat);
2769 pci_write_config_byte(pci_dev, PCI_LATENCY_TIMER, pci_lat);
2770 } else if (lat < MIN_PCI_LATENCY) {
2771 PRINTK(KERN_INFO, "%s PCI latency timer from %hu to %hu",
2772 "increasing", lat, MIN_PCI_LATENCY);
2773 pci_write_config_byte(pci_dev, PCI_LATENCY_TIMER, MIN_PCI_LATENCY);
2774 }
2775
2776 dev->iobase = iobase;
2777 dev->irq = irq;
2778 dev->membase = membase;
2779
2780 dev->rx_q_entry = dev->rx_q_reset = &memmap->rx_q_entries[0];
2781 dev->rx_q_wrap = &memmap->rx_q_entries[RX_CHANS-1];
2782
2783 // these next three are performance hacks
2784 dev->last_vc = -1;
2785 dev->tx_last = -1;
2786 dev->tx_idle = 0;
2787
2788 dev->tx_regions = 0;
2789 dev->tx_bytes = 0;
2790 dev->tx_skb = NULL;
2791 dev->tx_iovec = NULL;
2792
2793 dev->tx_cell_count = 0;
2794 dev->rx_cell_count = 0;
2795 dev->hec_error_count = 0;
2796 dev->unassigned_cell_count = 0;
2797
2798 dev->noof_spare_buffers = 0;
2799
2800 {
2801 unsigned int i;
2802 for (i = 0; i < TX_CHANS; ++i)
2803 dev->tx_channel_record[i] = -1;
2804 }
2805
2806 dev->flags = 0;
2807
2808 // Allocate cell rates and remember ASIC version
2809 // Fibre: ATM_OC3_PCR = 1555200000/8/270*260/53 - 29/53
2810 // Copper: (WRONG) we want 6 into the above, close to 25Mb/s
2811 // Copper: (plagarise!) 25600000/8/270*260/53 - n/53
2812
2813 if (hrz_init(dev)) {
2814 // to be really pedantic, this should be ATM_OC3c_PCR
2815 dev->tx_avail = ATM_OC3_PCR;
2816 dev->rx_avail = ATM_OC3_PCR;
2817 set_bit(ultra, &dev->flags); // NOT "|= ultra" !
2818 } else {
2819 dev->tx_avail = ((25600000/8)*26)/(27*53);
2820 dev->rx_avail = ((25600000/8)*26)/(27*53);
2821 PRINTD(DBG_WARN, "Buggy ASIC: no TX bus-mastering.");
2822 }
2823
2824 // rate changes spinlock
2825 spin_lock_init(&dev->rate_lock);
2826
2827 // on-board memory access spinlock; we want atomic reads and
2828 // writes to adapter memory (handles IRQ and SMP)
2829 spin_lock_init(&dev->mem_lock);
2830
2831 init_waitqueue_head(&dev->tx_queue);
2832
2833 // vpi in 0..4, vci in 6..10
2834 dev->atm_dev->ci_range.vpi_bits = vpi_bits;
2835 dev->atm_dev->ci_range.vci_bits = 10-vpi_bits;
2836
2837 init_timer(&dev->housekeeping);
2838 dev->housekeeping.function = do_housekeeping;
2839 dev->housekeeping.data = (unsigned long) dev;
2840 mod_timer(&dev->housekeeping, jiffies);
2841
2842out:
2843 return err;
2844
2845out_free_irq:
2846 free_irq(dev->irq, dev);
2847out_free:
2848 kfree(dev);
2849out_release:
2850 release_region(iobase, HRZ_IO_EXTENT);
2851out_disable:
2852 pci_disable_device(pci_dev);
2853 goto out;
2854}
2855
2856static void __devexit hrz_remove_one(struct pci_dev *pci_dev)
2857{
2858 hrz_dev *dev;
2859
2860 dev = pci_get_drvdata(pci_dev);
2861
2862 PRINTD(DBG_INFO, "closing %p (atm_dev = %p)", dev, dev->atm_dev);
2863 del_timer_sync(&dev->housekeeping);
2864 hrz_reset(dev);
2865 atm_dev_deregister(dev->atm_dev);
2866 free_irq(dev->irq, dev);
2867 release_region(dev->iobase, HRZ_IO_EXTENT);
2868 kfree(dev);
2869
2870 pci_disable_device(pci_dev);
2871}
2872
2873static void __init hrz_check_args (void) {
2874#ifdef DEBUG_HORIZON
2875 PRINTK (KERN_NOTICE, "debug bitmap is %hx", debug &= DBG_MASK);
2876#else
2877 if (debug)
2878 PRINTK (KERN_NOTICE, "no debug support in this image");
2879#endif
2880
2881 if (vpi_bits > HRZ_MAX_VPI)
2882 PRINTK (KERN_ERR, "vpi_bits has been limited to %hu",
2883 vpi_bits = HRZ_MAX_VPI);
2884
2885 if (max_tx_size < 0 || max_tx_size > TX_AAL5_LIMIT)
2886 PRINTK (KERN_NOTICE, "max_tx_size has been limited to %hu",
2887 max_tx_size = TX_AAL5_LIMIT);
2888
2889 if (max_rx_size < 0 || max_rx_size > RX_AAL5_LIMIT)
2890 PRINTK (KERN_NOTICE, "max_rx_size has been limited to %hu",
2891 max_rx_size = RX_AAL5_LIMIT);
2892
2893 return;
2894}
2895
2896MODULE_AUTHOR(maintainer_string);
2897MODULE_DESCRIPTION(description_string);
2898MODULE_LICENSE("GPL");
2899module_param(debug, ushort, 0644);
2900module_param(vpi_bits, ushort, 0);
2901module_param(max_tx_size, int, 0);
2902module_param(max_rx_size, int, 0);
2903module_param(pci_lat, byte, 0);
2904MODULE_PARM_DESC(debug, "debug bitmap, see .h file");
2905MODULE_PARM_DESC(vpi_bits, "number of bits (0..4) to allocate to VPIs");
2906MODULE_PARM_DESC(max_tx_size, "maximum size of TX AAL5 frames");
2907MODULE_PARM_DESC(max_rx_size, "maximum size of RX AAL5 frames");
2908MODULE_PARM_DESC(pci_lat, "PCI latency in bus cycles");
2909
2910static struct pci_device_id hrz_pci_tbl[] = {
2911 { PCI_VENDOR_ID_MADGE, PCI_DEVICE_ID_MADGE_HORIZON, PCI_ANY_ID, PCI_ANY_ID,
2912 0, 0, 0 },
2913 { 0, }
2914};
2915
2916MODULE_DEVICE_TABLE(pci, hrz_pci_tbl);
2917
2918static struct pci_driver hrz_driver = {
2919 .name = "horizon",
2920 .probe = hrz_probe,
2921 .remove = __devexit_p(hrz_remove_one),
2922 .id_table = hrz_pci_tbl,
2923};
2924
2925/********** module entry **********/
2926
2927static int __init hrz_module_init (void) {
2928 // sanity check - cast is needed since printk does not support %Zu
2929 if (sizeof(struct MEMMAP) != 128*1024/4) {
2930 PRINTK (KERN_ERR, "Fix struct MEMMAP (is %lu fakewords).",
2931 (unsigned long) sizeof(struct MEMMAP));
2932 return -ENOMEM;
2933 }
2934
2935 show_version();
2936
2937 // check arguments
2938 hrz_check_args();
2939
2940 // get the juice
2941 return pci_register_driver(&hrz_driver);
2942}
2943
2944/********** module exit **********/
2945
2946static void __exit hrz_module_exit (void) {
2947 PRINTD (DBG_FLOW, "cleanup_module");
2948
2949 return pci_unregister_driver(&hrz_driver);
2950}
2951
2952module_init(hrz_module_init);
2953module_exit(hrz_module_exit);
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-20 21:51:46 -0500