Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus

Pull MIPS updates from Ralf Baechle:
 "The MIPS bits for 3.8.  This also includes a bunch fixes that were
  sitting in the linux-mips.org git tree for a long time.  This pull
  request contains updates to several OCTEON drivers and the board
  support code for BCM47XX, BCM63XX, XLP, XLR, XLS, lantiq, Loongson1B,
  updates to the SSB bus support, MIPS kexec code and adds support for
  kdump.

  When pulling this, there are two expected merge conflicts in
  include/linux/bcma/bcma_driver_chipcommon.h which are trivial to
  resolve, just remove the conflict markers and keep both alternatives."

* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (90 commits)
  MIPS: PMC-Sierra Yosemite: Remove support.
  VIDEO: Newport Fix console crashes
  MIPS: wrppmc: Fix build of PCI code.
  MIPS: IP22/IP28: Fix build of EISA code.
  MIPS: RB532: Fix build of prom code.
  MIPS: PowerTV: Fix build.
  MIPS: IP27: Correct fucked grammar in ops-bridge.c
  MIPS: Highmem: Fix build error if CONFIG_DEBUG_HIGHMEM is disabled
  MIPS: Fix potencial corruption
  MIPS: Fix for warning from FPU emulation code
  MIPS: Handle COP3 Unusable exception as COP1X for FP emulation
  MIPS: Fix poweroff failure when HOTPLUG_CPU configured.
  MIPS: MT: Fix build with CONFIG_UIDGID_STRICT_TYPE_CHECKS=y
  MIPS: Remove unused smvp.h
  MIPS/EDAC: Improve OCTEON EDAC support.
  MIPS: OCTEON: Add definitions for OCTEON memory contoller registers.
  MIPS: OCTEON: Add OCTEON family definitions to octeon-model.h
  ata: pata_octeon_cf: Use correct byte order for DMA in when built little-endian.
  MIPS/OCTEON/ata: Convert pata_octeon_cf.c to use device tree.
  MIPS: Remove usage of CEVT_R4K_LIB config option.
  ...

1 files changed, 288 insertions, 135 deletions

diff --git a/drivers/ata/pata_octeon_cf.c b/drivers/ata/pata_octeon_cf.c
index 1d61d5d278fa..4e1194b4c271 100644
--- a/drivers/ata/pata_octeon_cf.c
+++ b/drivers/ata/pata_octeon_cf.c
@@ -5,19 +5,22 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 2005 - 2009 Cavium Networks
+ * Copyright (C) 2005 - 2012 Cavium Inc.
  * Copyright (C) 2008 Wind River Systems
  */
 
 #include <linux/kernel.h>
 #include <linux/module.h>
 #include <linux/libata.h>
-#include <linux/irq.h>
+#include <linux/hrtimer.h>
 #include <linux/slab.h>
+#include <linux/irq.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
 #include <linux/platform_device.h>
-#include <linux/workqueue.h>
 #include <scsi/scsi_host.h>
 
+#include <asm/byteorder.h>
 #include <asm/octeon/octeon.h>
 
 /*
@@ -34,20 +37,36 @@
  */
 
 #define DRV_NAME        "pata_octeon_cf"
-#define DRV_VERSION     "2.1"
+#define DRV_VERSION     "2.2"
+
+/* Poll interval in nS. */
+#define OCTEON_CF_BUSY_POLL_INTERVAL 500000
 
+#define DMA_CFG 0
+#define DMA_TIM 0x20
+#define DMA_INT 0x38
+#define DMA_INT_EN 0x50
 
 struct octeon_cf_port {
-        struct workqueue_struct *wq;
-        struct delayed_work delayed_finish;
+        struct hrtimer delayed_finish;
         struct ata_port *ap;
         int dma_finished;
+        void            *c0;
+        unsigned int cs0;
+        unsigned int cs1;
+        bool is_true_ide;
+        u64 dma_base;
 };
 
 static struct scsi_host_template octeon_cf_sht = {
         ATA_PIO_SHT(DRV_NAME),
 };
 
+static int enable_dma;
+module_param(enable_dma, int, 0444);
+MODULE_PARM_DESC(enable_dma,
+                 "Enable use of DMA on interfaces that support it (0=no dma [default], 1=use dma)");
+
 /**
  * Convert nanosecond based time to setting used in the
  * boot bus timing register, based on timing multiple
@@ -66,12 +85,29 @@ static unsigned int ns_to_tim_reg(unsigned int tim_mult, unsigned int nsecs)
         return val;
 }
 
-static void octeon_cf_set_boot_reg_cfg(int cs)
+static void octeon_cf_set_boot_reg_cfg(int cs, unsigned int multiplier)
 {
         union cvmx_mio_boot_reg_cfgx reg_cfg;
+        unsigned int tim_mult;
+
+        switch (multiplier) {
+        case 8:
+                tim_mult = 3;
+                break;
+        case 4:
+                tim_mult = 0;
+                break;
+        case 2:
+                tim_mult = 2;
+                break;
+        default:
+                tim_mult = 1;
+                break;
+        }
+
         reg_cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(cs));
         reg_cfg.s.dmack = 0;    /* Don't assert DMACK on access */
-        reg_cfg.s.tim_mult = 2; /* Timing mutiplier 2x */
+        reg_cfg.s.tim_mult = tim_mult;  /* Timing mutiplier */
         reg_cfg.s.rd_dly = 0;   /* Sample on falling edge of BOOT_OE */
         reg_cfg.s.sam = 0;      /* Don't combine write and output enable */
         reg_cfg.s.we_ext = 0;   /* No write enable extension */
@@ -92,12 +128,12 @@ static void octeon_cf_set_boot_reg_cfg(int cs)
  */
 static void octeon_cf_set_piomode(struct ata_port *ap, struct ata_device *dev)
 {
-        struct octeon_cf_data *ocd = ap->dev->platform_data;
+        struct octeon_cf_port *cf_port = ap->private_data;
         union cvmx_mio_boot_reg_timx reg_tim;
-        int cs = ocd->base_region;
         int T;
         struct ata_timing timing;
 
+        unsigned int div;
         int use_iordy;
         int trh;
         int pause;
@@ -106,7 +142,15 @@ static void octeon_cf_set_piomode(struct ata_port *ap, struct ata_device *dev)
         int t2;
         int t2i;
 
-        T = (int)(2000000000000LL / octeon_get_clock_rate());
+        /*
+         * A divisor value of four will overflow the timing fields at
+         * clock rates greater than 800MHz
+         */
+        if (octeon_get_io_clock_rate() <= 800000000)
+                div = 4;
+        else
+                div = 8;
+        T = (int)((1000000000000LL * div) / octeon_get_io_clock_rate());
 
         if (ata_timing_compute(dev, dev->pio_mode, &timing, T, T))
                 BUG();
@@ -121,23 +165,26 @@ static void octeon_cf_set_piomode(struct ata_port *ap, struct ata_device *dev)
         if (t2i)
                 t2i--;
 
-        trh = ns_to_tim_reg(2, 20);
+        trh = ns_to_tim_reg(div, 20);
         if (trh)
                 trh--;
 
-        pause = timing.cycle - timing.active - timing.setup - trh;
+        pause = (int)timing.cycle - (int)timing.active -
+                (int)timing.setup - trh;
+        if (pause < 0)
+                pause = 0;
         if (pause)
                 pause--;
 
-        octeon_cf_set_boot_reg_cfg(cs);
-        if (ocd->dma_engine >= 0)
+        octeon_cf_set_boot_reg_cfg(cf_port->cs0, div);
+        if (cf_port->is_true_ide)
                 /* True IDE mode, program both chip selects.  */
-                octeon_cf_set_boot_reg_cfg(cs + 1);
+                octeon_cf_set_boot_reg_cfg(cf_port->cs1, div);
 
 
         use_iordy = ata_pio_need_iordy(dev);
 
-        reg_tim.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_TIMX(cs));
+        reg_tim.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_TIMX(cf_port->cs0));
         /* Disable page mode */
         reg_tim.s.pagem = 0;
         /* Enable dynamic timing */
@@ -161,20 +208,22 @@ static void octeon_cf_set_piomode(struct ata_port *ap, struct ata_device *dev)
         /* How long read enable is asserted */
         reg_tim.s.oe = t2;
         /* Time after CE that read/write starts */
-        reg_tim.s.ce = ns_to_tim_reg(2, 5);
+        reg_tim.s.ce = ns_to_tim_reg(div, 5);
         /* Time before CE that address is valid */
         reg_tim.s.adr = 0;
 
         /* Program the bootbus region timing for the data port chip select. */
-        cvmx_write_csr(CVMX_MIO_BOOT_REG_TIMX(cs), reg_tim.u64);
-        if (ocd->dma_engine >= 0)
+        cvmx_write_csr(CVMX_MIO_BOOT_REG_TIMX(cf_port->cs0), reg_tim.u64);
+        if (cf_port->is_true_ide)
                 /* True IDE mode, program both chip selects.  */
-                cvmx_write_csr(CVMX_MIO_BOOT_REG_TIMX(cs + 1), reg_tim.u64);
+                cvmx_write_csr(CVMX_MIO_BOOT_REG_TIMX(cf_port->cs1),
+                               reg_tim.u64);
 }
 
 static void octeon_cf_set_dmamode(struct ata_port *ap, struct ata_device *dev)
 {
-        struct octeon_cf_data *ocd = dev->link->ap->dev->platform_data;
+        struct octeon_cf_port *cf_port = ap->private_data;
+        union cvmx_mio_boot_pin_defs pin_defs;
         union cvmx_mio_boot_dma_timx dma_tim;
         unsigned int oe_a;
         unsigned int oe_n;
@@ -183,6 +232,7 @@ static void octeon_cf_set_dmamode(struct ata_port *ap, struct ata_device *dev)
         unsigned int pause;
         unsigned int T0, Tkr, Td;
         unsigned int tim_mult;
+        int c;
 
         const struct ata_timing *timing;
 
@@ -199,13 +249,19 @@ static void octeon_cf_set_dmamode(struct ata_port *ap, struct ata_device *dev)
         /* not spec'ed, value in eclocks, not affected by tim_mult */
         dma_arq = 8;
         pause = 25 - dma_arq * 1000 /
-                (octeon_get_clock_rate() / 1000000); /* Tz */
+                (octeon_get_io_clock_rate() / 1000000); /* Tz */
 
         oe_a = Td;
         /* Tkr from cf spec, lengthened to meet T0 */
         oe_n = max(T0 - oe_a, Tkr);
 
-        dma_tim.s.dmack_pi = 1;
+        pin_defs.u64 = cvmx_read_csr(CVMX_MIO_BOOT_PIN_DEFS);
+
+        /* DMA channel number. */
+        c = (cf_port->dma_base & 8) >> 3;
+
+        /* Invert the polarity if the default is 0*/
+        dma_tim.s.dmack_pi = (pin_defs.u64 & (1ull << (11 + c))) ? 0 : 1;
 
         dma_tim.s.oe_n = ns_to_tim_reg(tim_mult, oe_n);
         dma_tim.s.oe_a = ns_to_tim_reg(tim_mult, oe_a);
@@ -228,14 +284,11 @@ static void octeon_cf_set_dmamode(struct ata_port *ap, struct ata_device *dev)
 
         pr_debug("ns to ticks (mult %d) of %d is: %d\n", tim_mult, 60,
                  ns_to_tim_reg(tim_mult, 60));
-        pr_debug("oe_n: %d, oe_a: %d, dmack_s: %d, dmack_h: "
-                 "%d, dmarq: %d, pause: %d\n",
+        pr_debug("oe_n: %d, oe_a: %d, dmack_s: %d, dmack_h: %d, dmarq: %d, pause: %d\n",
                  dma_tim.s.oe_n, dma_tim.s.oe_a, dma_tim.s.dmack_s,
                  dma_tim.s.dmack_h, dma_tim.s.dmarq, dma_tim.s.pause);
 
-        cvmx_write_csr(CVMX_MIO_BOOT_DMA_TIMX(ocd->dma_engine),
-                       dma_tim.u64);
-
+        cvmx_write_csr(cf_port->dma_base + DMA_TIM, dma_tim.u64);
 }
 
 /**
@@ -489,15 +542,10 @@ static void octeon_cf_exec_command16(struct ata_port *ap,
         ata_wait_idle(ap);
 }
 
-static void octeon_cf_irq_on(struct ata_port *ap)
+static void octeon_cf_ata_port_noaction(struct ata_port *ap)
 {
 }
 
-static void octeon_cf_irq_clear(struct ata_port *ap)
-{
-        return;
-}
-
 static void octeon_cf_dma_setup(struct ata_queued_cmd *qc)
 {
         struct ata_port *ap = qc->ap;
@@ -519,7 +567,7 @@ static void octeon_cf_dma_setup(struct ata_queued_cmd *qc)
  */
 static void octeon_cf_dma_start(struct ata_queued_cmd *qc)
 {
-        struct octeon_cf_data *ocd = qc->ap->dev->platform_data;
+        struct octeon_cf_port *cf_port = qc->ap->private_data;
         union cvmx_mio_boot_dma_cfgx mio_boot_dma_cfg;
         union cvmx_mio_boot_dma_intx mio_boot_dma_int;
         struct scatterlist *sg;
@@ -535,15 +583,16 @@ static void octeon_cf_dma_start(struct ata_queued_cmd *qc)
          */
         mio_boot_dma_int.u64 = 0;
         mio_boot_dma_int.s.done = 1;
-        cvmx_write_csr(CVMX_MIO_BOOT_DMA_INTX(ocd->dma_engine),
-                       mio_boot_dma_int.u64);
+        cvmx_write_csr(cf_port->dma_base + DMA_INT, mio_boot_dma_int.u64);
 
         /* Enable the interrupt.  */
-        cvmx_write_csr(CVMX_MIO_BOOT_DMA_INT_ENX(ocd->dma_engine),
-                       mio_boot_dma_int.u64);
+        cvmx_write_csr(cf_port->dma_base + DMA_INT_EN, mio_boot_dma_int.u64);
 
         /* Set the direction of the DMA */
         mio_boot_dma_cfg.u64 = 0;
+#ifdef __LITTLE_ENDIAN
+        mio_boot_dma_cfg.s.endian = 1;
+#endif
         mio_boot_dma_cfg.s.en = 1;
         mio_boot_dma_cfg.s.rw = ((qc->tf.flags & ATA_TFLAG_WRITE) != 0);
 
@@ -569,8 +618,7 @@ static void octeon_cf_dma_start(struct ata_queued_cmd *qc)
                 (mio_boot_dma_cfg.s.rw) ? "write" : "read", sg->length,
                 (void *)(unsigned long)mio_boot_dma_cfg.s.adr);
 
-        cvmx_write_csr(CVMX_MIO_BOOT_DMA_CFGX(ocd->dma_engine),
-                       mio_boot_dma_cfg.u64);
+        cvmx_write_csr(cf_port->dma_base + DMA_CFG, mio_boot_dma_cfg.u64);
 }
 
 /**
@@ -583,10 +631,9 @@ static unsigned int octeon_cf_dma_finished(struct ata_port *ap,
                                         struct ata_queued_cmd *qc)
 {
         struct ata_eh_info *ehi = &ap->link.eh_info;
-        struct octeon_cf_data *ocd = ap->dev->platform_data;
+        struct octeon_cf_port *cf_port = ap->private_data;
         union cvmx_mio_boot_dma_cfgx dma_cfg;
         union cvmx_mio_boot_dma_intx dma_int;
-        struct octeon_cf_port *cf_port;
         u8 status;
 
         VPRINTK("ata%u: protocol %d task_state %d\n",
@@ -596,9 +643,7 @@ static unsigned int octeon_cf_dma_finished(struct ata_port *ap,
         if (ap->hsm_task_state != HSM_ST_LAST)
                 return 0;
 
-        cf_port = ap->private_data;
-
-        dma_cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_DMA_CFGX(ocd->dma_engine));
+        dma_cfg.u64 = cvmx_read_csr(cf_port->dma_base + DMA_CFG);
         if (dma_cfg.s.size != 0xfffff) {
                 /* Error, the transfer was not complete.  */
                 qc->err_mask |= AC_ERR_HOST_BUS;
@@ -608,15 +653,15 @@ static unsigned int octeon_cf_dma_finished(struct ata_port *ap,
         /* Stop and clear the dma engine.  */
         dma_cfg.u64 = 0;
         dma_cfg.s.size = -1;
-        cvmx_write_csr(CVMX_MIO_BOOT_DMA_CFGX(ocd->dma_engine), dma_cfg.u64);
+        cvmx_write_csr(cf_port->dma_base + DMA_CFG, dma_cfg.u64);
 
         /* Disable the interrupt.  */
         dma_int.u64 = 0;
-        cvmx_write_csr(CVMX_MIO_BOOT_DMA_INT_ENX(ocd->dma_engine), dma_int.u64);
+        cvmx_write_csr(cf_port->dma_base + DMA_INT_EN, dma_int.u64);
 
         /* Clear the DMA complete status */
         dma_int.s.done = 1;
-        cvmx_write_csr(CVMX_MIO_BOOT_DMA_INTX(ocd->dma_engine), dma_int.u64);
+        cvmx_write_csr(cf_port->dma_base + DMA_INT, dma_int.u64);
 
         status = ap->ops->sff_check_status(ap);
 
@@ -649,69 +694,68 @@ static irqreturn_t octeon_cf_interrupt(int irq, void *dev_instance)
                 struct ata_queued_cmd *qc;
                 union cvmx_mio_boot_dma_intx dma_int;
                 union cvmx_mio_boot_dma_cfgx dma_cfg;
-                struct octeon_cf_data *ocd;
 
                 ap = host->ports[i];
-                ocd = ap->dev->platform_data;
                 cf_port = ap->private_data;
-                dma_int.u64 =
-                        cvmx_read_csr(CVMX_MIO_BOOT_DMA_INTX(ocd->dma_engine));
-                dma_cfg.u64 =
-                        cvmx_read_csr(CVMX_MIO_BOOT_DMA_CFGX(ocd->dma_engine));
+
+                dma_int.u64 = cvmx_read_csr(cf_port->dma_base + DMA_INT);
+                dma_cfg.u64 = cvmx_read_csr(cf_port->dma_base + DMA_CFG);
 
                 qc = ata_qc_from_tag(ap, ap->link.active_tag);
 
-                if (qc && !(qc->tf.flags & ATA_TFLAG_POLLING)) {
-                        if (dma_int.s.done && !dma_cfg.s.en) {
-                                if (!sg_is_last(qc->cursg)) {
-                                        qc->cursg = sg_next(qc->cursg);
-                                        handled = 1;
-                                        octeon_cf_dma_start(qc);
-                                        continue;
-                                } else {
-                                        cf_port->dma_finished = 1;
-                                }
-                        }
-                        if (!cf_port->dma_finished)
-                                continue;
-                        status = ioread8(ap->ioaddr.altstatus_addr);
-                        if (status & (ATA_BUSY | ATA_DRQ)) {
-                                /*
-                                 * We are busy, try to handle it
-                                 * later.  This is the DMA finished
-                                 * interrupt, and it could take a
-                                 * little while for the card to be
-                                 * ready for more commands.
-                                 */
-                                /* Clear DMA irq. */
-                                dma_int.u64 = 0;
-                                dma_int.s.done = 1;
-                                cvmx_write_csr(CVMX_MIO_BOOT_DMA_INTX(ocd->dma_engine),
-                                               dma_int.u64);
-
-                                queue_delayed_work(cf_port->wq,
-                                                   &cf_port->delayed_finish, 1);
+                if (!qc || (qc->tf.flags & ATA_TFLAG_POLLING))
+                        continue;
+
+                if (dma_int.s.done && !dma_cfg.s.en) {
+                        if (!sg_is_last(qc->cursg)) {
+                                qc->cursg = sg_next(qc->cursg);
                                 handled = 1;
+                                octeon_cf_dma_start(qc);
+                                continue;
                         } else {
-                                handled |= octeon_cf_dma_finished(ap, qc);
+                                cf_port->dma_finished = 1;
                         }
                 }
+                if (!cf_port->dma_finished)
+                        continue;
+                status = ioread8(ap->ioaddr.altstatus_addr);
+                if (status & (ATA_BUSY | ATA_DRQ)) {
+                        /*
+                         * We are busy, try to handle it later.  This
+                         * is the DMA finished interrupt, and it could
+                         * take a little while for the card to be
+                         * ready for more commands.
+                         */
+                        /* Clear DMA irq. */
+                        dma_int.u64 = 0;
+                        dma_int.s.done = 1;
+                        cvmx_write_csr(cf_port->dma_base + DMA_INT,
+                                       dma_int.u64);
+                        hrtimer_start_range_ns(&cf_port->delayed_finish,
+                                               ns_to_ktime(OCTEON_CF_BUSY_POLL_INTERVAL),
+                                               OCTEON_CF_BUSY_POLL_INTERVAL / 5,
+                                               HRTIMER_MODE_REL);
+                        handled = 1;
+                } else {
+                        handled |= octeon_cf_dma_finished(ap, qc);
+                }
         }
         spin_unlock_irqrestore(&host->lock, flags);
         DPRINTK("EXIT\n");
         return IRQ_RETVAL(handled);
 }
 
-static void octeon_cf_delayed_finish(struct work_struct *work)
+static enum hrtimer_restart octeon_cf_delayed_finish(struct hrtimer *hrt)
 {
-        struct octeon_cf_port *cf_port = container_of(work,
+        struct octeon_cf_port *cf_port = container_of(hrt,
                                                       struct octeon_cf_port,
-                                                      delayed_finish.work);
+                                                      delayed_finish);
         struct ata_port *ap = cf_port->ap;
         struct ata_host *host = ap->host;
         struct ata_queued_cmd *qc;
         unsigned long flags;
         u8 status;
+        enum hrtimer_restart rv = HRTIMER_NORESTART;
 
         spin_lock_irqsave(&host->lock, flags);
 
@@ -726,15 +770,17 @@ static void octeon_cf_delayed_finish(struct work_struct *work)
         status = ioread8(ap->ioaddr.altstatus_addr);
         if (status & (ATA_BUSY | ATA_DRQ)) {
                 /* Still busy, try again. */
-                queue_delayed_work(cf_port->wq,
-                                   &cf_port->delayed_finish, 1);
+                hrtimer_forward_now(hrt,
+                                    ns_to_ktime(OCTEON_CF_BUSY_POLL_INTERVAL));
+                rv = HRTIMER_RESTART;
                 goto out;
         }
         qc = ata_qc_from_tag(ap, ap->link.active_tag);
-        if (qc && !(qc->tf.flags & ATA_TFLAG_POLLING))
+        if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING)))
                 octeon_cf_dma_finished(ap, qc);
 out:
         spin_unlock_irqrestore(&host->lock, flags);
+        return rv;
 }
 
 static void octeon_cf_dev_config(struct ata_device *dev)
@@ -786,8 +832,8 @@ static struct ata_port_operations octeon_cf_ops = {
         .qc_prep                = ata_noop_qc_prep,
         .qc_issue               = octeon_cf_qc_issue,
         .sff_dev_select         = octeon_cf_dev_select,
-        .sff_irq_on             = octeon_cf_irq_on,
-        .sff_irq_clear          = octeon_cf_irq_clear,
+        .sff_irq_on             = octeon_cf_ata_port_noaction,
+        .sff_irq_clear          = octeon_cf_ata_port_noaction,
         .cable_detect           = ata_cable_40wire,
         .set_piomode            = octeon_cf_set_piomode,
         .set_dmamode            = octeon_cf_set_dmamode,
@@ -798,46 +844,113 @@ static int __devinit octeon_cf_probe(struct platform_device *pdev)
 {
         struct resource *res_cs0, *res_cs1;
 
+        bool is_16bit;
+        const __be32 *cs_num;
+        struct property *reg_prop;
+        int n_addr, n_size, reg_len;
+        struct device_node *node;
+        const void *prop;
         void __iomem *cs0;
         void __iomem *cs1 = NULL;
         struct ata_host *host;
         struct ata_port *ap;
-        struct octeon_cf_data *ocd;
         int irq = 0;
         irq_handler_t irq_handler = NULL;
         void __iomem *base;
         struct octeon_cf_port *cf_port;
-        char version[32];
+        int rv = -ENOMEM;
 
-        res_cs0 = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 
-        if (!res_cs0)
+        node = pdev->dev.of_node;
+        if (node == NULL)
                 return -EINVAL;
 
-        ocd = pdev->dev.platform_data;
+        cf_port = kzalloc(sizeof(*cf_port), GFP_KERNEL);
+        if (!cf_port)
+                return -ENOMEM;
 
-        cs0 = devm_ioremap_nocache(&pdev->dev, res_cs0->start,
-                                   resource_size(res_cs0));
+        cf_port->is_true_ide = (of_find_property(node, "cavium,true-ide", NULL) != NULL);
 
-        if (!cs0)
-                return -ENOMEM;
+        prop = of_get_property(node, "cavium,bus-width", NULL);
+        if (prop)
+                is_16bit = (be32_to_cpup(prop) == 16);
+        else
+                is_16bit = false;
 
-        /* Determine from availability of DMA if True IDE mode or not */
-        if (ocd->dma_engine >= 0) {
-                res_cs1 = platform_get_resource(pdev, IORESOURCE_MEM, 1);
-                if (!res_cs1)
-                        return -EINVAL;
+        n_addr = of_n_addr_cells(node);
+        n_size = of_n_size_cells(node);
 
+        reg_prop = of_find_property(node, "reg", &reg_len);
+        if (!reg_prop || reg_len < sizeof(__be32)) {
+                rv = -EINVAL;
+                goto free_cf_port;
+        }
+        cs_num = reg_prop->value;
+        cf_port->cs0 = be32_to_cpup(cs_num);
+
+        if (cf_port->is_true_ide) {
+                struct device_node *dma_node;
+                dma_node = of_parse_phandle(node,
+                                            "cavium,dma-engine-handle", 0);
+                if (dma_node) {
+                        struct platform_device *dma_dev;
+                        dma_dev = of_find_device_by_node(dma_node);
+                        if (dma_dev) {
+                                struct resource *res_dma;
+                                int i;
+                                res_dma = platform_get_resource(dma_dev, IORESOURCE_MEM, 0);
+                                if (!res_dma) {
+                                        of_node_put(dma_node);
+                                        rv = -EINVAL;
+                                        goto free_cf_port;
+                                }
+                                cf_port->dma_base = (u64)devm_ioremap_nocache(&pdev->dev, res_dma->start,
+                                                                         resource_size(res_dma));
+
+                                if (!cf_port->dma_base) {
+                                        of_node_put(dma_node);
+                                        rv = -EINVAL;
+                                        goto free_cf_port;
+                                }
+
+                                irq_handler = octeon_cf_interrupt;
+                                i = platform_get_irq(dma_dev, 0);
+                                if (i > 0)
+                                        irq = i;
+                        }
+                        of_node_put(dma_node);
+                }
+                res_cs1 = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+                if (!res_cs1) {
+                        rv = -EINVAL;
+                        goto free_cf_port;
+                }
                 cs1 = devm_ioremap_nocache(&pdev->dev, res_cs1->start,
-                                           resource_size(res_cs1));
+                                           res_cs1->end - res_cs1->start + 1);
 
                 if (!cs1)
-                        return -ENOMEM;
+                        goto free_cf_port;
+
+                if (reg_len < (n_addr + n_size + 1) * sizeof(__be32)) {
+                        rv = -EINVAL;
+                        goto free_cf_port;
+                }
+                cs_num += n_addr + n_size;
+                cf_port->cs1 = be32_to_cpup(cs_num);
         }
 
-        cf_port = kzalloc(sizeof(*cf_port), GFP_KERNEL);
-        if (!cf_port)
-                return -ENOMEM;
+        res_cs0 = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+
+        if (!res_cs0) {
+                rv = -EINVAL;
+                goto free_cf_port;
+        }
+
+        cs0 = devm_ioremap_nocache(&pdev->dev, res_cs0->start,
+                                   resource_size(res_cs0));
+
+        if (!cs0)
+                goto free_cf_port;
 
         /* allocate host */
         host = ata_host_alloc(&pdev->dev, 1);
@@ -846,21 +959,22 @@ static int __devinit octeon_cf_probe(struct platform_device *pdev)
 
         ap = host->ports[0];
         ap->private_data = cf_port;
+        pdev->dev.platform_data = cf_port;
         cf_port->ap = ap;
         ap->ops = &octeon_cf_ops;
         ap->pio_mask = ATA_PIO6;
         ap->flags |= ATA_FLAG_NO_ATAPI | ATA_FLAG_PIO_POLLING;
 
-        base = cs0 + ocd->base_region_bias;
-        if (!ocd->is16bit) {
+        if (!is_16bit) {
+                base = cs0 + 0x800;
                 ap->ioaddr.cmd_addr     = base;
                 ata_sff_std_ports(&ap->ioaddr);
 
                 ap->ioaddr.altstatus_addr = base + 0xe;
                 ap->ioaddr.ctl_addr     = base + 0xe;
                 octeon_cf_ops.sff_data_xfer = octeon_cf_data_xfer8;
-        } else if (cs1) {
-                /* Presence of cs1 indicates True IDE mode.  */
+        } else if (cf_port->is_true_ide) {
+                base = cs0;
                 ap->ioaddr.cmd_addr     = base + (ATA_REG_CMD << 1) + 1;
                 ap->ioaddr.data_addr    = base + (ATA_REG_DATA << 1);
                 ap->ioaddr.error_addr   = base + (ATA_REG_ERR << 1) + 1;
@@ -876,19 +990,15 @@ static int __devinit octeon_cf_probe(struct platform_device *pdev)
                 ap->ioaddr.ctl_addr     = cs1 + (6 << 1) + 1;
                 octeon_cf_ops.sff_data_xfer = octeon_cf_data_xfer16;
 
-                ap->mwdma_mask  = ATA_MWDMA4;
-                irq = platform_get_irq(pdev, 0);
-                irq_handler = octeon_cf_interrupt;
-
-                /* True IDE mode needs delayed work to poll for not-busy.  */
-                cf_port->wq = create_singlethread_workqueue(DRV_NAME);
-                if (!cf_port->wq)
-                        goto free_cf_port;
-                INIT_DELAYED_WORK(&cf_port->delayed_finish,
-                                  octeon_cf_delayed_finish);
+                ap->mwdma_mask  = enable_dma ? ATA_MWDMA4 : 0;
 
+                /* True IDE mode needs a timer to poll for not-busy.  */
+                hrtimer_init(&cf_port->delayed_finish, CLOCK_MONOTONIC,
+                             HRTIMER_MODE_REL);
+                cf_port->delayed_finish.function = octeon_cf_delayed_finish;
         } else {
                 /* 16 bit but not True IDE */
+                base = cs0 + 0x800;
                 octeon_cf_ops.sff_data_xfer     = octeon_cf_data_xfer16;
                 octeon_cf_ops.softreset         = octeon_cf_softreset16;
                 octeon_cf_ops.sff_check_status  = octeon_cf_check_status16;
@@ -902,28 +1012,71 @@ static int __devinit octeon_cf_probe(struct platform_device *pdev)
                 ap->ioaddr.ctl_addr     = base + 0xe;
                 ap->ioaddr.altstatus_addr = base + 0xe;
         }
+        cf_port->c0 = ap->ioaddr.ctl_addr;
+
+        pdev->dev.coherent_dma_mask = DMA_BIT_MASK(64);
+        pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask;
 
         ata_port_desc(ap, "cmd %p ctl %p", base, ap->ioaddr.ctl_addr);
 
 
-        snprintf(version, sizeof(version), "%s %d bit%s",
-                 DRV_VERSION,
-                 (ocd->is16bit) ? 16 : 8,
-                 (cs1) ? ", True IDE" : "");
-        ata_print_version_once(&pdev->dev, version);
+        dev_info(&pdev->dev, "version " DRV_VERSION" %d bit%s.\n",
+                 is_16bit ? 16 : 8,
+                 cf_port->is_true_ide ? ", True IDE" : "");
 
-        return ata_host_activate(host, irq, irq_handler, 0, &octeon_cf_sht);
+        return ata_host_activate(host, irq, irq_handler,
+                                 IRQF_SHARED, &octeon_cf_sht);
 
 free_cf_port:
         kfree(cf_port);
-        return -ENOMEM;
+        return rv;
+}
+
+static void octeon_cf_shutdown(struct device *dev)
+{
+        union cvmx_mio_boot_dma_cfgx dma_cfg;
+        union cvmx_mio_boot_dma_intx dma_int;
+
+        struct octeon_cf_port *cf_port = dev->platform_data;
+
+        if (cf_port->dma_base) {
+                /* Stop and clear the dma engine.  */
+                dma_cfg.u64 = 0;
+                dma_cfg.s.size = -1;
+                cvmx_write_csr(cf_port->dma_base + DMA_CFG, dma_cfg.u64);
+
+                /* Disable the interrupt.  */
+                dma_int.u64 = 0;
+                cvmx_write_csr(cf_port->dma_base + DMA_INT_EN, dma_int.u64);
+
+                /* Clear the DMA complete status */
+                dma_int.s.done = 1;
+                cvmx_write_csr(cf_port->dma_base + DMA_INT, dma_int.u64);
+
+                __raw_writeb(0, cf_port->c0);
+                udelay(20);
+                __raw_writeb(ATA_SRST, cf_port->c0);
+                udelay(20);
+                __raw_writeb(0, cf_port->c0);
+                mdelay(100);
+        }
 }
 
+static struct of_device_id octeon_cf_match[] = {
+        {
+                .compatible = "cavium,ebt3000-compact-flash",
+        },
+        {},
+};
+MODULE_DEVICE_TABLE(of, octeon_i2c_match);
+
 static struct platform_driver octeon_cf_driver = {
         .probe          = octeon_cf_probe,
         .driver         = {
                 .name   = DRV_NAME,
                 .owner  = THIS_MODULE,
+                .of_match_table = octeon_cf_match,
+                .shutdown = octeon_cf_shutdown
         },
 };