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authorMark Langsdorf <mark.langsdorf@calxeda.com>2013-08-14 14:23:32 -0400
committerTejun Heo <tj@kernel.org>2013-08-14 16:43:30 -0400
commit2b79c56fb41d3956f672990fe83e342a809c89ab (patch)
tree4de09de58eeffe51d987fca8a94d4897e348b542 /drivers/ata
parentb2e4c7b94e2826bea435aa3107e7c44f3e68515b (diff)
sata, highbank: send extra clock cycles in SGPIO patterns
Some SGPIO PICs don't follow the standard very well and expect a certain number of clock cycles or port frames in each SGPIO pattern. Add two optional parameters in the DTB that can provide the number of extra clock cycles to be sent before and after SGPIO pattern. Read those parameters from the DTB and send the extra clock cycles. Signed-off-by: Mark Langsdorf <mark.langsdorf@calxeda.com> Acked-by: Rob Herring <rob.herring@calxeda.com> Signed-off-by: Tejun Heo <tj@kernel.org>
Diffstat (limited to 'drivers/ata')
-rw-r--r--drivers/ata/sata_highbank.c13
1 files changed, 13 insertions, 0 deletions
diff --git a/drivers/ata/sata_highbank.c b/drivers/ata/sata_highbank.c
index ba43c7217545..0849672218c9 100644
--- a/drivers/ata/sata_highbank.c
+++ b/drivers/ata/sata_highbank.c
@@ -84,6 +84,9 @@ static DEFINE_SPINLOCK(sgpio_lock);
84 84
85struct ecx_plat_data { 85struct ecx_plat_data {
86 u32 n_ports; 86 u32 n_ports;
87 /* number of extra clocks that the SGPIO PIC controller expects */
88 u32 pre_clocks;
89 u32 post_clocks;
87 unsigned sgpio_gpio[SGPIO_PINS]; 90 unsigned sgpio_gpio[SGPIO_PINS];
88 u32 sgpio_pattern; 91 u32 sgpio_pattern;
89 u32 port_to_sgpio[SGPIO_PORTS]; 92 u32 port_to_sgpio[SGPIO_PORTS];
@@ -160,6 +163,9 @@ static ssize_t ecx_transmit_led_message(struct ata_port *ap, u32 state,
160 spin_lock_irqsave(&sgpio_lock, flags); 163 spin_lock_irqsave(&sgpio_lock, flags);
161 ecx_parse_sgpio(pdata, ap->port_no, state); 164 ecx_parse_sgpio(pdata, ap->port_no, state);
162 sgpio_out = pdata->sgpio_pattern; 165 sgpio_out = pdata->sgpio_pattern;
166 for (i = 0; i < pdata->pre_clocks; i++)
167 ecx_led_cycle_clock(pdata);
168
163 gpio_set_value(pdata->sgpio_gpio[SLOAD], 1); 169 gpio_set_value(pdata->sgpio_gpio[SLOAD], 1);
164 ecx_led_cycle_clock(pdata); 170 ecx_led_cycle_clock(pdata);
165 gpio_set_value(pdata->sgpio_gpio[SLOAD], 0); 171 gpio_set_value(pdata->sgpio_gpio[SLOAD], 0);
@@ -172,6 +178,8 @@ static ssize_t ecx_transmit_led_message(struct ata_port *ap, u32 state,
172 sgpio_out >>= 1; 178 sgpio_out >>= 1;
173 ecx_led_cycle_clock(pdata); 179 ecx_led_cycle_clock(pdata);
174 } 180 }
181 for (i = 0; i < pdata->post_clocks; i++)
182 ecx_led_cycle_clock(pdata);
175 183
176 /* save off new led state for port/slot */ 184 /* save off new led state for port/slot */
177 emp->led_state = state; 185 emp->led_state = state;
@@ -206,6 +214,11 @@ static void highbank_set_em_messages(struct device *dev,
206 of_property_read_u32_array(np, "calxeda,led-order", 214 of_property_read_u32_array(np, "calxeda,led-order",
207 pdata->port_to_sgpio, 215 pdata->port_to_sgpio,
208 pdata->n_ports); 216 pdata->n_ports);
217 if (of_property_read_u32(np, "calxeda,pre-clocks", &pdata->pre_clocks))
218 pdata->pre_clocks = 0;
219 if (of_property_read_u32(np, "calxeda,post-clocks",
220 &pdata->post_clocks))
221 pdata->post_clocks = 0;
209 222
210 /* store em_loc */ 223 /* store em_loc */
211 hpriv->em_loc = 0; 224 hpriv->em_loc = 0;