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authorSonic Zhang <sonic.zhang@analog.com>2008-01-30 03:43:26 -0500
committerJeff Garzik <jeff@garzik.org>2008-02-01 12:26:41 -0500
commitf9204112586c1b9b5a5e5979d285e58a349774e0 (patch)
treebe0c082a755f2f37a8ca05a66c8935abd5cd9ef3 /drivers/ata
parenta315acdacfba4c8bbf450129eeb45766112b8009 (diff)
Blackfin pata-bf54x driver: Add debug information
Signed-off-by: Robin Getz <robin.getz@analog.com> Signed-off-by: Michael Hennerich <michael.hennerich@analog.com> Signed-off-by: Sonic Zhang <sonic.zhang@analog.com> Signed-off-by: Bryan Wu <bryan.wu@analog.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
Diffstat (limited to 'drivers/ata')
-rw-r--r--drivers/ata/pata_bf54x.c37
1 files changed, 19 insertions, 18 deletions
diff --git a/drivers/ata/pata_bf54x.c b/drivers/ata/pata_bf54x.c
index ca62bb79fa0f..d86970add683 100644
--- a/drivers/ata/pata_bf54x.c
+++ b/drivers/ata/pata_bf54x.c
@@ -299,7 +299,7 @@ static void bfin_set_piomode(struct ata_port *ap, struct ata_device *adev)
299 */ 299 */
300 n6 = num_clocks_min(t6min, fsclk); 300 n6 = num_clocks_min(t6min, fsclk);
301 if (mode >= 0 && mode <= 4 && n6 >= 1) { 301 if (mode >= 0 && mode <= 4 && n6 >= 1) {
302 pr_debug("set piomode: mode=%d, fsclk=%ud\n", mode, fsclk); 302 dev_dbg(adev->ap->dev, "set piomode: mode=%d, fsclk=%ud\n", mode, fsclk);
303 /* calculate the timing values for register transfers. */ 303 /* calculate the timing values for register transfers. */
304 while (mode > 0 && pio_fsclk[mode] > fsclk) 304 while (mode > 0 && pio_fsclk[mode] > fsclk)
305 mode--; 305 mode--;
@@ -376,7 +376,7 @@ static void bfin_set_dmamode(struct ata_port *ap, struct ata_device *adev)
376 376
377 mode = adev->dma_mode - XFER_UDMA_0; 377 mode = adev->dma_mode - XFER_UDMA_0;
378 if (mode >= 0 && mode <= 5) { 378 if (mode >= 0 && mode <= 5) {
379 pr_debug("set udmamode: mode=%d\n", mode); 379 dev_dbg(adev->ap->dev, "set udmamode: mode=%d\n", mode);
380 /* the most restrictive timing value is t6 and tc, 380 /* the most restrictive timing value is t6 and tc,
381 * the DIOW - data hold. If one SCLK pulse is longer 381 * the DIOW - data hold. If one SCLK pulse is longer
382 * than this minimum value then register 382 * than this minimum value then register
@@ -433,7 +433,7 @@ static void bfin_set_dmamode(struct ata_port *ap, struct ata_device *adev)
433 433
434 mode = adev->dma_mode - XFER_MW_DMA_0; 434 mode = adev->dma_mode - XFER_MW_DMA_0;
435 if (mode >= 0 && mode <= 2) { 435 if (mode >= 0 && mode <= 2) {
436 pr_debug("set mdmamode: mode=%d\n", mode); 436 dev_dbg(adev->ap->dev, "set mdmamode: mode=%d\n", mode);
437 /* the most restrictive timing value is tf, the DMACK to 437 /* the most restrictive timing value is tf, the DMACK to
438 * read data released. If one SCLK pulse is longer than 438 * read data released. If one SCLK pulse is longer than
439 * this maximum value then the MDMA mode 439 * this maximum value then the MDMA mode
@@ -697,7 +697,7 @@ static void bfin_tf_load(struct ata_port *ap, const struct ata_taskfile *tf)
697 write_atapi_register(base, ATA_REG_LBAL, tf->hob_lbal); 697 write_atapi_register(base, ATA_REG_LBAL, tf->hob_lbal);
698 write_atapi_register(base, ATA_REG_LBAM, tf->hob_lbam); 698 write_atapi_register(base, ATA_REG_LBAM, tf->hob_lbam);
699 write_atapi_register(base, ATA_REG_LBAH, tf->hob_lbah); 699 write_atapi_register(base, ATA_REG_LBAH, tf->hob_lbah);
700 pr_debug("hob: feat 0x%X nsect 0x%X, lba 0x%X " 700 dev_dbg(ap->dev, "hob: feat 0x%X nsect 0x%X, lba 0x%X "
701 "0x%X 0x%X\n", 701 "0x%X 0x%X\n",
702 tf->hob_feature, 702 tf->hob_feature,
703 tf->hob_nsect, 703 tf->hob_nsect,
@@ -711,7 +711,7 @@ static void bfin_tf_load(struct ata_port *ap, const struct ata_taskfile *tf)
711 write_atapi_register(base, ATA_REG_LBAL, tf->lbal); 711 write_atapi_register(base, ATA_REG_LBAL, tf->lbal);
712 write_atapi_register(base, ATA_REG_LBAM, tf->lbam); 712 write_atapi_register(base, ATA_REG_LBAM, tf->lbam);
713 write_atapi_register(base, ATA_REG_LBAH, tf->lbah); 713 write_atapi_register(base, ATA_REG_LBAH, tf->lbah);
714 pr_debug("feat 0x%X nsect 0x%X lba 0x%X 0x%X 0x%X\n", 714 dev_dbg(ap->dev, "feat 0x%X nsect 0x%X lba 0x%X 0x%X 0x%X\n",
715 tf->feature, 715 tf->feature,
716 tf->nsect, 716 tf->nsect,
717 tf->lbal, 717 tf->lbal,
@@ -721,7 +721,7 @@ static void bfin_tf_load(struct ata_port *ap, const struct ata_taskfile *tf)
721 721
722 if (tf->flags & ATA_TFLAG_DEVICE) { 722 if (tf->flags & ATA_TFLAG_DEVICE) {
723 write_atapi_register(base, ATA_REG_DEVICE, tf->device); 723 write_atapi_register(base, ATA_REG_DEVICE, tf->device);
724 pr_debug("device 0x%X\n", tf->device); 724 dev_dbg(ap->dev, "device 0x%X\n", tf->device);
725 } 725 }
726 726
727 ata_wait_idle(ap); 727 ata_wait_idle(ap);
@@ -782,7 +782,7 @@ static void bfin_exec_command(struct ata_port *ap,
782 const struct ata_taskfile *tf) 782 const struct ata_taskfile *tf)
783{ 783{
784 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr; 784 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
785 pr_debug("ata%u: cmd 0x%X\n", ap->print_id, tf->command); 785 dev_dbg(ap->dev, "ata%u: cmd 0x%X\n", ap->print_id, tf->command);
786 786
787 write_atapi_register(base, ATA_REG_CMD, tf->command); 787 write_atapi_register(base, ATA_REG_CMD, tf->command);
788 ata_pause(ap); 788 ata_pause(ap);
@@ -834,7 +834,7 @@ static void bfin_bmdma_setup(struct ata_queued_cmd *qc)
834 struct scatterlist *sg; 834 struct scatterlist *sg;
835 unsigned int si; 835 unsigned int si;
836 836
837 pr_debug("in atapi dma setup\n"); 837 dev_dbg(qc->ap->dev, "in atapi dma setup\n");
838 /* Program the ATA_CTRL register with dir */ 838 /* Program the ATA_CTRL register with dir */
839 if (qc->tf.flags & ATA_TFLAG_WRITE) { 839 if (qc->tf.flags & ATA_TFLAG_WRITE) {
840 /* fill the ATAPI DMA controller */ 840 /* fill the ATAPI DMA controller */
@@ -870,7 +870,7 @@ static void bfin_bmdma_start(struct ata_queued_cmd *qc)
870 struct scatterlist *sg; 870 struct scatterlist *sg;
871 unsigned int si; 871 unsigned int si;
872 872
873 pr_debug("in atapi dma start\n"); 873 dev_dbg(qc->ap->dev, "in atapi dma start\n");
874 if (!(ap->udma_mask || ap->mwdma_mask)) 874 if (!(ap->udma_mask || ap->mwdma_mask))
875 return; 875 return;
876 876
@@ -888,7 +888,7 @@ static void bfin_bmdma_start(struct ata_queued_cmd *qc)
888 sg_dma_address(sg) + sg_dma_len(sg)); 888 sg_dma_address(sg) + sg_dma_len(sg));
889 } 889 }
890 enable_dma(CH_ATAPI_TX); 890 enable_dma(CH_ATAPI_TX);
891 pr_debug("enable udma write\n"); 891 dev_dbg(qc->ap->dev, "enable udma write\n");
892 892
893 /* Send ATA DMA write command */ 893 /* Send ATA DMA write command */
894 bfin_exec_command(ap, &qc->tf); 894 bfin_exec_command(ap, &qc->tf);
@@ -898,7 +898,7 @@ static void bfin_bmdma_start(struct ata_queued_cmd *qc)
898 | XFER_DIR)); 898 | XFER_DIR));
899 } else { 899 } else {
900 enable_dma(CH_ATAPI_RX); 900 enable_dma(CH_ATAPI_RX);
901 pr_debug("enable udma read\n"); 901 dev_dbg(qc->ap->dev, "enable udma read\n");
902 902
903 /* Send ATA DMA read command */ 903 /* Send ATA DMA read command */
904 bfin_exec_command(ap, &qc->tf); 904 bfin_exec_command(ap, &qc->tf);
@@ -936,7 +936,7 @@ static void bfin_bmdma_stop(struct ata_queued_cmd *qc)
936 struct scatterlist *sg; 936 struct scatterlist *sg;
937 unsigned int si; 937 unsigned int si;
938 938
939 pr_debug("in atapi dma stop\n"); 939 dev_dbg(qc->ap->dev, "in atapi dma stop\n");
940 if (!(ap->udma_mask || ap->mwdma_mask)) 940 if (!(ap->udma_mask || ap->mwdma_mask))
941 return; 941 return;
942 942
@@ -1157,6 +1157,8 @@ static unsigned char bfin_bmdma_status(struct ata_port *ap)
1157 host_stat |= ATA_DMA_ERR; 1157 host_stat |= ATA_DMA_ERR;
1158 } 1158 }
1159 1159
1160 dev_dbg(ap->dev, "ATAPI: host_stat=0x%x\n", host_stat);
1161
1160 return host_stat; 1162 return host_stat;
1161} 1163}
1162 1164
@@ -1213,8 +1215,7 @@ static void bfin_irq_clear(struct ata_port *ap)
1213{ 1215{
1214 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr; 1216 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
1215 1217
1216 pr_debug("in atapi irq clear\n"); 1218 dev_dbg(ap->dev, "in atapi irq clear\n");
1217
1218 ATAPI_SET_INT_STATUS(base, ATAPI_GET_INT_STATUS(base)|ATAPI_DEV_INT 1219 ATAPI_SET_INT_STATUS(base, ATAPI_GET_INT_STATUS(base)|ATAPI_DEV_INT
1219 | MULTI_DONE_INT | UDMAIN_DONE_INT | UDMAOUT_DONE_INT 1220 | MULTI_DONE_INT | UDMAIN_DONE_INT | UDMAOUT_DONE_INT
1220 | MULTI_TERM_INT | UDMAIN_TERM_INT | UDMAOUT_TERM_INT); 1221 | MULTI_TERM_INT | UDMAIN_TERM_INT | UDMAOUT_TERM_INT);
@@ -1232,7 +1233,7 @@ static unsigned char bfin_irq_on(struct ata_port *ap)
1232 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr; 1233 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
1233 u8 tmp; 1234 u8 tmp;
1234 1235
1235 pr_debug("in atapi irq on\n"); 1236 dev_dbg(ap->dev, "in atapi irq on\n");
1236 ap->ctl &= ~ATA_NIEN; 1237 ap->ctl &= ~ATA_NIEN;
1237 ap->last_ctl = ap->ctl; 1238 ap->last_ctl = ap->ctl;
1238 1239
@@ -1255,7 +1256,7 @@ static void bfin_bmdma_freeze(struct ata_port *ap)
1255{ 1256{
1256 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr; 1257 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
1257 1258
1258 pr_debug("in atapi dma freeze\n"); 1259 dev_dbg(ap->dev, "in atapi dma freeze\n");
1259 ap->ctl |= ATA_NIEN; 1260 ap->ctl |= ATA_NIEN;
1260 ap->last_ctl = ap->ctl; 1261 ap->last_ctl = ap->ctl;
1261 1262
@@ -1328,7 +1329,7 @@ static void bfin_error_handler(struct ata_port *ap)
1328 1329
1329static void bfin_port_stop(struct ata_port *ap) 1330static void bfin_port_stop(struct ata_port *ap)
1330{ 1331{
1331 pr_debug("in atapi port stop\n"); 1332 dev_dbg(ap->dev, "in atapi port stop\n");
1332 if (ap->udma_mask != 0 || ap->mwdma_mask != 0) { 1333 if (ap->udma_mask != 0 || ap->mwdma_mask != 0) {
1333 free_dma(CH_ATAPI_RX); 1334 free_dma(CH_ATAPI_RX);
1334 free_dma(CH_ATAPI_TX); 1335 free_dma(CH_ATAPI_TX);
@@ -1337,7 +1338,7 @@ static void bfin_port_stop(struct ata_port *ap)
1337 1338
1338static int bfin_port_start(struct ata_port *ap) 1339static int bfin_port_start(struct ata_port *ap)
1339{ 1340{
1340 pr_debug("in atapi port start\n"); 1341 dev_dbg(ap->dev, "in atapi port start\n");
1341 if (!(ap->udma_mask || ap->mwdma_mask)) 1342 if (!(ap->udma_mask || ap->mwdma_mask))
1342 return 0; 1343 return 0;
1343 1344