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authorBryan Wu <bryan.wu@analog.com>2008-01-30 03:43:28 -0500
committerJeff Garzik <jeff@garzik.org>2008-02-01 12:26:43 -0500
commit9f24e82d07e2c64467d0c0c04a798de56461fd4a (patch)
tree7ef1e16f5f829805d99906e9548632aca541a45d /drivers/ata
parent30d849c95f0598309ca6451900b1fd0d2c0384e6 (diff)
Blackfin pata-bf54x driver: fix compiling bug - no ata_port struct in struct ata_device any more
Cc: Sonic Zhang <sonic.zhang@analog.com> Signed-off-by: Bryan Wu <bryan.wu@analog.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
Diffstat (limited to 'drivers/ata')
-rw-r--r--drivers/ata/pata_bf54x.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/ata/pata_bf54x.c b/drivers/ata/pata_bf54x.c
index d66f7733b796..7f87f105c2f6 100644
--- a/drivers/ata/pata_bf54x.c
+++ b/drivers/ata/pata_bf54x.c
@@ -299,7 +299,7 @@ static void bfin_set_piomode(struct ata_port *ap, struct ata_device *adev)
299 */ 299 */
300 n6 = num_clocks_min(t6min, fsclk); 300 n6 = num_clocks_min(t6min, fsclk);
301 if (mode >= 0 && mode <= 4 && n6 >= 1) { 301 if (mode >= 0 && mode <= 4 && n6 >= 1) {
302 dev_dbg(adev->ap->dev, "set piomode: mode=%d, fsclk=%ud\n", mode, fsclk); 302 dev_dbg(adev->link->ap->dev, "set piomode: mode=%d, fsclk=%ud\n", mode, fsclk);
303 /* calculate the timing values for register transfers. */ 303 /* calculate the timing values for register transfers. */
304 while (mode > 0 && pio_fsclk[mode] > fsclk) 304 while (mode > 0 && pio_fsclk[mode] > fsclk)
305 mode--; 305 mode--;
@@ -376,7 +376,7 @@ static void bfin_set_dmamode(struct ata_port *ap, struct ata_device *adev)
376 376
377 mode = adev->dma_mode - XFER_UDMA_0; 377 mode = adev->dma_mode - XFER_UDMA_0;
378 if (mode >= 0 && mode <= 5) { 378 if (mode >= 0 && mode <= 5) {
379 dev_dbg(adev->ap->dev, "set udmamode: mode=%d\n", mode); 379 dev_dbg(adev->link->ap->dev, "set udmamode: mode=%d\n", mode);
380 /* the most restrictive timing value is t6 and tc, 380 /* the most restrictive timing value is t6 and tc,
381 * the DIOW - data hold. If one SCLK pulse is longer 381 * the DIOW - data hold. If one SCLK pulse is longer
382 * than this minimum value then register 382 * than this minimum value then register
@@ -433,7 +433,7 @@ static void bfin_set_dmamode(struct ata_port *ap, struct ata_device *adev)
433 433
434 mode = adev->dma_mode - XFER_MW_DMA_0; 434 mode = adev->dma_mode - XFER_MW_DMA_0;
435 if (mode >= 0 && mode <= 2) { 435 if (mode >= 0 && mode <= 2) {
436 dev_dbg(adev->ap->dev, "set mdmamode: mode=%d\n", mode); 436 dev_dbg(adev->link->ap->dev, "set mdmamode: mode=%d\n", mode);
437 /* the most restrictive timing value is tf, the DMACK to 437 /* the most restrictive timing value is tf, the DMACK to
438 * read data released. If one SCLK pulse is longer than 438 * read data released. If one SCLK pulse is longer than
439 * this maximum value then the MDMA mode 439 * this maximum value then the MDMA mode