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authorMikael Pettersson <mikpe@it.uu.se>2007-01-13 15:31:05 -0500
committerJeff Garzik <jeff@garzik.org>2007-02-09 17:39:34 -0500
commit4113bb6b67ced963b3269a72f335dd278543b56d (patch)
treeda9fc29744ac5e02cb95e7652c059f0217cffcf3 /drivers/ata
parent73fd456b2dd770ab4fcf14b9d45b7482237a2cf7 (diff)
sata_promise: issue ATAPI commands as normal packets
This patch (against libata #upstream + the ATAPI cleanup patch) reimplements sata_promise's ATAPI support to format ATAPI DMA commands as normal packets, and to issue them via the hardware's normal packet machinery. It turns out that the only reason for issuing ATAPI DMA commands via the pdc_issue_atapi_pkt_cmd() procedure was to perform two interrupt-fiddling steps for ATA_DFLAG_CDB_INTR devices. But these steps aren't needed because sata_promise sets ATA_FLAG_PIO_POLLING, which disables DMA for those devices. The remaining steps can easily be done in ATA taskfile packets. Concrete changes: - pdc_atapi_dma_pkt() is extended to program all packet setup steps, and not just contain the CDB; the sequence of steps exactly mirrors what pdc_issue_atapi_pkt_cmd() did - pdc_atapi_dma_pkt() needed more parameters: simplify it by just passing 'qc' and having it extract the data it needs - pdc_issue_atai_pkt_cmd() and its two helper procedures pdc_wait_for_drq() and pdc_wait_on_busy() are removed Tested on first- and second-generation chips, SATAPI and PATAPI, with no observable regressions. Signed-off-by: Mikael Pettersson <mikpe@it.uu.se> Signed-off-by: Jeff Garzik <jeff@garzik.org>
Diffstat (limited to 'drivers/ata')
-rw-r--r--drivers/ata/sata_promise.c162
1 files changed, 60 insertions, 102 deletions
diff --git a/drivers/ata/sata_promise.c b/drivers/ata/sata_promise.c
index 4c09d6504f0c..9d73cb9de42a 100644
--- a/drivers/ata/sata_promise.c
+++ b/drivers/ata/sata_promise.c
@@ -448,28 +448,80 @@ static void pdc_sata_scr_write (struct ata_port *ap, unsigned int sc_reg,
448 writel(val, (void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4)); 448 writel(val, (void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4));
449} 449}
450 450
451static void pdc_atapi_dma_pkt(struct ata_taskfile *tf, 451static void pdc_atapi_dma_pkt(struct ata_queued_cmd *qc)
452 dma_addr_t sg_table,
453 unsigned int cdb_len, u8 *cdb,
454 u8 *buf)
455{ 452{
453 struct ata_port *ap = qc->ap;
454 dma_addr_t sg_table = ap->prd_dma;
455 unsigned int cdb_len = qc->dev->cdb_len;
456 u8 *cdb = qc->cdb;
457 struct pdc_port_priv *pp = ap->private_data;
458 u8 *buf = pp->pkt;
456 u32 *buf32 = (u32 *) buf; 459 u32 *buf32 = (u32 *) buf;
460 unsigned int dev_sel, feature, nbytes;
457 461
458 /* set control bits (byte 0), zero delay seq id (byte 3), 462 /* set control bits (byte 0), zero delay seq id (byte 3),
459 * and seq id (byte 2) 463 * and seq id (byte 2)
460 */ 464 */
461 if (!(tf->flags & ATA_TFLAG_WRITE)) 465 if (!(qc->tf.flags & ATA_TFLAG_WRITE))
462 buf32[0] = cpu_to_le32(PDC_PKT_READ); 466 buf32[0] = cpu_to_le32(PDC_PKT_READ);
463 else 467 else
464 buf32[0] = 0; 468 buf32[0] = 0;
465 buf32[1] = cpu_to_le32(sg_table); /* S/G table addr */ 469 buf32[1] = cpu_to_le32(sg_table); /* S/G table addr */
466 buf32[2] = 0; /* no next-packet */ 470 buf32[2] = 0; /* no next-packet */
467 471
472 /* select drive */
473 if (sata_scr_valid(ap)) {
474 dev_sel = PDC_DEVICE_SATA;
475 } else {
476 dev_sel = ATA_DEVICE_OBS;
477 if (qc->dev->devno != 0)
478 dev_sel |= ATA_DEV1;
479 }
480 buf[12] = (1 << 5) | ATA_REG_DEVICE;
481 buf[13] = dev_sel;
482 buf[14] = (1 << 5) | ATA_REG_DEVICE | PDC_PKT_CLEAR_BSY;
483 buf[15] = dev_sel; /* once more, waiting for BSY to clear */
484
485 buf[16] = (1 << 5) | ATA_REG_NSECT;
486 buf[17] = 0x00;
487 buf[18] = (1 << 5) | ATA_REG_LBAL;
488 buf[19] = 0x00;
489
490 /* set feature and byte counter registers */
491 if (qc->tf.protocol != ATA_PROT_ATAPI_DMA) {
492 feature = PDC_FEATURE_ATAPI_PIO;
493 /* set byte counter register to real transfer byte count */
494 nbytes = qc->nbytes;
495 if (!nbytes)
496 nbytes = qc->nsect << 9;
497 if (nbytes > 0xffff)
498 nbytes = 0xffff;
499 } else {
500 feature = PDC_FEATURE_ATAPI_DMA;
501 /* set byte counter register to 0 */
502 nbytes = 0;
503 }
504 buf[20] = (1 << 5) | ATA_REG_FEATURE;
505 buf[21] = feature;
506 buf[22] = (1 << 5) | ATA_REG_BYTEL;
507 buf[23] = nbytes & 0xFF;
508 buf[24] = (1 << 5) | ATA_REG_BYTEH;
509 buf[25] = (nbytes >> 8) & 0xFF;
510
511 /* send ATAPI packet command 0xA0 */
512 buf[26] = (1 << 5) | ATA_REG_CMD;
513 buf[27] = ATA_CMD_PACKET;
514
515 /* select drive and check DRQ */
516 buf[28] = (1 << 5) | ATA_REG_DEVICE | PDC_PKT_WAIT_DRDY;
517 buf[29] = dev_sel;
518
468 /* we can represent cdb lengths 2/4/6/8/10/12/14/16 */ 519 /* we can represent cdb lengths 2/4/6/8/10/12/14/16 */
469 BUG_ON(cdb_len & ~0x1E); 520 BUG_ON(cdb_len & ~0x1E);
470 521
471 buf[12] = (((cdb_len >> 1) & 7) << 5) | ATA_REG_DATA | PDC_LAST_REG; 522 /* append the CDB as the final part */
472 memcpy(buf+13, cdb, cdb_len); 523 buf[30] = (((cdb_len >> 1) & 7) << 5) | ATA_REG_DATA | PDC_LAST_REG;
524 memcpy(buf+31, cdb, cdb_len);
473} 525}
474 526
475static void pdc_qc_prep(struct ata_queued_cmd *qc) 527static void pdc_qc_prep(struct ata_queued_cmd *qc)
@@ -503,7 +555,7 @@ static void pdc_qc_prep(struct ata_queued_cmd *qc)
503 555
504 case ATA_PROT_ATAPI_DMA: 556 case ATA_PROT_ATAPI_DMA:
505 ata_qc_prep(qc); 557 ata_qc_prep(qc);
506 pdc_atapi_dma_pkt(&qc->tf, qc->ap->prd_dma, qc->dev->cdb_len, qc->cdb, pp->pkt); 558 pdc_atapi_dma_pkt(qc);
507 break; 559 break;
508 560
509 default: 561 default:
@@ -716,104 +768,10 @@ static inline void pdc_packet_start(struct ata_queued_cmd *qc)
716 readl((void __iomem *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT); /* flush */ 768 readl((void __iomem *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT); /* flush */
717} 769}
718 770
719static unsigned int pdc_wait_for_drq(struct ata_port *ap)
720{
721 void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
722 unsigned int i;
723 unsigned int status;
724
725 /* Following pdc-ultra's WaitForDrq() we loop here until BSY
726 * is clear and DRQ is set in altstatus. We could possibly call
727 * ata_busy_wait() and loop until DRQ is set, but since we don't
728 * know how much time a call to ata_busy_wait() took, we don't
729 * know when to time out the outer loop.
730 */
731 for(i = 0; i < 1000; ++i) {
732 status = readb(port_mmio + PDC_ALTSTATUS);
733 if (status == 0xFF)
734 break;
735 if (status & ATA_BUSY)
736 ;
737 else if (status & (ATA_DRQ | ATA_ERR))
738 break;
739 mdelay(1);
740 }
741 if (i >= 1000)
742 ata_port_printk(ap, KERN_WARNING, "%s timed out\n", __FUNCTION__);
743 return status;
744}
745
746static unsigned int pdc_wait_on_busy(struct ata_port *ap)
747{
748 unsigned int status = ata_busy_wait(ap, ATA_BUSY, 1000);
749 if (status != 0xff && (status & ATA_BUSY))
750 ata_port_printk(ap, KERN_WARNING, "%s timed out\n", __FUNCTION__);
751 return status;
752}
753
754static void pdc_issue_atapi_pkt_cmd(struct ata_queued_cmd *qc)
755{
756 struct ata_port *ap = qc->ap;
757 void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
758 void __iomem *host_mmio = ap->host->mmio_base;
759 unsigned int nbytes;
760 unsigned int tmp;
761
762 writeb(0x00, port_mmio + PDC_CTLSTAT); /* route drive INT to SEQ 0 */
763 writeb(PDC_SEQCNTRL_INT_MASK, host_mmio + 0); /* but mask SEQ 0 INT */
764
765 /* select drive */
766 if (sata_scr_valid(ap)) {
767 tmp = PDC_DEVICE_SATA;
768 } else {
769 tmp = ATA_DEVICE_OBS;
770 if (qc->dev->devno != 0)
771 tmp |= ATA_DEV1;
772 }
773 writeb(tmp, port_mmio + PDC_DEVICE);
774 pdc_wait_on_busy(ap);
775
776 writeb(0x00, port_mmio + PDC_SECTOR_COUNT);
777 writeb(0x00, port_mmio + PDC_SECTOR_NUMBER);
778
779 /* set feature and byte counter registers */
780 if (qc->tf.protocol != ATA_PROT_ATAPI_DMA) {
781 tmp = PDC_FEATURE_ATAPI_PIO;
782 /* set byte counter register to real transfer byte count */
783 nbytes = qc->nbytes;
784 if (!nbytes)
785 nbytes = qc->nsect << 9;
786 if (nbytes > 0xffff)
787 nbytes = 0xffff;
788 } else {
789 tmp = PDC_FEATURE_ATAPI_DMA;
790 /* set byte counter register to 0 */
791 nbytes = 0;
792 }
793 writeb(tmp, port_mmio + PDC_FEATURE);
794 writeb(nbytes & 0xFF, port_mmio + PDC_CYLINDER_LOW);
795 writeb((nbytes >> 8) & 0xFF, port_mmio + PDC_CYLINDER_HIGH);
796
797 /* send ATAPI packet command 0xA0 */
798 writeb(ATA_CMD_PACKET, port_mmio + PDC_COMMAND);
799
800 /* pdc_qc_issue_prot() currently sends ATAPI PIO packets back
801 * to libata. If we start handling those packets ourselves,
802 * then we must busy-wait for INT (CTLSTAT bit 27) at this point
803 * if the device has ATA_DFLAG_CDB_INTR set.
804 */
805
806 pdc_wait_for_drq(ap);
807
808 /* now the device only waits for the CDB */
809}
810
811static unsigned int pdc_qc_issue_prot(struct ata_queued_cmd *qc) 771static unsigned int pdc_qc_issue_prot(struct ata_queued_cmd *qc)
812{ 772{
813 switch (qc->tf.protocol) { 773 switch (qc->tf.protocol) {
814 case ATA_PROT_ATAPI_DMA: 774 case ATA_PROT_ATAPI_DMA:
815 pdc_issue_atapi_pkt_cmd(qc);
816 /*FALLTHROUGH*/
817 case ATA_PROT_DMA: 775 case ATA_PROT_DMA:
818 case ATA_PROT_NODATA: 776 case ATA_PROT_NODATA:
819 pdc_packet_start(qc); 777 pdc_packet_start(qc);